Lines Matching defs:Regs

88   void EmitRegMapping(raw_ostream &OS, const std::deque<CodeGenRegister> &Regs,
91                             const std::deque<CodeGenRegister> &Regs,
212     const CodeGenRegister::Vec &Regs = RC.getMembers();
214     if (Regs.empty() || RC.Artificial)
375     raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
381   for (auto &RE : Regs) {
397   StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace");
442   for (auto &RE : Regs) {
502     raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
506   for (auto &RE : Regs) {
515   StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace");
864   const auto &Regs = RegBank.getRegisters();
873   SmallVector<DiffVec, 4> SubRegLists(Regs.size());
874   SmallVector<DiffVec, 4> SuperRegLists(Regs.size());
875   SmallVector<DiffVec, 4> RegUnitLists(Regs.size());
879   SmallVector<MaskVec, 4> RegUnitLaneMasks(Regs.size());
886   SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size());
892   for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) {
959   for (const auto &Reg : Regs) {
1054   EmitRegMappingTables(OS, Regs, false);
1061   for (const auto &RE : Regs) {
1079      << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, "
1087   EmitRegMapping(OS, Regs, false);
1428   const auto &Regs = RegBank.getRegisters();
1430   for (const auto &Reg : Regs)
1434   llvm::BitVector InAllocClass(Regs.size() + 1, false);
1440   for (const auto &Reg : Regs) {
1453   // Size of the emitted array should be NumRegCosts * (Regs.size() + 1).
1594       OS << "  static const uint16_t Mapping[" << Regs.size() + 1 << "] = {\n";
1596       for (const CodeGenRegister &Reg : Regs) {
1629   EmitRegMappingTables(OS, Regs, true);
1642      << "  InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1
1655   EmitRegMapping(OS, Regs, true);
1663     const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
1664     assert(Regs && "Cannot expand CalleeSavedRegs instance");
1668     for (const Record *Reg : *Regs)
1673     BitVector Covered = RegBank.computeCoveredRegisters(*Regs);
1772   for (const auto &Reg : Regs)