Lines Matching defs:Regs

215   RegUnitIterator(const CodeGenRegister::Vec &Regs)
216       : RegI(Regs.begin()), RegE(Regs.end()) {
1207   std::vector<const Record *> Regs = RC.getAllDerivedDefinitions("Register");
1208   if (!Regs.empty() && Regs[0]->isSubClassOf("X86Reg")) {
1217       Regs.insert(Regs.end(), TupRegs.begin(), TupRegs.end());
1220     llvm::sort(Regs, LessRecordRegister());
1222     for (unsigned i = 0, e = Regs.size(); i != e; ++i)
1223       getReg(Regs[i]);
1225     llvm::sort(Regs, LessRecordRegister());
1227     for (unsigned i = 0, e = Regs.size(); i != e; ++i)
1228       getReg(Regs[i]);
1711   CodeGenRegister::Vec Regs;
1740     const CodeGenRegister::Vec &Regs = RegClass.getMembers();
1741     if (Regs.empty())
1744     unsigned USetID = UberSetIDs.findLeader((*Regs.begin())->EnumValue);
1747     AllocatableRegs.set((*Regs.begin())->EnumValue);
1748     for (const CodeGenRegister *CGR : llvm::drop_begin(Regs)) {
1778     USet->Regs.push_back(&Reg);
1794     for (RegUnitIterator UnitI(I->Regs); UnitI.isValid(); ++UnitI) {
1816                       : I->Regs) dbgs()
1824     for (const auto R : I->Regs) {
2510 CodeGenRegBank::computeCoveredRegisters(ArrayRef<const Record *> Regs) {
2513   // First add Regs with all sub-registers.
2514   for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
2515     CodeGenRegister *Reg = getReg(Regs[i]);