| /llvm-project/llvm/tools/llvm-exegesis/lib/ |
| H A D | RegisterAliasing.cpp | 33 const MCRegisterClass &RegClass) in RegisterAliasingTracker() argument
76 const auto &RegClass = RegInfo.getRegClass(RegClassIndex); in getRegisterClass() local
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| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 46 std::unique_ptr<RCInfo[]> RegClass; variable
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| H A D | RDFRegisters.h | 183 const TargetRegisterClass *RegClass = nullptr; member
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| /llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyPeephole.cpp | 98 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough() local
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| H A D | WebAssemblyRegStackify.cpp | 641 Register DefReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse() local
105 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); convertImplicitDefToConstZero() local
[all...] |
| /llvm-project/llvm/lib/CodeGen/ |
| H A D | RenameIndependentSubregs.cpp | 134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in INITIALIZE_PASS_DEPENDENCY() local
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| H A D | MachineRegisterInfo.cpp | 159 assert(RegClass->isAllocatable() && in createVirtualRegister() argument
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| H A D | TargetInstrInfo.cpp | 54 short RegClass = MCID.operands()[OpNum].RegClass; in getRegClass() local
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| /llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelDAGToDAG.cpp | 385 SDValue RegClass = in createGPRPairNode() local
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUMachineCFGStructurizer.cpp | |
| H A D | GCNDPPCombine.cpp | 197 int16_t RegClass = MI.getDesc().operands()[Idx].RegClass; getOperandSize() local
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64LoadStoreOptimizer.cpp | 1425 auto *RegClass = TRI->getMinimalPhysRegClass(MOP.getReg()); canRenameMOP() local
1628 auto *RegClass = TRI->getMinimalPhysRegClass(Reg); tryToFindRegisterToRename() local
1656 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); findRenameRegForSameLdStRegPair() local
[all...] |
| H A D | AArch64AsmPrinter.cpp | 1075 const TargetRegisterClass *RegClass; PrintAsmOperand() local
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| /llvm-project/llvm/include/llvm/IR/ |
| H A D | InlineAsm.h | 309 using RegClass = Bitfield::Element<unsigned, 16, 14>; variable
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb2InstrInfo.cpp | 562 const TargetRegisterClass *RegClass = rewriteT2FrameIndex() local
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| H A D | ARMISelDAGToDAG.cpp | 1855 SDValue RegClass = createGPRPairNode() local
1866 SDValue RegClass = createSRegPairNode() local
1877 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, createDRegPairNode() local
1888 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, createQRegPairNode() local
1900 SDValue RegClass = createQuadSRegsNode() local
1915 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, createQuadDRegsNode() local
1930 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, createQuadQRegsNode() local
[all...] |
| H A D | MVETPAndVPTOptimisationsPass.cpp | 617 return RegClass && (RegClass->getID() == ARM::VCCRRegClassID); in IsWritingToVCCR() local
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| H A D | ARMBaseRegisterInfo.cpp | 855 const TargetRegisterClass *RegClass = eliminateFrameIndex() local
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| /llvm-project/llvm/utils/TableGen/ |
| H A D | CompressInstEmitter.cpp | 151 validateRegister(Record * Reg,Record * RegClass) validateRegister() argument
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| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 49 const TargetRegisterClass &RegClass) { in constrainRegToClass() argument
60 const TargetRegisterClass &RegClass, MachineOperand &RegMO) { in constrainOperandRegClass() argument
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| /llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 146 DECODE_OPERAND_REG_8(RegClass) global() argument
181 DECODE_OPERAND_REG_7(RegClass,OpWidth) global() argument
[all...] |
| /llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.cpp | 1675 for (auto &RegClass : RegClasses) { in computeSubRegLaneMasks() local
1736 for (auto &RegClass : RegBank.getRegClasses()) { in computeUberSets() local
[all...] |
| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FrameLowering.cpp | 955 const TargetRegisterClass *RegClass = &X86::GR64RegClass; emitStackProbeInlineWindowsCoreCLR64() local
3683 auto &RegClass = adjustStackWithPops() local
[all...] |
| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCRegisterInfo.cpp | 590 const TargetRegisterClass *RegClass = MRI->getRegClass(VirtReg); getRegAllocationHints() local
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| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 385 __anon099186b20202(const TargetRegisterClass &RegClass, uint16_t Encoding) copyPhysRegVector() argument
549 for (const auto &RegClass : RVVRegClasses) { copyPhysReg() local
[all...] |