Lines Matching defs:RegClass

144 #define DECODE_OPERAND_REG_8(RegClass)                                         \
145   static DecodeStatus Decode##RegClass##RegisterClass(                         \
151         Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm));      \
179 #define DECODE_OPERAND_REG_7(RegClass, OpWidth)                                \
180   DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0)
223 // register from RegClass or immediate. Registers that don't belong to RegClass
256 // Default decoders generated by tablegen: 'Decode<RegClass>RegisterClass'
756             MCII->get(MI.getOpcode()).operands()[VAddrIdx].RegClass;
1155     auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass;
1181     auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass;