| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitTracker.cpp | 92 const TargetRegisterClass &RC = *MRI.getRegClass(Reg); in mask() local
123 if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg)) in getPhysRegBitWidth() local
131 const TargetRegisterClass &RC, unsigned Idx) const { in composeWithSubRegIndex() argument
281 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate()
288 auto half = [this] (const BT::RegisterCell &RC, unsigned N) in evaluate()
289 -> BT::RegisterCell { in evaluate()
298 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate() local
333 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate() local
349 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1)); in evaluate() local
356 RegisterCell RC = RegisterCell::self(Reg[0].Reg, RW); in evaluate() local
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| H A D | HexagonConstPropagation.cpp | 718 LatticeCell RC = Cells.get(DefR.Reg); in visitNonBranch() local
1080 LatticeCell &RC) { in getCell()
1390 LatticeCell RC; in evaluateANDrr() local
1406 LatticeCell RC; in evaluateANDri() local
1457 LatticeCell RC; in evaluateORrr() local
1473 LatticeCell RC; in evaluateORri() local
1522 LatticeCell RC; in evaluateXORrr() local
1941 LatticeCell RC; in evaluate() local
1963 LatticeCell RC; in evaluate() local
1997 LatticeCell RC = Outputs.get(DefR.Reg); in evaluate() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 198 static bool isSGPRClass(const TargetRegisterClass *RC) { in isSGPRClass()
210 static bool isVGPRClass(const TargetRegisterClass *RC) { in isVGPRClass()
215 static bool isAGPRClass(const TargetRegisterClass *RC) { in isAGPRClass()
220 bool isVectorSuperClass(const TargetRegisterClass *RC) const { in isVectorSuperClass()
225 bool isVSSuperClass(const TargetRegisterClass *RC) const { in isVSSuperClass()
230 static bool hasVGPRs(const TargetRegisterClass *RC) { in hasVGPRs()
235 static bool hasAGPRs(const TargetRegisterClass *RC) { in hasAGPRs()
240 static bool hasSGPRs(const TargetRegisterClass *RC) { in hasSGPRs()
245 static bool hasVectorRegisters(const TargetRegisterClass *RC) { in hasVectorRegisters()
305 bool isDivergentRegClass(const TargetRegisterClass *RC) const override { in isDivergentRegClass()
[all …]
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| H A D | GCNRewritePartialRegUses.cpp | 81 const TargetRegisterClass *RC; member
187 getSuperRegClassMask(const TargetRegisterClass * RC,unsigned SubRegIdx) const getSuperRegClassMask() argument
210 auto *RC = TRI->getRegClass(ClassID); getAllocatableAndAlignedRegClassMask() local
220 getRegClassWithShiftedSubregs(const TargetRegisterClass * RC,unsigned RShift,unsigned RegNumBits,unsigned CoverSubregIdx,SubRegMap & SubRegs) const getRegClassWithShiftedSubregs() argument
271 auto *RC = TRI->getRegClass(ClassID); getRegClassWithShiftedSubregs() local
294 getMinSizeReg(const TargetRegisterClass * RC,SubRegMap & SubRegs) const getMinSizeReg() argument
418 auto *RC = MRI->getRegClass(Reg); rewriteReg() local
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| H A D | SILowerSGPRSpills.cpp | 105 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass( in insertCSRSaves() local
146 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass( in insertCSRRestores() local
235 const TargetRegisterClass *RC = in spillCalleeSavedRegs() local
427 const TargetRegisterClass *RC = TRI->getWaveMaskRegClass(); runOnMachineFunction() local
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| /freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 78 const RCInfo &get(const TargetRegisterClass *RC) const { in get() argument
94 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs() argument
101 getOrder(const TargetRegisterClass * RC) getOrder() argument
111 isProperSubClass(const TargetRegisterClass * RC) isProperSubClass() argument
127 getMinCost(const TargetRegisterClass * RC) getMinCost() argument
135 getLastCostChange(const TargetRegisterClass * RC) getLastCostChange() argument
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| H A D | TargetRegisterInfo.h | 124 hasSubClass(const TargetRegisterClass * RC) hasSubClass() argument
129 hasSubClassEq(const TargetRegisterClass * RC) hasSubClassEq() argument
136 hasSuperClass(const TargetRegisterClass * RC) hasSuperClass() argument
141 hasSuperClassEq(const TargetRegisterClass * RC) hasSuperClassEq() argument
286 getRegSizeInBits(const TargetRegisterClass & RC) getRegSizeInBits() argument
292 getSpillSize(const TargetRegisterClass & RC) getSpillSize() argument
298 getSpillAlign(const TargetRegisterClass & RC) getSpillAlign() argument
303 isTypeLegalForClass(const TargetRegisterClass & RC,MVT T) isTypeLegalForClass() argument
311 isTypeLegalForClass(const TargetRegisterClass & RC,LLT T) isTypeLegalForClass() argument
325 legalclasstypes_begin(const TargetRegisterClass & RC) legalclasstypes_begin() argument
329 legalclasstypes_end(const TargetRegisterClass & RC) legalclasstypes_end() argument
563 isDivergentRegClass(const TargetRegisterClass * RC) isDivergentRegClass() argument
614 getMatchingSuperReg(MCRegister Reg,unsigned SubIdx,const TargetRegisterClass * RC) getMatchingSuperReg() argument
649 getSubClassWithSubReg(const TargetRegisterClass * RC,unsigned Idx) getSubClassWithSubReg() argument
773 getRegClassInfo(const TargetRegisterClass & RC) getRegClassInfo() argument
820 getCrossCopyRegClass(const TargetRegisterClass * RC) getCrossCopyRegClass() argument
829 getLargestLegalSuperClass(const TargetRegisterClass * RC,const MachineFunction &) getLargestLegalSuperClass() argument
842 getRegPressureLimit(const TargetRegisterClass * RC,MachineFunction & MF) getRegPressureLimit() argument
1046 saveScavengerRegister(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,MachineBasicBlock::iterator & UseMI,const TargetRegisterClass * RC,Register Reg) saveScavengerRegister() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyExplicitLocals.cpp | 88 static unsigned getDropOpcode(const TargetRegisterClass *RC) { in getDropOpcode() argument
107 getLocalGetOpcode(const TargetRegisterClass * RC) getLocalGetOpcode() argument
126 getLocalSetOpcode(const TargetRegisterClass * RC) getLocalSetOpcode() argument
145 getLocalTeeOpcode(const TargetRegisterClass * RC) getLocalTeeOpcode() argument
164 typeForRegClass(const TargetRegisterClass * RC) typeForRegClass() argument
301 const TargetRegisterClass *RC = MRI.getRegClass(DefReg); runOnMachineFunction() local
334 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); runOnMachineFunction() local
406 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); runOnMachineFunction() local
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| /freebsd-src/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | RegisterBankEmitter.cpp | 72 addRegisterClass(const CodeGenRegisterClass * RC) addRegisterClass() argument
174 visitRegisterBankClasses(const CodeGenRegBank & RegisterClassHierarchy,const CodeGenRegisterClass * RC,const Twine & Kind,std::function<void (const CodeGenRegisterClass *,StringRef)> VisitFn,SmallPtrSetImpl<const CodeGenRegisterClass * > & VisitedRCs) visitRegisterBankClasses() argument
226 for (const auto &RC : Bank.register_classes()) emitBaseClassImplementation() local
233 for (const auto &RC : RCs) { emitBaseClassImplementation() local
272 const CodeGenRegisterClass &RC = *Bank.getRCWithLargestRegSize(M); emitBaseClassImplementation() local
303 for (const CodeGenRegisterClass *RC : run() local
307 __anon233271c80202(const CodeGenRegisterClass *RC, StringRef Kind) run() argument
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| H A D | RegisterInfoEmitter.cpp | 148 for (const auto &RC : RegisterClasses) in runEnums() local
218 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure() local
1023 for (const auto &RC : RegisterClasses) { runMCDesc() local
1059 for (const auto &RC : RegisterClasses) { runMCDesc() local
1177 __anone53e88b80502(const auto &RC) runTargetHeader() argument
1187 for (const auto &RC : RegisterClasses) { runTargetHeader() local
1224 for (const auto &RC : RegisterClasses) { runTargetDesc() local
1237 for (const auto &RC : RegisterClasses) { runTargetDesc() local
1282 for (const auto &RC : RegisterClasses) { runTargetDesc() local
1327 for (const auto &RC : RegisterClasses) { runTargetDesc() local
1355 for (const auto &RC : RegisterClasses) { runTargetDesc() local
1370 for (const auto &RC : RegisterClasses) { runTargetDesc() local
1405 for (const auto &RC : RegisterClasses) { runTargetDesc() local
1435 for (const auto &RC : RegisterClasses) runTargetDesc() local
1513 for (const auto &RC : RegisterClasses) { runTargetDesc() local
1546 for (const auto &RC : RegisterClasses) { runTargetDesc() local
1584 for (const auto &RC : RegisterClasses) { runTargetDesc() local
1611 for (const CodeGenRegisterClass *RC : BaseClasses) { runTargetDesc() local
1739 for (const CodeGenRegisterClass *RC : Category.getClasses()) runTargetDesc() local
1753 for (const CodeGenRegisterClass *RC : Category.getClasses()) runTargetDesc() local
1767 for (const CodeGenRegisterClass *RC : Category.getClasses()) runTargetDesc() local
1835 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) { debugDump() local
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| H A D | CodeGenRegisters.cpp | |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreMachineFunctionInfo.cpp | 45 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createLRSpillSlot() local
63 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createFPSpillSlot() local
76 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createEHSpillSlot() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsMachineFunction.cpp | 79 const TargetRegisterClass *RC; in initGlobalBaseReg() local
160 const TargetRegisterClass &RC = in createEhDataRegsFI() local
175 const TargetRegisterClass &RC = Mips::GPR32RegClass; in createISRRegFI() local
202 const TargetRegisterClass *RC) { in getMoveF64ViaSpillFI()
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| H A D | MipsSEFrameLowering.cpp | 173 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() local
188 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() local
206 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() local
231 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); expandStoreACC() local
264 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); expandCopyACC() local
317 const TargetRegisterClass *RC = &Mips::GPR32RegClass; expandBuildPairF64() local
383 const TargetRegisterClass *RC = expandExtractElementF64() local
421 const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? emitPrologue() local
719 const TargetRegisterClass *RC = emitEpilogue() local
834 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); spillCalleeSavedRegisters() local
895 const TargetRegisterClass &RC = STI.isGP64bit() ? determineCalleeSaves() local
911 const TargetRegisterClass &RC = determineCalleeSaves() local
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| H A D | MipsInstrInfo.h | 139 const TargetRegisterClass *RC, in storeRegToStackSlot()
147 int FrameIndex, const TargetRegisterClass *RC, in loadRegFromStackSlot()
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 449 PPCEmitLoad(MVT VT,Register & ResultReg,Address & Addr,const TargetRegisterClass * RC,bool IsZExt,unsigned FP64LoadOpc) PPCEmitLoad() argument
606 const TargetRegisterClass *RC = SelectLoad() local
623 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); PPCEmitStore() local
987 auto RC = MRI.getRegClass(SrcReg); SelectFPTrunc() local
1051 const TargetRegisterClass *RC = &PPC::F8RCRegClass; PPCMoveToFPReg() local
1130 const TargetRegisterClass *RC = &PPC::F8RCRegClass; SelectIToFP() local
1174 const TargetRegisterClass *RC = PPCMoveToIntReg() local
1225 auto RC = MRI.getRegClass(SrcReg); SelectFPToI() local
1280 const TargetRegisterClass *RC = SelectBinaryIntOp() local
1442 const TargetRegisterClass *RC = processCallArgs() local
1454 const TargetRegisterClass *RC = processCallArgs() local
1768 const TargetRegisterClass *RC = SelectRet() local
1777 const TargetRegisterClass *RC = SelectRet() local
1925 const TargetRegisterClass *RC = SelectIntExt() local
2000 const TargetRegisterClass *RC; PPCMaterializeFP() local
2061 const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass; PPCMaterializeGV() local
2119 PPCMaterialize32BitInt(int64_t Imm,const TargetRegisterClass * RC) PPCMaterialize32BitInt() argument
2151 PPCMaterialize64BitInt(int64_t Imm,const TargetRegisterClass * RC) PPCMaterialize64BitInt() argument
2221 const TargetRegisterClass *RC = PPCMaterializeInt() local
2403 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass : fastEmit_i() local
2423 fastEmitInst_ri(unsigned MachineInstOpcode,const TargetRegisterClass * RC,unsigned Op0,uint64_t Imm) fastEmitInst_ri() argument
2442 fastEmitInst_r(unsigned MachineInstOpcode,const TargetRegisterClass * RC,unsigned Op0) fastEmitInst_r() argument
2455 fastEmitInst_rr(unsigned MachineInstOpcode,const TargetRegisterClass * RC,unsigned Op0,unsigned Op1) fastEmitInst_rr() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveStacks.cpp | 54 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { in getOrCreateInterval() argument
79 const TargetRegisterClass *RC = getIntervalRegClass(Slot); in print() local
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| H A D | RegisterBank.cpp | 26 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify() local
92 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print() local
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| H A D | SwiftErrorValueTracking.cpp | 36 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateVReg() local
58 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateVRegDefAt() local
126 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in createEntriesInEntryBlock() local
240 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in propagateVRegs() local
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| H A D | RegAllocBase.cpp | 127 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg->reg()); allocatePhysRegs() local
184 const TargetRegisterClass &RC = *MRI->getRegClass(Reg); enqueue() local
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| /freebsd-src/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstantFolder.h | 46 auto *RC = dyn_cast<Constant>(RHS); in FoldBinOp() local
58 auto *RC = dyn_cast<Constant>(RHS); in FoldExactBinOp() local
71 auto *RC = dyn_cast<Constant>(RHS); in FoldNoWrapBinOp() local
100 auto *RC = dyn_cast<Constant>(RHS); FoldICmp() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ResourcePriorityQueue.cpp | 59 for (const TargetRegisterClass *RC : TRI->regclasses()) in ResourcePriorityQueue() local
359 for (const TargetRegisterClass *RC : TRI->regclasses()) in regPressureDelta() local
363 for (const TargetRegisterClass *RC : TRI->regclasses()) { in regPressureDelta() local
477 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
488 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXRegisterInfo.cpp | 29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { in getNVPTXRegClassName() argument
65 getNVPTXRegClassStr(TargetRegisterClass const * RC) getNVPTXRegClassStr() argument
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| /freebsd-src/contrib/llvm-project/llvm/include/llvm/Analysis/ |
| H A D | TargetFolder.h | 57 auto *RC = dyn_cast<Constant>(RHS); in FoldBinOp() local
69 auto *RC = dyn_cast<Constant>(RHS); in FoldExactBinOp() local
82 auto *RC = dyn_cast<Constant>(RHS); in FoldNoWrapBinOp() local
104 auto *RC = dyn_cast<Constant>(RHS); FoldICmp() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVRegisterBankInfo.cpp | 28 SPIRVRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, in getRegBankFromRegClass() argument
|