Lines Matching defs:RC
148 for (const auto &RC : RegisterClasses)
149 OS << " " << RC.getIdName() << " = " << RC.EnumValue << ",\n";
215 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
217 for (const auto &RC : RegBank.getRegClasses()) {
218 const CodeGenRegister::Vec &Regs = RC.getMembers();
219 OS << " {" << RC.getWeight(RegBank) << ", ";
220 if (Regs.empty() || RC.Artificial)
224 RC.buildRegUnitSet(RegBank, RegUnits);
227 OS << "}, \t// " << RC.getName() << "\n";
230 << " return RCWeightTable[RC->getID()];\n"
325 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n";
332 << " return &RCSetsTable[RCSetStartTable[RC->getID()]];\n"
1008 for (const auto &RC : RegisterClasses) {
1009 ArrayRef<Record *> Order = RC.getOrder();
1012 const std::string &Name = RC.getName();
1044 for (const auto &RC : RegisterClasses) {
1045 ArrayRef<Record *> Order = RC.getOrder();
1046 std::string RCName = Order.empty() ? "nullptr" : RC.getName();
1047 std::string RCBitsName = Order.empty() ? "nullptr" : RC.getName() + "Bits";
1049 assert(isInt<8>(RC.CopyCost) && "Copy cost too large.");
1051 if (RC.RSI.isSimple())
1052 RegSize = RC.RSI.getSimple().RegSize;
1054 << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size()
1055 << ", " << RCBitsSize << ", " << RC.getQualifiedIdName() << ", "
1056 << RegSize << ", " << RC.CopyCost << ", "
1057 << (RC.Allocatable ? "true" : "false") << ", "
1058 << (RC.getBaseClassOrder() ? "true" : "false") << " },\n";
1138 << "const TargetRegisterClass *RC) const override;\n"
1145 << "const TargetRegisterClass *RC) const override;\n"
1163 [](const auto &RC) { return RC.getBaseClassOrder(); })) {
1174 for (const auto &RC : RegisterClasses) {
1175 const std::string &Name = RC.getName();
1210 for (const auto &RC : RegisterClasses) {
1211 ArrayRef<Record *> Order = RC.getOrder();
1213 if (RC.Allocatable)
1223 for (const auto &RC : RegisterClasses) {
1225 for (const ValueTypeByHwMode &VVT : RC.VTs)
1281 for (const auto &RC : RegisterClasses) {
1282 assert(RC.EnumValue == EV && "Unexpected order of register classes");
1285 const RegSizeInfo &RI = RC.RSI.get(M);
1289 for (const ValueTypeByHwMode &VVT : RC.VTs)
1293 << RC.getName() << '\n';
1302 // register class, RC, is the set of sub-classes, including RC itself.
1304 // If RC has super-registers, also create a list of subreg indices and bit
1308 // For all SuperReg in SuperRC: SuperReg:Idx in RC
1312 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ...
1325 for (const auto &RC : RegisterClasses) {
1326 OS << "static const uint32_t " << RC.getName()
1328 printBitVectorAsHex(OS, RC.getSubClasses(), 32);
1331 // project into RC.
1332 IdxList &SRIList = SuperRegIdxLists[RC.EnumValue];
1335 RC.getSuperRegClasses(&Idx, MaskBV);
1353 for (const auto &RC : RegisterClasses) {
1354 ArrayRef<CodeGenRegisterClass *> Supers = RC.getSuperClasses();
1360 OS << "static const TargetRegisterClass *const " << RC.getName()
1368 for (const auto &RC : RegisterClasses) {
1369 if (!RC.AltOrderSelect.empty()) {
1370 OS << "\nstatic inline unsigned " << RC.getName()
1371 << "AltOrderSelect(const MachineFunction &MF) {" << RC.AltOrderSelect
1373 << "static ArrayRef<MCPhysReg> " << RC.getName()
1375 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) {
1376 ArrayRef<Record *> Elems = RC.getOrder(oi);
1385 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
1388 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
1389 if (RC.getOrder(oi).empty())
1393 OS << ")\n };\n const unsigned Select = " << RC.getName()
1394 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
1403 for (const auto &RC : RegisterClasses) {
1404 OS << " extern const TargetRegisterClass " << RC.getName()
1406 << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n "
1407 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + "
1408 << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n ";
1409 printMask(OS, RC.LaneMask);
1410 OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n "
1411 << (RC.GlobalPriority ? "true" : "false") << ",\n "
1412 << format("0x%02x", RC.TSFlags) << ", /* TSFlags */\n "
1413 << (RC.HasDisjunctSubRegs ? "true" : "false")
1415 << (RC.CoveredBySubRegs ? "true" : "false")
1417 if (RC.getSuperClasses().empty())
1420 OS << RC.getName() << "Superclasses,\n ";
1421 if (RC.AltOrderSelect.empty())
1424 OS << RC.getName() << "GetRawAllocationOrder\n";
1433 for (const auto &RC : RegisterClasses)
1434 OS << " &" << RC.getQualifiedName() << "RegClass,\n";
1500 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
1511 for (const auto &RC : RegisterClasses) {
1512 OS << " {\t// " << RC.getName() << "\n";
1514 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx))
1522 OS << " };\n assert(RC && \"Missing regclass\");\n"
1523 << " if (!Idx) return RC;\n --Idx;\n"
1525 << " unsigned TV = Table[RC->getID()][Idx];\n"
1530 << "::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx)"
1544 for (const auto &RC : RegisterClasses) {
1545 OS << " {\t// " << RC.getName() << '\n';
1548 MatchingSubClass = RC.getMatchingSubClassWithSubRegs(RegBank, &Idx);
1556 OS << " " << EnumValue << ",\t// " << RC.getName() << ':'
1569 OS << " };\n assert(RC && \"Missing regclass\");\n"
1570 << " if (!Idx) return RC;\n --Idx;\n"
1572 << " unsigned TV = Table[RC->getID()][Idx];\n"
1582 for (const auto &RC : RegisterClasses) {
1583 if (RC.getBaseClassOrder())
1584 BaseClasses.push_back(&RC);
1610 for (const CodeGenRegisterClass *RC : BaseClasses) {
1611 if (is_contained(RC->getMembers(), &Reg)) {
1612 BaseRC = RC;
1734 for (const CodeGenRegisterClass *RC : Category.getClasses())
1735 OS << " " << RC->getQualifiedName()
1748 for (const CodeGenRegisterClass *RC : Category.getClasses())
1749 OS << " " << RC->getQualifiedName()
1762 for (const CodeGenRegisterClass *RC : Category.getClasses())
1763 OS << " " << RC->getQualifiedName()
1831 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) {
1832 OS << "RegisterClass " << RC.getName() << ":\n";
1835 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize;
1838 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillAlignment;
1839 OS << " }\n\tNumRegs: " << RC.getMembers().size() << '\n';
1840 OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n';
1841 OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n';
1842 OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n';
1843 OS << "\tAllocatable: " << RC.Allocatable << '\n';
1844 OS << "\tAllocationPriority: " << unsigned(RC.AllocationPriority) << '\n';
1845 OS << "\tBaseClassOrder: " << RC.getBaseClassOrder() << '\n';
1847 for (const CodeGenRegister *R : RC.getMembers()) {
1852 const BitVector &SubClasses = RC.getSubClasses();
1860 for (const CodeGenRegisterClass *SRC : RC.getSuperClasses()) {