Lines Matching defs:RC
113 const TargetRegisterClass *RC,
116 const TargetRegisterClass *RC, unsigned Op0);
118 const TargetRegisterClass *RC,
143 bool isVSFRCRegClass(const TargetRegisterClass *RC) const {
144 return RC->getID() == PPC::VSFRCRegClassID;
146 bool isVSSRCRegClass(const TargetRegisterClass *RC) const {
147 return RC->getID() == PPC::VSSRCRegClassID;
161 const TargetRegisterClass *RC, bool IsZExt = true,
174 const TargetRegisterClass *RC);
176 const TargetRegisterClass *RC);
449 const TargetRegisterClass *RC,
456 // Otherwise, RC is the register class to use. If the result of the
464 (RC ? RC :
606 const TargetRegisterClass *RC =
610 if (!PPCEmitLoad(VT, ResultReg, Addr, RC, true,
623 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg);
624 bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass);
658 bool IsVSSRC = isVSSRCRegClass(RC);
659 bool IsVSFRC = isVSFRCRegClass(RC);
987 auto RC = MRI.getRegClass(SrcReg);
993 } else if (Subtarget->hasP8Vector() && isVSFRCRegClass(RC)) {
1051 const TargetRegisterClass *RC = &PPC::F8RCRegClass;
1053 if (!PPCEmitLoad(MVT::f64, ResultReg, Addr, RC, !IsSigned, LoadOpc))
1130 const TargetRegisterClass *RC = &PPC::F8RCRegClass;
1131 Register DestReg = createResultReg(RC);
1174 const TargetRegisterClass *RC =
1178 if (!PPCEmitLoad(VT, ResultReg, Addr, RC, !IsSigned))
1225 auto RC = MRI.getRegClass(SrcReg);
1233 } else if (isVSFRCRegClass(RC)) {
1280 const TargetRegisterClass *RC =
1283 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
1299 Register ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass);
1440 const TargetRegisterClass *RC =
1442 Register TmpReg = createResultReg(RC);
1452 const TargetRegisterClass *RC =
1454 Register TmpReg = createResultReg(RC);
1766 const TargetRegisterClass *RC =
1768 Register TmpReg = createResultReg(RC);
1775 const TargetRegisterClass *RC =
1777 Register TmpReg = createResultReg(RC);
1923 const TargetRegisterClass *RC =
1927 Register ResultReg = createResultReg(RC);
1998 const TargetRegisterClass *RC;
2000 RC = ((VT == MVT::f32) ? &PPC::GPRCRegClass : &PPC::SPERCRegClass);
2002 RC = ((VT == MVT::f32) ? &PPC::F4RCRegClass : &PPC::F8RCRegClass);
2004 Register DestReg = createResultReg(RC);
2059 const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass;
2060 Register DestReg = createResultReg(RC);
2098 Register HighPartReg = createResultReg(RC);
2121 const TargetRegisterClass *RC) {
2125 Register ResultReg = createResultReg(RC);
2126 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
2134 Register TmpReg = createResultReg(RC);
2153 const TargetRegisterClass *RC) {
2174 unsigned TmpReg1 = PPCMaterialize32BitInt(Imm, RC);
2182 TmpReg2 = createResultReg(RC);
2190 TmpReg3 = createResultReg(RC);
2197 Register ResultReg = createResultReg(RC);
2223 const TargetRegisterClass *RC =
2233 Register ImmReg = createResultReg(RC);
2241 return PPCMaterialize64BitInt(Imm, RC);
2243 return PPCMaterialize32BitInt(Imm, RC);
2405 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
2408 return PPCMaterialize64BitInt(Imm, RC);
2410 return PPCMaterialize32BitInt(Imm, RC);
2425 const TargetRegisterClass *RC,
2434 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2435 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2444 const TargetRegisterClass* RC,
2447 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2448 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2457 const TargetRegisterClass* RC,
2460 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2461 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));