Lines Matching defs:RC
81 const TargetRegisterClass *RC;
87 SubRegInfo(const TargetRegisterClass *RC_ = nullptr) : RC(RC_) {}
90 /// Map OldSubReg -> { RC, NewSubReg }. Used as in/out container.
93 /// Given register class RC and the set of used subregs as keys in the SubRegs
97 const TargetRegisterClass *getMinSizeReg(const TargetRegisterClass *RC,
100 /// Given regclass RC and pairs of [OldSubReg, SubRegRC] in SubRegs try to
116 getRegClassWithShiftedSubregs(const TargetRegisterClass *RC, unsigned RShift,
142 /// RC by SubRegIdx. The result is cached in SuperRegMasks data-member.
143 const uint32_t *getSuperRegClassMask(const TargetRegisterClass *RC,
146 /// Cache for getSuperRegClassMask method: { RC, SubRegIdx } -> Class bitmask.
187 GCNRewritePartialRegUses::getSuperRegClassMask(const TargetRegisterClass *RC,
190 SuperRegMasks.try_emplace({RC, SubRegIdx}, nullptr);
192 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) {
210 auto *RC = TRI->getRegClass(ClassID);
211 if (RC->isAllocatable() && TRI->isRegClassAligned(RC, AlignNumBits))
220 const TargetRegisterClass *RC, unsigned RShift, unsigned RegNumBits,
223 unsigned RCAlign = TRI->getRegClassAlignmentNumBits(RC);
238 // Covering subreg will become a full register, RC should be allocatable.
271 auto *RC = TRI->getRegClass(ClassID);
272 unsigned NumBits = TRI->getRegSizeInBits(*RC);
275 MinRC = RC;
290 return (MinRC != RC || RShift != 0) ? MinRC : nullptr;
294 GCNRewritePartialRegUses::getMinSizeReg(const TargetRegisterClass *RC,
316 return getRegClassWithShiftedSubregs(RC, Offset, End - Offset, CoverSubreg,
324 MaxAlign = std::max(MaxAlign, TRI->getSubRegAlignmentNumBits(RC, SubReg));
328 if (TRI->getSubRegAlignmentNumBits(RC, SubReg) != MaxAlign)
343 return getRegClassWithShiftedSubregs(RC, RShift, End - RShift, 0, SubRegs);
418 auto *RC = MRI->getRegClass(Reg);
420 << ':' << TRI->getRegClassName(RC) << '\n');
431 const TargetRegisterClass *&SubRegRC = I->second.RC;
434 SubRegRC = TRI->getSubRegisterClass(RC, SubReg);
451 auto *NewRC = getMinSizeReg(RC, SubRegs);
459 << TRI->getRegClassName(RC) << " -> "