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Searched defs:PredReg (Results 1 – 21 of 21) sorted by relevance

/llvm-project/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.h90 Register PredReg; in getVPTInstrPredicate() local
H A DThumb2InstrInfo.cpp74 ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg); in ReplaceTailWithBranchTo() local
122 return getITInstrPredicate(*MBBI, PredReg) == ARMCC::AL; in isLegalToSplitMBBAt() local
313 emitT2RegPlusImmediate(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,Register DestReg,Register BaseReg,int NumBytes,ARMCC::CondCodes Pred,Register PredReg,const ARMBaseInstrInfo & TII,unsigned MIFlags) emitT2RegPlusImmediate() argument
573 Register PredReg; rewriteT2FrameIndex() local
787 getITInstrPredicate(const MachineInstr & MI,Register & PredReg) getITInstrPredicate() argument
805 getVPTInstrPredicate(const MachineInstr & MI,Register & PredReg) getVPTInstrPredicate() argument
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H A DMVEVPTBlockPass.cpp251 ARMVCC::VPTCodes Pred = getVPTInstrPredicate(*MI, PredReg); in InsertVPTBlocks() local
105 Register PredReg; StepOverPredicatedInstrs() local
H A DARMLoadStoreOptimizer.cpp490 UpdateBaseRegUses(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,const DebugLoc & DL,unsigned Base,unsigned WordOffset,ARMCC::CondCodes Pred,unsigned PredReg) UpdateBaseRegUses() argument
631 CreateLoadStoreMulti(MachineBasicBlock & MBB,MachineBasicBlock::iterator InsertBefore,int Offset,unsigned Base,bool BaseKill,unsigned Opcode,ARMCC::CondCodes Pred,unsigned PredReg,const DebugLoc & DL,ArrayRef<std::pair<unsigned,bool>> Regs,ArrayRef<MachineInstr * > Instrs) CreateLoadStoreMulti() argument
838 CreateLoadStoreDouble(MachineBasicBlock & MBB,MachineBasicBlock::iterator InsertBefore,int Offset,unsigned Base,bool BaseKill,unsigned Opcode,ARMCC::CondCodes Pred,unsigned PredReg,const DebugLoc & DL,ArrayRef<std::pair<unsigned,bool>> Regs,ArrayRef<MachineInstr * > Instrs) const CreateLoadStoreDouble() argument
908 Register PredReg; MergeOpsUpdate() local
1192 isIncrementOrDecrement(const MachineInstr & MI,Register Reg,ARMCC::CondCodes Pred,Register PredReg) isIncrementOrDecrement() argument
1224 findIncDecBefore(MachineBasicBlock::iterator MBBI,Register Reg,ARMCC::CondCodes Pred,Register PredReg,int & Offset) findIncDecBefore() argument
1244 findIncDecAfter(MachineBasicBlock::iterator MBBI,Register Reg,ARMCC::CondCodes Pred,Register PredReg,int & Offset,const TargetRegisterInfo * TRI) findIncDecAfter() argument
1297 Register PredReg; MergeBaseUpdateLSMultiple() local
1493 Register PredReg; MergeBaseUpdateLoadStore() local
1631 Register PredReg; MergeBaseUpdateLSDouble() local
1738 InsertLDR_STR(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,int Offset,bool isDef,unsigned NewOpc,unsigned Reg,bool RegDeadKill,bool RegUndef,unsigned BaseReg,bool BaseKill,bool BaseUndef,ARMCC::CondCodes Pred,unsigned PredReg,const TargetInstrInfo * TII,MachineInstr * MI) InsertLDR_STR() argument
1801 Register PredReg; FixInvalidRegPairOp() local
1901 Register PredReg; LoadStoreMultipleOpti() local
2258 CanFormLdStDWord(MachineInstr * Op0,MachineInstr * Op1,DebugLoc & dl,unsigned & NewOpc,Register & FirstReg,Register & SecondReg,Register & BaseReg,int & Offset,Register & PredReg,ARMCC::CondCodes & Pred,bool & isT2) CanFormLdStDWord() argument
2417 Register BaseReg, PredReg; RescheduleOps() local
2566 Register PredReg; RescheduleLoadStoreInstrs() local
3180 Register PredReg; DistributeIncrements() local
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H A DThumb2SizeReduction.cpp729 if (getInstrPredicate(*MI, PredReg) != ARMCC::AL) in ReduceSpecial() local
469 Register PredReg = MI->getOperand(5).getReg(); ReduceLoadStore() local
687 Register PredReg; ReduceSpecial() local
800 Register PredReg; ReduceTo2Addr() local
892 Register PredReg; ReduceToNarrow() local
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H A DThumbRegisterInfo.cpp65 emitThumb1LoadConstPool(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,unsigned DestReg,unsigned SubIdx,int Val,ARMCC::CondCodes Pred,unsigned PredReg,unsigned MIFlags) emitThumb1LoadConstPool() argument
85 emitThumb2LoadConstPool(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,unsigned DestReg,unsigned SubIdx,int Val,ARMCC::CondCodes Pred,unsigned PredReg,unsigned MIFlags) emitThumb2LoadConstPool() argument
106 emitLoadConstPool(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,Register DestReg,unsigned SubIdx,int Val,ARMCC::CondCodes Pred,Register PredReg,unsigned MIFlags) const emitLoadConstPool() argument
H A DThumb2ITBlockPass.cpp201 Register PredReg; InsertITInstructions() local
H A DARMBaseRegisterInfo.cpp499 emitLoadConstPool(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,Register DestReg,unsigned SubIdx,int Val,ARMCC::CondCodes Pred,Register PredReg,unsigned MIFlags) const emitLoadConstPool() argument
852 Register PredReg = (PIdx == -1) ? Register() : MI.getOperand(PIdx+1).getReg(); eliminateFrameIndex() local
H A DMLxExpansionPass.cpp282 Register PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
H A DARMConstantIslandPass.cpp1470 Register PredReg; createNewWater() local
1516 Register PredReg; createNewWater() local
1540 Register PredReg; createNewWater() local
1943 Register PredReg; optimizeThumb2Branches() local
H A DARMFrameLowering.cpp540 emitRegPlusImmediate(bool isARM,MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,const ARMBaseInstrInfo & TII,unsigned DestReg,unsigned SrcReg,int NumBytes,unsigned MIFlags=MachineInstr::NoFlags,ARMCC::CondCodes Pred=ARMCC::AL,unsigned PredReg=0) emitRegPlusImmediate() argument
554 emitSPUpdate(bool isARM,MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,const ARMBaseInstrInfo & TII,int NumBytes,unsigned MIFlags=MachineInstr::NoFlags,ARMCC::CondCodes Pred=ARMCC::AL,unsigned PredReg=0) emitSPUpdate() argument
2890 unsigned PredReg = TII.getFramePred(*I); eliminateCallFramePseudoInstr() local
H A DARMISelDAGToDAG.cpp1758 SDValue PredReg; tryMVEIndexedLoad() local
2925 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); SelectCDE_CXxD() local
4274 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); Select() local
4286 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); Select() local
4297 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); Select() local
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H A DARMBaseInstrInfo.cpp2234 getInstrPredicate(const MachineInstr & MI,Register & PredReg) getInstrPredicate() argument
2264 Register PredReg; commuteInstructionImpl() local
2472 emitARMRegPlusImmediate(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,Register DestReg,Register BaseReg,int NumBytes,ARMCC::CondCodes Pred,Register PredReg,const ARMBaseInstrInfo & TII,unsigned MIFlags) emitARMRegPlusImmediate() argument
5618 Register PredReg; findCMPToFoldIntoCBZ() local
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H A DARMExpandPseudoInsts.cpp1063 Register PredReg; in ExpandMOV32BitImm() local
/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp190 MCRegister DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
H A DHexagonMCCompound.cpp177 MCRegister PredReg = Predicate.getReg(); in getCompoundOp() local
H A DHexagonMCChecker.cpp94 MCRegister PredReg; in init() local
68 initReg(MCInst const & MCI,unsigned R,unsigned & PredReg,bool & isTrue) initReg() argument
/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp321 bool HexagonGenPredicate::isScalarPred(RegisterSubReg PredReg) { in isScalarPred()
H A DHexagonInstrInfo.cpp1701 Register PredReg; PredicateInstruction() local
4550 getPredReg(ArrayRef<MachineOperand> Cond,Register & PredReg,unsigned & PredRegPos,unsigned & PredRegFlags) const getPredReg() argument
H A DHexagonHardwareLoops.cpp651 Register PredReg; getLoopTripCount() local
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp1481 optimizePTestInstr(MachineInstr * PTest,unsigned MaskReg,unsigned PredReg,const MachineRegisterInfo * MRI) const optimizePTestInstr() argument