Lines Matching defs:PredReg
173 ARMCC::CondCodes Pred, unsigned PredReg);
177 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
183 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
488 unsigned PredReg) {
557 .addReg(PredReg);
579 .addReg(PredReg);
629 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
749 .add(predOps(Pred, PredReg));
760 .add(predOps(Pred, PredReg));
766 .add(predOps(Pred, PredReg));
771 .add(predOps(Pred, PredReg))
816 UpdateBaseRegUses(MBB, InsertBefore, DL, Base, NumRegs, Pred, PredReg);
823 MIB.addImm(Pred).addReg(PredReg);
836 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
853 MIB.addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
906 Register PredReg;
907 ARMCC::CondCodes Pred = getInstrPredicate(*First, PredReg);
912 Opcode, Pred, PredReg, DL, Regs,
916 Opcode, Pred, PredReg, DL, Regs, Cand.Instrs);
1190 ARMCC::CondCodes Pred, Register PredReg) {
1211 MIPredReg != PredReg)
1222 ARMCC::CondCodes Pred, Register PredReg, int &Offset) {
1235 Offset = isIncrementOrDecrement(*PrevMBBI, Reg, Pred, PredReg);
1242 ARMCC::CondCodes Pred, Register PredReg, int &Offset,
1255 unsigned Off = isIncrementOrDecrement(*NextMBBI, Reg, Pred, PredReg);
1295 Register PredReg;
1296 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
1311 = findIncDecBefore(MBBI, Base, Pred, PredReg, Offset);
1318 MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset, TRI);
1351 .addImm(Pred).addReg(PredReg);
1491 Register PredReg;
1492 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
1498 = findIncDecBefore(MBBI, Base, Pred, PredReg, Offset);
1505 MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset, TRI);
1533 .addReg(PredReg)
1549 .addReg(PredReg)
1561 .add(predOps(Pred, PredReg))
1573 .add(predOps(Pred, PredReg))
1591 .add(predOps(Pred, PredReg))
1601 .add(predOps(Pred, PredReg))
1629 Register PredReg;
1630 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
1635 PredReg, Offset);
1640 MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset, TRI);
1659 .addImm(Offset).addImm(Pred).addReg(PredReg);
1736 unsigned PredReg, const TargetInstrInfo *TII,
1743 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1752 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1799 Register PredReg;
1800 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
1811 .addImm(Pred).addReg(PredReg)
1819 .addImm(Pred).addReg(PredReg)
1842 false, BaseReg, false, BaseUndef, Pred, PredReg, TII, MI);
1844 false, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,
1858 EvenUndef, BaseReg, false, BaseUndef, Pred, PredReg, TII,
1861 OddUndef, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,
1899 Register PredReg;
1900 ARMCC::CondCodes Pred = getInstrPredicate(*MBBI, PredReg);
1910 // Note: No need to match PredReg in the next if.
2170 Register &BaseReg, int &Offset, Register &PredReg,
2256 Register &PredReg, ARMCC::CondCodes &Pred, bool &isT2) {
2316 Pred = getInstrPredicate(*Op0, PredReg);
2415 Register BaseReg, PredReg;
2423 Offset, PredReg, Pred, isT2)) {
2443 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
2457 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
2561 Register PredReg;
2562 if (getInstrPredicate(MI, PredReg) != ARMCC::AL)
3175 Register PredReg;
3177 getInstrPredicate(*Increment, PredReg) != ARMCC::AL)