Revision tags: llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1 |
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6b813576 |
| 28-Sep-2024 |
Craig Topper <craig.topper@sifive.com> |
[Hexagon] Use MCRegister. NFC
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Revision tags: llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2 |
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14bc3748 |
| 17-Apr-2023 |
Jay Foad <jay.foad@amd.com> |
[MC] Use subregs/superregs instead of MCSubRegIterator/MCSuperRegIterator. NFC.
Differential Revision: https://reviews.llvm.org/D148613
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Revision tags: llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3 |
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432caca3 |
| 18-Feb-2023 |
Fangrui Song <i@maskray.me> |
Simplify with hasFeature. NFC
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Revision tags: llvmorg-16.0.0-rc2 |
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97d51e3f |
| 01-Feb-2023 |
Alexey Karyakin <akaryaki@quicinc.com> |
[Hexagon] Disallow using the same register for Vy/Vx in vdeal/vshuff
Non-assignment forms of vshuff and vdeal use the first two registers (Vy, Vx) as both inputs and outputs. It is not valid to use
[Hexagon] Disallow using the same register for Vy/Vx in vdeal/vshuff
Non-assignment forms of vshuff and vdeal use the first two registers (Vy, Vx) as both inputs and outputs. It is not valid to use the same register for both Vy and Vx. The double-write error was not detected previously because of a special case, which is not actually necessary.
Differential Revision: https://reviews.llvm.org/D142251
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Revision tags: llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7 |
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073401e5 |
| 11-Jan-2023 |
Jay Foad <jay.foad@amd.com> |
[MC] Define and use MCInstrDesc implicit_uses and implicit_defs. NFC.
The new methods return a range for easier iteration. Use them everywhere instead of getImplicitUses, getNumImplicitUses, getImpl
[MC] Define and use MCInstrDesc implicit_uses and implicit_defs. NFC.
The new methods return a range for easier iteration. Use them everywhere instead of getImplicitUses, getNumImplicitUses, getImplicitDefs and getNumImplicitDefs. A future patch will remove the old methods.
In some use cases the new methods are less efficient because they always have to scan the whole uses/defs array to count its length, but that will be fixed in a future patch by storing the number of implicit uses/defs explicitly in MCInstrDesc. At that point there will be no need to 0-terminate the arrays.
Differential Revision: https://reviews.llvm.org/D142215
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768aed13 |
| 13-Jan-2023 |
Jay Foad <jay.foad@amd.com> |
[MC] Make more use of MCInstrDesc::operands. NFC.
Change MCInstrDesc::operands to return an ArrayRef so we can easily use it everywhere instead of the (IMHO ugly) opInfo_begin and opInfo_end. A futu
[MC] Make more use of MCInstrDesc::operands. NFC.
Change MCInstrDesc::operands to return an ArrayRef so we can easily use it everywhere instead of the (IMHO ugly) opInfo_begin and opInfo_end. A future patch will remove opInfo_begin and opInfo_end.
Also use it instead of raw access to the OpInfo pointer. A future patch will remove this pointer.
Differential Revision: https://reviews.llvm.org/D142213
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Revision tags: llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5 |
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557efc9a |
| 04-Jun-2022 |
Fangrui Song <i@maskray.me> |
[llvm] Remove unneeded cl::ZeroOrMore for cl::opt options. NFC
Some cl::ZeroOrMore were added to avoid the `may only occur zero or one times!` error. More were added due to cargo cult. Since the err
[llvm] Remove unneeded cl::ZeroOrMore for cl::opt options. NFC
Some cl::ZeroOrMore were added to avoid the `may only occur zero or one times!` error. More were added due to cargo cult. Since the error has been removed, cl::ZeroOrMore is unneeded.
Also remove cl::init(false) while touching the lines.
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Revision tags: llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1 |
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ef736a1c |
| 08-Feb-2022 |
serge-sans-paille <sguelton@redhat.com> |
Cleanup LLVMMC headers
There's a few relevant forward declarations in there that may require downstream adding explicit includes:
llvm/MC/MCContext.h no longer includes llvm/BinaryFormat/ELF.h, llv
Cleanup LLVMMC headers
There's a few relevant forward declarations in there that may require downstream adding explicit includes:
llvm/MC/MCContext.h no longer includes llvm/BinaryFormat/ELF.h, llvm/MC/MCSubtargetInfo.h, llvm/MC/MCTargetOptions.h llvm/MC/MCObjectStreamer.h no longer include llvm/MC/MCAssembler.h llvm/MC/MCAssembler.h no longer includes llvm/MC/MCFixup.h, llvm/MC/MCFragment.h
Counting preprocessed lines required to rebuild llvm-project on my setup: before: 1052436830 after: 1049293745
Which is significant and backs up the change in addition to the usual benefits of decreasing coupling between headers and compilation units.
Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup Differential Revision: https://reviews.llvm.org/D119244
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Revision tags: llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2 |
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137642f4 |
| 07-Jan-2022 |
Yuanxiang Ye <yuanxian@quicinc.com> |
[Hexagon] Reject accumulating on vd.tmp
Added hvx accum checker function and test cases.
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Revision tags: llvmorg-13.0.1-rc1, llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3, llvmorg-13.0.0-rc2, llvmorg-13.0.0-rc1, llvmorg-14-init, llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3, llvmorg-12.0.1-rc2, llvmorg-12.0.1-rc1, llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4, llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2, llvmorg-11.1.0, llvmorg-11.1.0-rc3, llvmorg-12.0.0-rc1, llvmorg-13-init, llvmorg-11.1.0-rc2, llvmorg-11.1.0-rc1, llvmorg-11.0.1, llvmorg-11.0.1-rc2, llvmorg-11.0.1-rc1, llvmorg-11.0.0, llvmorg-11.0.0-rc6, llvmorg-11.0.0-rc5, llvmorg-11.0.0-rc4, llvmorg-11.0.0-rc3, llvmorg-11.0.0-rc2, llvmorg-11.0.0-rc1, llvmorg-12-init, llvmorg-10.0.1, llvmorg-10.0.1-rc4, llvmorg-10.0.1-rc3, llvmorg-10.0.1-rc2, llvmorg-10.0.1-rc1, llvmorg-10.0.0, llvmorg-10.0.0-rc6, llvmorg-10.0.0-rc5, llvmorg-10.0.0-rc4, llvmorg-10.0.0-rc3, llvmorg-10.0.0-rc2, llvmorg-10.0.0-rc1, llvmorg-11-init, llvmorg-9.0.1, llvmorg-9.0.1-rc3, llvmorg-9.0.1-rc2, llvmorg-9.0.1-rc1, llvmorg-9.0.0, llvmorg-9.0.0-rc6, llvmorg-9.0.0-rc5, llvmorg-9.0.0-rc4, llvmorg-9.0.0-rc3, llvmorg-9.0.0-rc2, llvmorg-9.0.0-rc1, llvmorg-10-init, llvmorg-8.0.1, llvmorg-8.0.1-rc4, llvmorg-8.0.1-rc3, llvmorg-8.0.1-rc2, llvmorg-8.0.1-rc1, llvmorg-8.0.0, llvmorg-8.0.0-rc5, llvmorg-8.0.0-rc4, llvmorg-8.0.0-rc3, llvmorg-7.1.0, llvmorg-7.1.0-rc1, llvmorg-8.0.0-rc2, llvmorg-8.0.0-rc1, llvmorg-7.0.1, llvmorg-7.0.1-rc3, llvmorg-7.0.1-rc2, llvmorg-7.0.1-rc1, llvmorg-7.0.0, llvmorg-7.0.0-rc3, llvmorg-7.0.0-rc2, llvmorg-7.0.0-rc1, llvmorg-6.0.1, llvmorg-6.0.1-rc3, llvmorg-6.0.1-rc2 |
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1f71e46f |
| 03-May-2018 |
Brian Cain <bcain@quicinc.com> |
[Hexagon] Apply tiny core packet size slots limit
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a2473601 |
| 07-Jan-2022 |
colinl <colinl@codeaurora.org> |
[Hexagon] Simplify AX instruction detection
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f3a344d2 |
| 07-Jan-2022 |
Kazu Hirata <kazu@google.com> |
[Target] Remove redundant member initialization (NFC)
Identified with readability-redundant-member-init.
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b17f036a |
| 28-Sep-2018 |
Brian Cain <bcain@quicinc.com> |
[Hexagon] Consider HVX reg aliases for .cur warning
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e5947760 |
| 03-Jan-2022 |
Kazu Hirata <kazu@google.com> |
Revert "[llvm] Remove redundant member initialization (NFC)"
This reverts commit fd4808887ee47f3ec8a030e9211169ef4fb094c3.
This patch causes gcc to issue a lot of warnings like:
warning: base cl
Revert "[llvm] Remove redundant member initialization (NFC)"
This reverts commit fd4808887ee47f3ec8a030e9211169ef4fb094c3.
This patch causes gcc to issue a lot of warnings like:
warning: base class ‘class llvm::MCParsedAsmOperand’ should be explicitly initialized in the copy constructor [-Wextra]
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fd480888 |
| 02-Jan-2022 |
Kazu Hirata <kazu@google.com> |
[llvm] Remove redundant member initialization (NFC)
Identified with readability-redundant-member-init.
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1e7bd93f |
| 28-Dec-2021 |
Brian Cain <bcain@quicinc.com> |
[Hexagon] Add HexagonMCInstrInfo::IsABranchingInst, NFC
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c5327137 |
| 06-Sep-2018 |
Brian Cain <bcain@quicinc.com> |
[Hexagon] Fix for producer operands search w/z-reg
Z-register does not show up in defs, so checks searching for the def operand must look for a different def index than they would normally.
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648246cc |
| 28-Dec-2021 |
Krzysztof Parzyszek <kparzysz@quicinc.com> |
[Hexagon] Remove isPredicateRegister in favor of isPredReg, NFC
HexagonMCChecker has its own function isPredicateRegister, which does the same thing as HexagonMCInstrInfo::isPredReg.
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f766bc09 |
| 22-Dec-2021 |
Krzysztof Parzyszek <kparzysz@quicinc.com> |
[Hexagon] Introduce Hexagon v69 ISA
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cfba1a96 |
| 15-May-2020 |
Brian Cain <bcain@quicinc.com> |
[Hexagon] pX.new cannot be used with p3:0 as producer
Writes to p3:0 do not produce new values, we should bar any .new consumer trying to use it as a producer.
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bf3b86bc |
| 14-Aug-2018 |
Brian Cain <bcain@codeaurora.org> |
[Hexagon] v67+ HVX register pairs should support either direction
Assembler now permits pairs like 'v0:1', which are encoded differently from the odd-first pairs like 'v1:0'.
The compiler will requ
[Hexagon] v67+ HVX register pairs should support either direction
Assembler now permits pairs like 'v0:1', which are encoded differently from the odd-first pairs like 'v1:0'.
The compiler will require more work to leverage these new register pairs.
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6dbbd0f3 |
| 08-Aug-2019 |
Brian Cain <bcain@quicinc.com> |
[llvm-mc] Add reportWarning() to MCContext
Adding reportWarning() to MCContext, so that it can be used from the Hexagon assembler backend.
llvm-svn: 368327
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6214b577 |
| 03-Jun-2019 |
Dmitri Gribenko <gribozavr@gmail.com> |
Include what you use in HexagonMCChecker.cpp
HexagonMCChecker.cpp was not using any APIs from Hexagon.h. Doing so is problematic from include-what-you-use perspective, but it is also a layering iss
Include what you use in HexagonMCChecker.cpp
HexagonMCChecker.cpp was not using any APIs from Hexagon.h. Doing so is problematic from include-what-you-use perspective, but it is also a layering issue (it creates a dependency cycle between the primary Hexagon target library and the MCTargetDesc library).
llvm-svn: 362383
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2946cd70 |
| 19-Jan-2019 |
Chandler Carruth <chandlerc@gmail.com> |
Update the file headers across all of the LLVM projects in the monorepo to reflect the new license.
We understand that people may be surprised that we're moving the header entirely to discuss the ne
Update the file headers across all of the LLVM projects in the monorepo to reflect the new license.
We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach.
Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository.
llvm-svn: 351636
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Revision tags: llvmorg-6.0.1-rc1, llvmorg-5.0.2, llvmorg-5.0.2-rc2, llvmorg-5.0.2-rc1, llvmorg-6.0.0, llvmorg-6.0.0-rc3, llvmorg-6.0.0-rc2, llvmorg-6.0.0-rc1 |
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a8ab1b75 |
| 11-Dec-2017 |
Krzysztof Parzyszek <kparzysz@codeaurora.org> |
[Hexagon] Add support for Hexagon V65
llvm-svn: 320404
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