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Searched defs:NumParts (Results 1 – 23 of 23) sorted by relevance

/llvm-project/libcxx/benchmarks/
H A Dfilesystem.bench.cpp
/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp680 unsigned NumParts = determineAssignments() local
787 const unsigned NumParts = Args[i].Flags.size(); handleAssignments() local
1110 unsigned NumParts = getReturnInfo() local
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H A DLegalizerHelper.cpp263 int NumParts = LCMTy.getSizeInBits() / NarrowTy.getSizeInBits(); in buildLCMMergePieces() local
61 unsigned NumParts = Size / NarrowSize; getNarrowTypeBreakDown() local
1236 int NumParts = SizeOp0 / NarrowSize; narrowScalar() local
1254 int NumParts = TotalSize / NarrowSize; narrowScalar() local
1392 int NumParts = SizeOp0 / NarrowSize; narrowScalar() local
1473 unsigned NumParts = SizeOp0 / NarrowSize; narrowScalar() local
1628 int NumParts = SizeOp0 / NarrowSize; narrowScalar() local
1691 unsigned NumParts = SizeOp0 / NarrowSize; narrowScalar() local
4159 int NumParts, NumLeftover; makeDstOps() local
4445 unsigned NumParts = DstTy.getNumElements() / NarrowTy.getNumElements(); fewerElementsVectorMerge() local
4558 int NumParts = -1; reduceLoadStoreWidth() local
4587 __anon87a70b730102(LLT PartTy, SmallVectorImpl<Register> &ValRegs, unsigned NumParts, unsigned Offset) reduceLoadStoreWidth() argument
4979 const unsigned NumParts = fewerElementsVectorReductions() local
5065 unsigned NumParts = SrcTy.getNumElements(); fewerElementsVectorSeqReductions() local
5899 unsigned NumParts = Size / NarrowSize; narrowScalarMul() local
5954 int NumParts = SizeOp1 / NarrowSize; narrowScalarExtract() local
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H A DUtils.cpp493 extractParts(Register Reg,LLT Ty,int NumParts,SmallVectorImpl<Register> & VRegs,MachineIRBuilder & MIRBuilder,MachineRegisterInfo & MRI) extractParts() argument
511 unsigned NumParts = RegSize / MainSize; extractParts() local
/llvm-project/llvm/include/llvm/Target/
H A DTargetMachine.h433 splitModule(Module & M,unsigned NumParts,function_ref<void (std::unique_ptr<Module> MPart)> ModuleCallback) splitModule() argument
/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUSplitModule.cpp436 doPartitioning(SplitModuleLogger & SML,Module & M,unsigned NumParts,CostType ModuleCost,const DenseMap<const Function *,CostType> & FnCosts,const SmallVector<FunctionWithDependencies> & WorkList) doPartitioning() argument
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H A DAMDGPUTargetMachine.cpp830 splitModule(Module & M,unsigned NumParts,function_ref<void (std::unique_ptr<Module> MPart)> ModuleCallback) splitModule() argument
H A DAMDGPULegalizerInfo.cpp598 const unsigned NumParts = PointerTy.getSizeInBits() / 32; castBufferRsrcFromV4I32() local
634 const unsigned NumParts = PointerTy.getSizeInBits() / 32; castBufferRsrcToV4I32() local
4136 unsigned NumParts = Size / 32; legalizeMul() local
5512 unsigned NumParts = Size / 32; legalizeLaneOp() local
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H A DAMDGPURegisterBankInfo.cpp722 unsigned NumParts = Bits / 32; in buildReadFirstLane() local
898 unsigned NumParts = OpSize / PartSize; in executeInWaterfallLoop() local
H A DSIRegisterInfo.cpp2994 const unsigned NumParts = RegDWORDs / EltDWORDs; getRegSplitParts() local
/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZTargetTransformInfo.cpp670 unsigned NumParts = getNumVectorRegs(SrcTy); getVectorTruncCost() local
H A DSystemZISelLowering.cpp1582 splitValueIntoRegisterParts(SelectionDAG & DAG,const SDLoc & DL,SDValue Val,SDValue * Parts,unsigned NumParts,MVT PartVT,std::optional<CallingConv::ID> CC) const splitValueIntoRegisterParts() argument
1594 joinRegisterPartsIntoValue(SelectionDAG & DAG,const SDLoc & DL,const SDValue * Parts,unsigned NumParts,MVT PartVT,EVT ValueVT,std::optional<CallingConv::ID> CC) const joinRegisterPartsIntoValue() argument
/llvm-project/clang/utils/TableGen/
H A DMveEmitter.cpp1768 constexpr unsigned NumParts = 4; EmitHeader() local
2032 constexpr unsigned NumParts = 3; EmitHeader() local
/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp170 getCopyFromParts(SelectionDAG & DAG,const SDLoc & DL,const SDValue * Parts,unsigned NumParts,MVT PartVT,EVT ValueVT,const Value * V,SDValue InChain,std::optional<CallingConv::ID> CC=std::nullopt,std::optional<ISD::NodeType> AssertOp=std::nullopt) getCopyFromParts() argument
342 getCopyFromPartsVector(SelectionDAG & DAG,const SDLoc & DL,const SDValue * Parts,unsigned NumParts,MVT PartVT,EVT ValueVT,const Value * V,SDValue InChain,std::optional<CallingConv::ID> CallConv) getCopyFromPartsVector() argument
508 getCopyToParts(SelectionDAG & DAG,const SDLoc & DL,SDValue Val,SDValue * Parts,unsigned NumParts,MVT PartVT,const Value * V,std::optional<CallingConv::ID> CallConv=std::nullopt,ISD::NodeType ExtendKind=ISD::ANY_EXTEND) getCopyToParts() argument
691 getCopyToPartsVector(SelectionDAG & DAG,const SDLoc & DL,SDValue Val,SDValue * Parts,unsigned NumParts,MVT PartVT,const Value * V,std::optional<CallingConv::ID> CallConv) getCopyToPartsVector() argument
975 unsigned NumParts = RegCount[Value]; getCopyToRegs() local
2259 unsigned NumParts = TLI.getNumRegistersForCallingConv(Context, CC, VT); visitRet() local
10962 unsigned NumParts = getNumRegistersForCallingConv(CLI.RetTy->getContext(), LowerCallTo() local
11622 unsigned NumParts = 0; LowerArguments() local
11650 unsigned NumParts = TLI->getNumRegistersForCallingConv( LowerArguments() local
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/llvm-project/llvm/lib/Transforms/Vectorize/
H A DSLPVectorizer.cpp261 getPartNumElems(unsigned Size,unsigned NumParts) getPartNumElems() argument
4201 int NumParts = TTI->getNumberOfParts(VecTy); findReusedOrderedScalars() local
4241 __anon779134672602(MutableArrayRef<unsigned> CurrentOrder, ArrayRef<int> Mask, int PartSz, int NumParts, function_ref<unsigned(unsigned)> GetVF) findReusedOrderedScalars() argument
4946 unsigned NumParts = divideCeil(VF, Sz); getReorderingData() local
8303 unsigned NumParts = TTI.getNumberOfParts(VecTy); getBuildVectorCost() local
8430 computeExtractCost(ArrayRef<Value * > VL,ArrayRef<int> Mask,ArrayRef<std::optional<TTI::ShuffleKind>> ShuffleKinds,unsigned NumParts) computeExtractCost() argument
8873 adjustExtracts(const TreeEntry * E,MutableArrayRef<int> Mask,ArrayRef<std::optional<TTI::ShuffleKind>> ShuffleKinds,unsigned NumParts,bool & UseVecBaseAsInput) adjustExtracts() argument
8996 unsigned NumParts = TTI.getNumberOfParts(MaskVecTy); add() local
9013 unsigned NumParts = TTI.getNumberOfParts(MaskVecTy); add() local
11245 isGatherShuffledEntry(const TreeEntry * TE,ArrayRef<Value * > VL,SmallVectorImpl<int> & Mask,SmallVectorImpl<SmallVector<const TreeEntry * >> & Entries,unsigned NumParts,bool ForOrder) isGatherShuffledEntry() argument
11818 adjustExtracts(const TreeEntry * E,MutableArrayRef<int> Mask,ArrayRef<std::optional<TTI::ShuffleKind>> ShuffleKinds,unsigned NumParts,bool & UseVecBaseAsInput) adjustExtracts() argument
12328 unsigned NumParts = TTI->getNumberOfParts(VecTy); processBuildVector() local
15477 unsigned NumParts = computeMinimumValueSizes() local
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/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1848 unsigned NumParts = GetReturnInfo() local
/llvm-project/llvm/lib/Transforms/IPO/
H A DGlobalOpt.cpp533 unsigned NumParts = count_if(Parts, [](const auto &Pair) { SRAGlobal() local
/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h4455 splitValueIntoRegisterParts(SelectionDAG & DAG,const SDLoc & DL,SDValue Val,SDValue * Parts,unsigned NumParts,MVT PartVT,std::optional<CallingConv::ID> CC) splitValueIntoRegisterParts() argument
4479 joinRegisterPartsIntoValue(SelectionDAG & DAG,const SDLoc & DL,const SDValue * Parts,unsigned NumParts,MVT PartVT,EVT ValueVT,std::optional<CallingConv::ID> CC) joinRegisterPartsIntoValue() argument
/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp3143 splitValueIntoRegisterParts(SelectionDAG & DAG,const SDLoc & DL,SDValue Val,SDValue * Parts,unsigned NumParts,MVT PartVT,std::optional<CallingConv::ID> CC) const splitValueIntoRegisterParts() argument
/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp4477 splitValueIntoRegisterParts(SelectionDAG & DAG,const SDLoc & DL,SDValue Val,SDValue * Parts,unsigned NumParts,MVT PartVT,std::optional<CallingConv::ID> CC) const splitValueIntoRegisterParts() argument
4492 joinRegisterPartsIntoValue(SelectionDAG & DAG,const SDLoc & DL,const SDValue * Parts,unsigned NumParts,MVT PartVT,EVT ValueVT,std::optional<CallingConv::ID> CC) const joinRegisterPartsIntoValue() argument
13426 unsigned NumParts = VecVT.getSizeInBits() / 128; PerformVQDMULHCombine() local
/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp21415 splitValueIntoRegisterParts(SelectionDAG & DAG,const SDLoc & DL,SDValue Val,SDValue * Parts,unsigned NumParts,MVT PartVT,std::optional<CallingConv::ID> CC) const splitValueIntoRegisterParts() argument
21469 joinRegisterPartsIntoValue(SelectionDAG & DAG,const SDLoc & DL,const SDValue * Parts,unsigned NumParts,MVT PartVT,EVT ValueVT,std::optional<CallingConv::ID> CC) const joinRegisterPartsIntoValue() argument
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp7406 unsigned NumParts = 1; LowerFormalArguments() local
8437 unsigned NumParts = 1; LowerCall() local
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/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp18476 splitValueIntoRegisterParts(SelectionDAG & DAG,const SDLoc & DL,SDValue Val,SDValue * Parts,unsigned NumParts,MVT PartVT,std::optional<CallingConv::ID> CC) const splitValueIntoRegisterParts() argument