| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 305 bool IsZExt = isa<ZExtInst>(I); isIntExtFree() local
1167 emitAddSub(bool UseAdd,MVT RetVT,const Value * LHS,const Value * RHS,bool SetFlags,bool WantResult,bool IsZExt) emitAddSub() argument
1467 emitCmp(const Value * LHS,const Value * RHS,bool IsZExt) emitCmp() argument
1490 emitICmp(MVT RetVT,const Value * LHS,const Value * RHS,bool IsZExt) emitICmp() argument
1534 emitAdd(MVT RetVT,const Value * LHS,const Value * RHS,bool SetFlags,bool WantResult,bool IsZExt) emitAdd() argument
1563 emitSub(MVT RetVT,const Value * LHS,const Value * RHS,bool SetFlags,bool WantResult,bool IsZExt) emitSub() argument
3919 bool IsZExt = Outs[0].Flags.isZExt(); selectRet() local
4010 emiti1Ext(unsigned SrcReg,MVT DestVT,bool IsZExt) emiti1Ext() argument
4102 emitLSL_ri(MVT RetVT,MVT SrcVT,unsigned Op0,uint64_t Shift,bool IsZExt) emitLSL_ri() argument
4205 emitLSR_ri(MVT RetVT,MVT SrcVT,unsigned Op0,uint64_t Shift,bool IsZExt) emitLSR_ri() argument
4321 emitASR_ri(MVT RetVT,MVT SrcVT,unsigned Op0,uint64_t Shift,bool IsZExt) emitASR_ri() argument
4401 emitIntExt(MVT SrcVT,unsigned SrcReg,MVT DestVT,bool IsZExt) emitIntExt() argument
4526 bool IsZExt = isa<ZExtInst>(I); optimizeIntExtLoad() local
4583 bool IsZExt = isa<ZExtInst>(I); selectIntExt() local
4669 bool IsZExt = true; selectMul() local
4732 bool IsZExt = I->getOpcode() != Instruction::AShr; selectShift() local
[all...] |
| H A D | AArch64ISelLowering.cpp | 17465 bool IsZExt = false; performVecReduceAddCombineWithUADDLP() local
[all...] |
| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 450 PPCEmitLoad(MVT VT,Register & ResultReg,Address & Addr,const TargetRegisterClass * RC,bool IsZExt,unsigned FP64LoadOpc) PPCEmitLoad() argument
818 PPCEmitCmp(const Value * SrcValue1,const Value * SrcValue2,bool IsZExt,unsigned DestReg,const PPC::Predicate Pred) PPCEmitCmp() argument
1808 PPCEmitIntExt(MVT SrcVT,unsigned SrcReg,MVT DestVT,unsigned DestReg,bool IsZExt) PPCEmitIntExt() argument
1905 bool IsZExt = isa<ZExtInst>(I); SelectIntExt() local
2312 bool IsZExt = false; tryToFoldLoadIntoMI() local
[all...] |
| H A D | PPCInstrInfo.cpp | 5260 bool IsZExt = definedByZeroExtendingOp(Reg, MRI); isSignOrZeroExtended() local
[all...] |
| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 1751 bool IsZExt = Outs[0].Flags.isZExt(); selectRet() local
1889 emitIntExt(MVT SrcVT,unsigned SrcReg,MVT DestVT,unsigned DestReg,bool IsZExt) emitIntExt() argument
1976 bool IsZExt = Opcode == Instruction::LShr; selectShift() local
|
| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineFrameInfo.h | 542 void setObjectZExt(int ObjectIdx, bool IsZExt) { in setObjectZExt() argument
|
| H A D | TargetLowering.h | 302 bool IsZExt : 1; global() variable
|
| /llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstructionCombining.cpp | 1049 bool IsZExt = isa<ZExtInst>(CastOp); foldBinOpOfSelectAndCastOfSelectCondition() local
3800 bool IsZExt = isa<ZExtInst>(Cond); visitSwitchInst() local
|
| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 781 bool IsZExt = (Ld->getExtensionType() == ISD::ZEXTLOAD); tryIndexedLoad() local
|