Lines Matching defs:IsZExt

205                       bool WantResult = true,  bool IsZExt = false);
223   bool emitCmp(const Value *LHS, const Value *RHS, bool IsZExt);
224   bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
237                    bool IsZExt = false);
241                    bool IsZExt = false);
259                       bool IsZExt = true);
262                       bool IsZExt = true);
265                       bool IsZExt = false);
304   bool IsZExt = isa<ZExtInst>(I);
311     if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr()))
1092                                Addr.getShift(), /*IsZExt=*/true);
1095                                Addr.getShift(), /*IsZExt=*/false);
1169                                      bool WantResult,  bool IsZExt) {
1180     ExtendType = IsZExt ? AArch64_AM::UXTB : AArch64_AM::SXTB;
1184     ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH;
1216     LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt);
1220     uint64_t Imm = IsZExt ? C->getZExtValue() : C->getSExtValue();
1296     RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
1469 bool AArch64FastISel::emitCmp(const Value *LHS, const Value *RHS, bool IsZExt) {
1484     return emitICmp(VT, LHS, RHS, IsZExt);
1492                                bool IsZExt) {
1494                  IsZExt) != 0;
1536                                   bool SetFlags, bool WantResult, bool IsZExt) {
1538                     IsZExt);
1565                                   bool SetFlags, bool WantResult, bool IsZExt) {
1567                     IsZExt);
3925       bool IsZExt = Outs[0].Flags.isZExt();
3926       SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
4016 unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) {
4024   if (IsZExt) {
4108                                      uint64_t Shift, bool IsZExt) {
4133       return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4172   unsigned Opc = OpcTable[IsZExt][Is64Bit];
4211                                      uint64_t Shift, bool IsZExt) {
4236       return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4268   if (Shift >= SrcBits && IsZExt)
4273   if (!IsZExt) {
4274     Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4279     IsZExt = true;
4288   unsigned Opc = OpcTable[IsZExt][Is64Bit];
4327                                      uint64_t Shift, bool IsZExt) {
4352       return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4384   if (Shift >= SrcBits && IsZExt)
4393   unsigned Opc = OpcTable[IsZExt][Is64Bit];
4407                                      bool IsZExt) {
4427     return emiti1Ext(SrcReg, DestVT, IsZExt);
4430       Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
4432       Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
4437       Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
4439       Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
4444     Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
4532   bool IsZExt = isa<ZExtInst>(I);
4540   if (!(IsZExt && isZExtLoad(LoadMI)) && !(!IsZExt && isSExtLoad(LoadMI)))
4549   if (IsZExt) {
4589   bool IsZExt = isa<ZExtInst>(I);
4591     if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) {
4607   unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);
4675       bool IsZExt = true;
4681             IsZExt = true;
4690             IsZExt = false;
4701           emitLSL_ri(VT, SrcVT, Src0Reg, ShiftVal, IsZExt);
4738     bool IsZExt = I->getOpcode() != Instruction::AShr;
4745           IsZExt = true;
4754           IsZExt = false;
4767       ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4770       ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4773       ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);