Lines Matching defs:IsZExt
156 const TargetRegisterClass *RC, bool IsZExt = true,
163 unsigned DestReg, bool IsZExt);
445 bool IsZExt, unsigned FP64LoadOpc) {
474 Opc = (IsZExt ? (Is32BitInt ? PPC::LHZ : PPC::LHZ8)
478 Opc = (IsZExt ? (Is32BitInt ? PPC::LWZ : PPC::LWZ8)
813 bool IsZExt, unsigned DestReg,
838 Imm = (IsZExt) ? (int64_t)CIVal.getZExtValue() :
840 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm)))
913 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW;
915 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI;
919 CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD;
921 CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI;
927 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
933 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
1438 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false))
1450 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/true))
1801 unsigned DestReg, bool IsZExt) {
1808 if (!IsZExt) {
1898 bool IsZExt = isa<ZExtInst>(I);
1924 if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt))
2305 bool IsZExt = false;
2312 IsZExt = true;
2323 IsZExt = true;
2361 if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt,