| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ExpandImm.cpp | 322 uint64_t Imm2 = MaybeDecomposition->second; in tryOrrOfLogicalImmediates() local
348 uint64_t Imm2 = MaybeDecomposition->second; in tryAndOfLogicalImmediates() local
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| /llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 204 emitII(unsigned Opcode,int16_t Imm1,int16_t Imm2,SMLoc IDLoc,const MCSubtargetInfo * STI) emitII() argument
253 emitRRIII(unsigned Opcode,unsigned Reg0,unsigned Reg1,int16_t Imm0,int16_t Imm1,int16_t Imm2,SMLoc IDLoc,const MCSubtargetInfo * STI) emitRRIII() argument
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 1676 int16_t Imm1 = 0, NewImm1 = 0, Imm2 = 0, NewImm2 = 0; eliminateRedundantCompare() local
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| H A D | PPCInstrInfo.cpp | 3253 selectReg(int64_t Imm1,int64_t Imm2,unsigned CompareOpc,unsigned TrueReg,unsigned FalseReg,unsigned CRSubReg) selectReg() argument
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| H A D | PPCISelDAGToDAG.cpp | 5067 unsigned Imm2; in tryAsSingleRLWIMI() local
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| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 2143 uint64_t Imm1, uint64_t Imm2) { in fastEmitInst_rii() argument
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 2602 bool Imm1 = Src1.isImm(), Imm2 = Src2.isImm(); evaluateHexCompare2() local
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| /llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 1471 int Imm2 = cast<ConstantSDNode>(Op.getOperand(4))->getSExtValue(); lowerINTRINSIC_VOID() local
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| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1723 Register Imm2 = Add2Def->getOperand(2).getReg(); matchPtrAddImmedChain() local
1802 Register Imm2 = Shl2Def->getOperand(2).getReg(); matchShiftImmedChain() local
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| /llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 5499 int64_t Imm1, Imm2; parseModImm() local
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