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Revision tags: llvmorg-18.1.8, llvmorg-18.1.7 |
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| #
ce1a0d8a |
| 20-May-2024 |
hanbeom <kese111@gmail.com> |
[AArch64] Optimize `MOV` to `ORR` when load symmetric constants (#86249)
This change looks for cases of symmetric constant loading.
`symmetric constant load` is when the upper 32 bits and lower 32 b
[AArch64] Optimize `MOV` to `ORR` when load symmetric constants (#86249)
This change looks for cases of symmetric constant loading.
`symmetric constant load` is when the upper 32 bits and lower 32 bits
of a 64-bit register load the same value.
When it finds this, it replaces it with an instruction that loads only
the lower 32 bits of the constant and stores it in the upper and lower
bits simultaneously.
For example:
renamable $x8 = MOVZXi 49370, 0
renamable $x8 = MOVKXi $x8, 320, 16
renamable $x8 = MOVKXi $x8, 49370, 32
renamable $x8 = MOVKXi $x8, 320, 48
becomes
renamable $x8 = MOVZXi 49370, 0
renamable $x8 = MOVKXi $x8, 320, 16
renamable $x8 = ORRXrs $x8, $x8, 32
show more ...
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Revision tags: llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3 |
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| #
f74e9f86 |
| 10-Oct-2023 |
Dougall Johnson <dougallj@gmail.com> |
[Aarch64] Materialize immediates with 64-bit ORR + EOR if shorter (#68287)
A number of useful constants can be encoded with a 64-bit ORR followed
by a 64-bit EOR, including all remaining repeated b
[Aarch64] Materialize immediates with 64-bit ORR + EOR if shorter (#68287)
A number of useful constants can be encoded with a 64-bit ORR followed
by a 64-bit EOR, including all remaining repeated byte patterns, some
useful repeated 16-bit patterns, and some irregular masks. This patch
prioritizes that encoding over three or four instruction encodings.
Encoding with MOV + MOVK or ORR + MOVK is still preferred for fast
literal generation and readability respectively.
The method devises three candidate values, and checks if both Candidate
and (Imm ^ Candidate) are valid logical immediates. If so, Imm is
materialized with:
```
ORR Xd, XZR, #(Imm ^ Candidate)
EOR Xd, Xd, #(Candidate)
```
The method has been exhaustively tested to ensure it can solve all
possible values (excluding 0, ~0, and plain logical immediates, which
are handled earlier).
show more ...
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Revision tags: llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3 |
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| #
df77dec9 |
| 14-Feb-2023 |
Kazu Hirata <kazu@google.com> |
[AArch64] Use llvm::rotl and llvm::rotr (NFC)
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| #
df3b703a |
| 12-Feb-2023 |
Kazu Hirata <kazu@google.com> |
[AArch64] Use llvm::countr_{zero,one} (NFC)
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Revision tags: llvmorg-16.0.0-rc2 |
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| #
b72330cd |
| 05-Feb-2023 |
Simon Pilgrim <llvm-dev@redking.me.uk> |
[AArch64] AArch64ExpandImm.cpp - fix MSVC "32-bit shift implicitly converted to 64 bits" warning. NFC.
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Revision tags: llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7 |
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| #
ae51a828 |
| 04-Jan-2023 |
Owen Anderson <resistor@mac.com> |
Teach the AArch64 backend to materialize immediates using a pair of ORR-immediate
instructions.
Credit to czwarich for figuring out the algorithm to test for this.
Re-applied with fix for ubsan err
Teach the AArch64 backend to materialize immediates using a pair of ORR-immediate
instructions.
Credit to czwarich for figuring out the algorithm to test for this.
Re-applied with fix for ubsan error on out-of-range shift.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D140952
show more ...
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| #
80fe7721 |
| 05-Feb-2023 |
Owen Anderson <resistor@mac.com> |
Revert "Teach the AArch64 backend to materialize immediates using a pair of ORR-immediate"
This reverts commit 8d433a0ae55ac25ba0a77d733e1ee5e23d1eb9f7 due to test failures on
CodeGen/AArch64/Global
Revert "Teach the AArch64 backend to materialize immediates using a pair of ORR-immediate"
This reverts commit 8d433a0ae55ac25ba0a77d733e1ee5e23d1eb9f7 due to test failures on
CodeGen/AArch64/GlobalISel/store-merging.ll
show more ...
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| #
8d433a0a |
| 04-Jan-2023 |
Owen Anderson <resistor@mac.com> |
Teach the AArch64 backend to materialize immediates using a pair of ORR-immediate
instructions.
Credit to czwarich for figuring out the algorithm to test for this.
Reviewed By: dmgreen
Differentia
Teach the AArch64 backend to materialize immediates using a pair of ORR-immediate
instructions.
Credit to czwarich for figuring out the algorithm to test for this.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D140952
show more ...
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| #
e0782018 |
| 28-Jan-2023 |
Kazu Hirata <kazu@google.com> |
[Target] Use llvm::count{l,r}_{zero,one} (NFC)
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Revision tags: llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1, llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2 |
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| #
d395befa |
| 11-Dec-2021 |
Kazu Hirata <kazu@google.com> |
[llvm] Use range-based for loops (NFC)
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Revision tags: llvmorg-13.0.1-rc1, llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3, llvmorg-13.0.0-rc2, llvmorg-13.0.0-rc1, llvmorg-14-init, llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3, llvmorg-12.0.1-rc2, llvmorg-12.0.1-rc1 |
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| #
7b0756a5 |
| 05-May-2021 |
Fangrui Song <i@maskray.me> |
[AArch64] Fix some coding standard issues related to namespace llvm
https://llvm.org/docs/CodingStandards.html#use-namespace-qualifiers-to-implement-previously-declared-functions
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Revision tags: llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4, llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2, llvmorg-11.1.0, llvmorg-11.1.0-rc3, llvmorg-12.0.0-rc1, llvmorg-13-init, llvmorg-11.1.0-rc2, llvmorg-11.1.0-rc1, llvmorg-11.0.1, llvmorg-11.0.1-rc2, llvmorg-11.0.1-rc1, llvmorg-11.0.0, llvmorg-11.0.0-rc6, llvmorg-11.0.0-rc5, llvmorg-11.0.0-rc4, llvmorg-11.0.0-rc3, llvmorg-11.0.0-rc2, llvmorg-11.0.0-rc1, llvmorg-12-init, llvmorg-10.0.1, llvmorg-10.0.1-rc4, llvmorg-10.0.1-rc3, llvmorg-10.0.1-rc2, llvmorg-10.0.1-rc1, llvmorg-10.0.0, llvmorg-10.0.0-rc6, llvmorg-10.0.0-rc5, llvmorg-10.0.0-rc4, llvmorg-10.0.0-rc3, llvmorg-10.0.0-rc2, llvmorg-10.0.0-rc1, llvmorg-11-init, llvmorg-9.0.1, llvmorg-9.0.1-rc3, llvmorg-9.0.1-rc2, llvmorg-9.0.1-rc1, llvmorg-9.0.0, llvmorg-9.0.0-rc6, llvmorg-9.0.0-rc5, llvmorg-9.0.0-rc4, llvmorg-9.0.0-rc3, llvmorg-9.0.0-rc2, llvmorg-9.0.0-rc1, llvmorg-10-init, llvmorg-8.0.1, llvmorg-8.0.1-rc4, llvmorg-8.0.1-rc3, llvmorg-8.0.1-rc2, llvmorg-8.0.1-rc1 |
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| #
92d0d133 |
| 25-Mar-2019 |
Eli Friedman <efriedma@quicinc.com> |
[AArch64] Prefer "mov" over "orr" to materialize constants.
This is generally more readable due to the way the assembler aliases
work.
(This causes a lot of test changes, but it's not really as sca
[AArch64] Prefer "mov" over "orr" to materialize constants.
This is generally more readable due to the way the assembler aliases
work.
(This causes a lot of test changes, but it's not really as scary as it
looks at first glance; it's just mechanically changing a bunch of checks
for orr to check for mov instead.)
Differential Revision: https://reviews.llvm.org/D59720
llvm-svn: 356954
show more ...
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| #
8a595b1d |
| 18-Mar-2019 |
Adhemerval Zanella <adhemerval.zanella@linaro.org> |
[AArch64] Refactor floating point materialization. NFC
It splits the login of actual instruction emission away from the logic
that figures out the appropriate sequence on AArch64ExpandPseudo::expand
[AArch64] Refactor floating point materialization. NFC
It splits the login of actual instruction emission away from the logic
that figures out the appropriate sequence on AArch64ExpandPseudo::expandMOVImm.
The new function AArch64_IMM::expandMOVImm, which return the list of the
instructions to materialize the immediate constant, is implemented on a
separated unit because it will be used in a subsequent patch to optimize
floating point materialization.
Reviewers: efriedma
Differential Revision: https://reviews.llvm.org/D58915
llvm-svn: 356387
show more ...
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