| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64MIPeepholeOpt.cpp | 205 __anon0cefc1b50202(T Imm, unsigned RegSize, T &Imm0, T &Imm1) visitAND() argument
212 __anon0cefc1b50302(MachineInstr &MI, OpcodePair Opcode, unsigned Imm0, unsigned Imm1, Register SrcReg, Register NewTmpReg, Register NewDstReg) visitAND() argument
331 splitAddSubImm(T Imm,unsigned RegSize,T & Imm0,T & Imm1) splitAddSubImm() argument
376 __anon0cefc1b50402(T Imm, unsigned RegSize, T &Imm0, T &Imm1) visitADDSUB() argument
385 __anon0cefc1b50502(MachineInstr &MI, OpcodePair Opcode, unsigned Imm0, unsigned Imm1, Register SrcReg, Register NewTmpReg, Register NewDstReg) visitADDSUB() argument
413 __anon0cefc1b50602(T Imm, unsigned RegSize, T &Imm0, T &Imm1) visitADDSSUBS() argument
431 __anon0cefc1b50702(MachineInstr &MI, OpcodePair Opcode, unsigned Imm0, unsigned Imm1, Register SrcReg, Register NewTmpReg, Register NewDstReg) visitADDSSUBS() argument
[all...] |
| H A D | AArch64ExpandImm.cpp | 321 uint64_t Imm1 = MaybeDecomposition->first; in tryOrrOfLogicalImmediates() local
347 uint64_t Imm1 = MaybeDecomposition->first; in tryAndOfLogicalImmediates() local
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| /llvm-project/llvm/lib/ExecutionEngine/JITLink/ |
| H A D | aarch32.cpp | 113 uint32_t Imm1 = (Value >> 11) & 0x01; encodeImmMovtT1MovwT3() local
126 uint32_t Imm1 = (Hi >> 10) & 0x01; decodeImmMovtT1MovwT3() local
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| /llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 204 emitII(unsigned Opcode,int16_t Imm1,int16_t Imm2,SMLoc IDLoc,const MCSubtargetInfo * STI) emitII() argument
252 emitRRIII(unsigned Opcode,unsigned Reg0,unsigned Reg1,int16_t Imm0,int16_t Imm1,int16_t Imm2,SMLoc IDLoc,const MCSubtargetInfo * STI) emitRRIII() argument
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 1676 int16_t Imm1 = 0, NewImm1 = 0, Imm2 = 0, NewImm2 = 0; eliminateRedundantCompare() local
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| H A D | PPCInstrInfo.cpp | 3253 selectReg(int64_t Imm1,int64_t Imm2,unsigned CompareOpc,unsigned TrueReg,unsigned FalseReg,unsigned CRSubReg) selectReg() argument
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| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 2143 uint64_t Imm1, uint64_t Imm2) { in fastEmitInst_rii() argument
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 2602 bool Imm1 = Src1.isImm(), Imm2 = Src2.isImm(); evaluateHexCompare2() local
|
| /llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 1470 unsigned Imm1 = Op2->getAsZExtVal(); lowerINTRINSIC_VOID() local
|
| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1713 Register Imm1 = MI.getOperand(2).getReg(); matchPtrAddImmedChain() local
1792 Register Imm1 = MI.getOperand(2).getReg(); matchShiftImmedChain() local
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| /llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 5499 int64_t Imm1, Imm2; parseModImm() local
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 56221 unsigned Imm1 = Ops[1].getConstantOperandVal(2); combineConcatVectorOps() local
56243 unsigned Imm1 = Ops[1].getConstantOperandVal(2); combineConcatVectorOps() local
[all...] |