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Searched defs:DstRC (Results 1 – 25 of 32) sorted by relevance

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/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInstructionSelect.cpp184 const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg); runOnMachineFunction() local
247 auto DstRC = MRI.getRegClass(DstReg); runOnMachineFunction() local
/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp286 const TargetRegisterClass *DstRC = getRegClassFromGRPhysReg(DstReg); selectCopy() local
314 const TargetRegisterClass *DstRC = selectCopy() local
750 canTurnIntoCOPY(const TargetRegisterClass * DstRC,const TargetRegisterClass * SrcRC) canTurnIntoCOPY() argument
759 selectTurnIntoCOPY(MachineInstr & I,MachineRegisterInfo & MRI,const unsigned DstReg,const TargetRegisterClass * DstRC,const unsigned SrcReg,const TargetRegisterClass * SrcRC) const selectTurnIntoCOPY() argument
794 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); selectTruncOrPtrToInt() local
923 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); selectAnyext() local
1153 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); selectUAddSub() local
1284 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI); emitExtractSubreg() local
1324 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI); emitInsertSubreg() local
1844 const TargetRegisterClass *DstRC = getRegClass(Ty, DstReg, MRI); selectSelect() local
[all...]
/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp202 const TargetRegisterClass *DstRC = DstReg.isVirtual() getCopyRegClasses() local
210 isVGPRToSGPRCopy(const TargetRegisterClass * SrcRC,const TargetRegisterClass * DstRC,const SIRegisterInfo & TRI) isVGPRToSGPRCopy() argument
217 isSGPRToVGPRCopy(const TargetRegisterClass * SrcRC,const TargetRegisterClass * DstRC,const SIRegisterInfo & TRI) isSGPRToVGPRCopy() argument
285 const TargetRegisterClass *SrcRC, *DstRC; foldVGPRCopyIntoRegSequence() local
631 const TargetRegisterClass *SrcRC, *DstRC; runOnMachineFunction() local
764 const TargetRegisterClass *SrcRC, *DstRC; runOnMachineFunction() local
914 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); analyzeVGPRToSGPRCopy() local
[all...]
H A DAMDGPUInstructionSelector.cpp112 const TargetRegisterClass *DstRC constrainCopyLikeIntrin() local
512 const TargetRegisterClass *DstRC = selectG_EXTRACT() local
551 const TargetRegisterClass *DstRC = selectG_MERGE_VALUES() local
612 const TargetRegisterClass *DstRC = selectG_UNMERGE_VALUES() local
812 const TargetRegisterClass *DstRC = selectG_INSERT() local
1466 const TargetRegisterClass *DstRC = TRI.getRegClassForSizeOnBank(32, *DstBank); selectRelocConstant() local
2230 const TargetRegisterClass *DstRC = selectG_TRUNC() local
2378 const TargetRegisterClass *DstRC = selectG_SZA_EXT() local
2613 const TargetRegisterClass *DstRC = selectG_CONSTANT() local
2946 const TargetRegisterClass *DstRC = TRI.getRegClassForTypeOnBank(Ty, *DstRB); selectG_PTRMASK() local
3066 const TargetRegisterClass *DstRC = selectG_EXTRACT_VECTOR_ELT() local
[all...]
/llvm-project/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp69 const TargetRegisterClass *DstRC, in isCrossCopy()
354 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes() local
447 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in isUndefInput() local
H A DMachineCombiner.cpp177 auto DstRC = MRI->getRegClass(Dst); isTransientMI() local
186 auto DstRC = MRI->getRegClass(Dst); isTransientMI() local
194 auto DstRC = MRI->getRegClass(Dst); isTransientMI() local
H A DRegisterCoalescer.cpp493 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); setRegisters() local
1388 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); reMaterializeTrivialDef() local
1982 auto DstRC = MRI->getRegClass(CP.getDstReg()); joinCopy() local
[all...]
H A DMachineVerifier.cpp1140 const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(Dst); verifyPreISelGenericInstruction() local
2198 const TargetRegisterClass *DstRC = visitMachineInstrBefore() local
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXCopy.cpp120 const TargetRegisterClass *DstRC = &PPC::VSLRCRegClass; processBlock() local
H A DPPCVSXSwapRemoval.cpp924 Register NewVReg = MRI->createVirtualRegister(DstRC); in handleSpecialSwappables() local
H A DPPCMIPeephole.cpp1239 const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(DstReg); simplifyCode() local
/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostSelectOptimize.cpp134 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in foldSimpleCrossClassCopies() local
H A DAArch64InstructionSelector.cpp1011 const TargetRegisterClass *DstRC; selectCopy() local
3146 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB); select() local
3459 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB); select() local
3669 emitScalarToVector(unsigned EltSize,const TargetRegisterClass * DstRC,Register Scalar,MachineIRBuilder & MIRBuilder) const emitScalarToVector() argument
3761 auto *DstRC = &AArch64::GPR64RegClass; selectMergeValues() local
3832 const TargetRegisterClass *DstRC = emitExtractVectorElt() local
4454 const TargetRegisterClass *DstRC = emitVectorConcat() local
5084 const TargetRegisterClass *DstRC = &AArch64::FPR128RegClass; emitLaneInsert() local
5678 const TargetRegisterClass *DstRC = tryOptBuildVecToSubregToReg() local
5711 const TargetRegisterClass *DstRC = &AArch64::FPR128RegClass; selectBuildVector() local
[all...]
/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.cpp315 shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS) const shouldCoalesce() argument
/llvm-project/llvm/utils/TableGen/
H A DFastISelEmitter.cpp219 const CodeGenRegisterClass *DstRC = nullptr; in initialize() local
494 const CodeGenRegisterClass *DstRC = nullptr; collectPatterns() local
[all...]
/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp355 shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS) const shouldCoalesce() argument
/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp382 shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS) const shouldCoalesce() argument
/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp896 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank( selectCopy() local
919 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank( selectImplicitDef() local
/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCInstructionSelector.cpp139 const TargetRegisterClass *DstRC = in selectCopy() local
/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp154 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; EmitCopyFromReg() local
642 const TargetRegisterClass *DstRC = EmitCopyToRegClassNode() local
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.cpp1054 shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS) const shouldCoalesce() argument
/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.cpp880 shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS) const shouldCoalesce() argument
H A DARMFastISel.cpp2061 Register ResultReg = createResultReg(DstRC); in FinishCall() local
2041 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT); FinishCall() local
/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp262 unsigned VRegSize = RegInfo.getRegSizeInBits(*DstRC) / 16; in expandCopyACC() local
/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h1116 shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS) shouldCoalesce() argument

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