Lines Matching defs:DstRC

111   const TargetRegisterClass *DstRC
115   if (!DstRC || DstRC != SrcRC)
118   return RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI) &&
609   const TargetRegisterClass *DstRC =
611   if (!DstRC || !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI))
648   const TargetRegisterClass *DstRC =
650   if (!DstRC)
653   ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(DstRC, SrcSize / 8);
667   if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI))
709     const TargetRegisterClass *DstRC =
711     if (DstRC && !RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI))
909   const TargetRegisterClass *DstRC =
911   if (!DstRC)
927   if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) ||
1648   const TargetRegisterClass *DstRC = TRI.getRegClassForSizeOnBank(32, *DstBank);
1649   if (!DstRC || !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI))
2411   const TargetRegisterClass *DstRC =
2413   if (!SrcRC || !DstRC)
2417       !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) {
2422   if (DstRC == &AMDGPU::VGPR_16RegClass && SrcSize == 32) {
2436     Register LoReg = MRI->createVirtualRegister(DstRC);
2437     Register HiReg = MRI->createVirtualRegister(DstRC);
2457       Register TmpReg0 = MRI->createVirtualRegister(DstRC);
2458       Register TmpReg1 = MRI->createVirtualRegister(DstRC);
2459       Register ImmReg = MRI->createVirtualRegister(DstRC);
2570     const TargetRegisterClass *DstRC =
2582     return RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) &&
3089   const TargetRegisterClass *DstRC = TRI.getRegClassForTypeOnBank(Ty, *DstRB);
3094   if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) ||
3209   const TargetRegisterClass *DstRC =
3211   if (!SrcRC || !DstRC)
3214       !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) ||
5909   const TargetRegisterClass *DstRC =
5911   if (!DstRC || !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI))
6032     const TargetRegisterClass *DstRC =
6034     if (!DstRC || !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI))