| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCOptAddrMode.cpp | 297 Register BaseReg = Ldst->getOperand(BasePos).getReg(); in canJoinInstructions() local
353 MachineOperand &Incr, unsigned BaseReg) { in canFixPastUses() argument
459 Register BaseReg = Ldst.getOperand(BasePos).getReg(); in changeToAddrMode() local
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| H A D | ARCRegisterInfo.cpp | 46 unsigned BaseReg = FrameReg; in replaceFrameIndex() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FixupLEAs.cpp | 458 Register BaseReg = LeaI->getOperand(1 + X86::AddrBaseReg).getReg(); in checkRegUsage() local
507 Register BaseReg = I->getOperand(1 + X86::AddrBaseReg).getReg(); in optLEAALU() local
566 Register BaseReg = Base.getReg(); in optTwoAddrLEA() local
759 Register BaseReg = Base.getReg(); in processInstrForSlow3OpLEA() local
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| H A D | X86AsmPrinter.cpp | 377 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); PrintLeaMemReference() local
473 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); PrintIntelMemReference() local
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| H A D | X86InsertPrefetch.cpp | 84 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg(); IsMemOpCompatibleWithPrefetch() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LocalStackSlotAllocation.cpp | 272 lookupCandidateBaseReg(unsigned BaseReg,int64_t BaseOffset,int64_t FrameSizeAdjust,int64_t LocalFrameOffset,const MachineInstr & MI,const TargetRegisterInfo * TRI) lookupCandidateBaseReg() argument
345 Register BaseReg; insertFrameReferenceRegisters() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.h | 49 auto BaseReg = MI.getOperand(0).getReg(); in isLDMBaseRegInList() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 497 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
527 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
535 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
548 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
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| H A D | ThumbRegisterInfo.cpp | 126 const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, in emitThumbRegPlusImmInReg()
254 Register BaseReg, int NumBytes, in emitThumbRegPlusImmediate()
521 void ThumbRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
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| H A D | ARMBaseRegisterInfo.cpp | 681 Register BaseReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in materializeFrameBaseRegister() local
693 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex() argument
722 Register BaseReg, in isFrameOffsetLegal() argument
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FalkorHWPFFix.cpp | 214 Register BaseReg; member
643 Register BaseReg = MI.getOperand(BaseRegIdx).getReg(); in getLoadInfo() local
[all...] |
| H A D | AArch64StorePairSuppress.cpp | 160 Register BaseReg = BaseOp->getReg(); runOnMachineFunction() local
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| H A D | AArch64RegisterInfo.cpp | 758 isFrameOffsetLegal(const MachineInstr * MI,Register BaseReg,int64_t Offset) const isFrameOffsetLegal() argument
780 Register BaseReg = MRI.createVirtualRegister(&AArch64::GPR64spRegClass); materializeFrameBaseRegister() local
792 resolveFrameIndex(MachineInstr & MI,Register BaseReg,int64_t Offset) const resolveFrameIndex() argument
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| H A D | AArch64LoadStoreOptimizer.cpp | 1297 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(LoadMI).getReg(); findMatchingStore() local
1692 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(FirstMI).getReg(); findMatchingInsn() local
2053 isMatchingUpdateInsn(MachineInstr & MemMI,MachineInstr & MI,unsigned BaseReg,int Offset) isMatchingUpdateInsn() argument
2104 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(MemMI).getReg(); findMatchingUpdateInsnForward() local
2182 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(MemMI).getReg(); findMatchingUpdateInsnBackward() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelDAGToDAG.cpp | 79 SelectGlobalValueVariableOffset(SDValue Addr,SDValue & BaseReg,SDValue & Offset) SelectGlobalValueVariableOffset() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVRegisterInfo.cpp | 607 isFrameOffsetLegal(const MachineInstr * MI,Register BaseReg,int64_t Offset) const isFrameOffsetLegal() argument
634 Register BaseReg = MFI.createVirtualRegister(&RISCV::GPRRegClass); materializeFrameBaseRegister() local
643 resolveFrameIndex(MachineInstr & MI,Register BaseReg,int64_t Offset) const resolveFrameIndex() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LoadStoreOpt.cpp | 87 Register BaseReg; in getPointerInfo() local
206 Register BaseReg; instMayAlias() local
730 Register BaseReg; mergeTruncStore() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86IntelInstPrinter.cpp | 383 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printMemReference() local
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| H A D | X86ATTInstPrinter.cpp | 426 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); in printMemReference() local
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| H A D | X86MCTargetDesc.cpp | 665 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); in evaluateMemoryOperandAddress() local
691 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); in getMemoryOperandRelocationOffset() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiMemAluCombiner.cpp | 373 BaseReg = MBBIter->getOperand(1).getReg(); in combineMemAluInBasicBlock() local
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| /freebsd-src/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/ |
| H A D | Store.cpp | 296 const MemRegion *BaseReg = MRMgr.getCXXBaseObjectRegion( in evalDerivedToBase() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | LoopStrengthReduce.cpp | 618 for (const SCEV *BaseReg : BaseRegs) hasRegsUsedByUsesOtherThan() local
635 for (const SCEV *BaseReg : BaseRegs) { print() local
1387 for (const SCEV *BaseReg : F.BaseRegs) { RateFormula() local
1597 for (const SCEV *BaseReg : F.BaseRegs) InsertFormula() local
3446 for (const SCEV *BaseReg : F.BaseRegs) CountRegisters() local
3684 const SCEV *BaseReg = IsScaledReg ? Base.ScaledReg : Base.BaseRegs[Idx]; GenerateReassociationsImpl() local
3804 for (const SCEV *BaseReg : Base.BaseRegs) { GenerateCombinations() local
3993 for (const SCEV *BaseReg : Base.BaseRegs) GenerateICmpZeroScales() local
4203 for (const SCEV *&BaseReg : F.BaseRegs) { GenerateTruncates() local
4387 const SCEV *BaseReg = F.BaseRegs[N]; GenerateCrossUseConstantOffsets() local
4970 for (const SCEV *BaseReg : F.BaseRegs) { NarrowSearchSpaceByDeletingCostlyFormulas() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCRegisterInfo.cpp | 1915 Register BaseReg = MRI.createVirtualRegister(RC); in materializeFrameBaseRegister() local
1924 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex() argument
1949 Register BaseReg, in isFrameOffsetLegal() argument
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