Lines Matching defs:BaseReg

746   for (const SCEV *BaseReg : BaseRegs)
747     if (RegUses.isRegUsedByUsesOtherThan(BaseReg, LUIdx))
763   for (const SCEV *BaseReg : BaseRegs) {
765     OS << "reg(" << *BaseReg << ')';
1523   for (const SCEV *BaseReg : F.BaseRegs) {
1524     if (VisitedRegs.count(BaseReg)) {
1528     RatePrimaryRegister(F, BaseReg, Regs, LoserRegs);
1738   for (const SCEV *BaseReg : F.BaseRegs)
1739     assert(!BaseReg->isZero() && "Zero allocated in a base register!");
1854       // ICmpZero     BaseReg + BaseOffset => ICmp BaseReg, -BaseOffset
1864     // ICmpZero BaseReg + -1*ScaleReg => ICmp BaseReg, ScaleReg
3681   for (const SCEV *BaseReg : F.BaseRegs)
3682     RegUses.countRegister(BaseReg, LUIdx);
3919   const SCEV *BaseReg = IsScaledReg ? Base.ScaledReg : Base.BaseRegs[Idx];
3924   if (AMK == TTI::AMK_PostIndexed && mayUsePostIncMode(TTI, LU, BaseReg, L, SE))
3927   const SCEV *Remainder = CollectSubexprs(BaseReg, nullptr, AddOps, L, SE);
4045   for (const SCEV *BaseReg : Base.BaseRegs) {
4046     if (SE.properlyDominates(BaseReg, L->getHeader()) &&
4047         !SE.hasComputableLoopEvolution(BaseReg, L)) {
4049         CombinedIntegerType = SE.getEffectiveSCEVType(BaseReg->getType());
4050       Ops.push_back(BaseReg);
4053       NewBase.BaseRegs.push_back(BaseReg);
4240   for (const SCEV *BaseReg : Base.BaseRegs)
4241     if (BaseReg->getType()->isPointerTy())
4454       for (const SCEV *&BaseReg : F.BaseRegs) {
4456             getAnyExtendConsideringPostIncUses(Loops, BaseReg, SrcTy, SE);
4461         BaseReg = NewBaseReg;
4660           const SCEV *BaseReg = F.BaseRegs[N];
4661           if (BaseReg != OrigReg)
4680           NewF.BaseRegs[N] = SE.getAddExpr(NegImmS, BaseReg);
5257       for (const SCEV *BaseReg : F.BaseRegs) {
5258         if (UniqRegs.count(BaseReg))
5260         FRegNum += RegNumMap[BaseReg] / LU.getNotSelectedProbability(BaseReg);
5261         if (isa<SCEVAddRecExpr>(BaseReg))
5263               RegNumMap[BaseReg] / LU.getNotSelectedProbability(BaseReg);