Lines Matching defs:BaseReg

185                             unsigned BaseReg, int Offset);
1299   Register BaseReg = AArch64InstrInfo::getLdStBaseOp(LoadMI).getReg();
1324     // it's unnecessary to check if BaseReg is modified by the store itself.
1328         BaseReg == AArch64InstrInfo::getLdStBaseOp(MI).getReg() &&
1344     if (!ModifiedRegUnits.available(BaseReg))
1694   Register BaseReg = AArch64InstrInfo::getLdStBaseOp(FirstMI).getReg();
1765       if (BaseReg == MIBaseReg) {
1839         // If the BaseReg has been modified, then we cannot do the optimization.
1845         if (!ModifiedRegUnits.available(BaseReg))
1940     if (!ModifiedRegUnits.available(BaseReg)) {
2055                                                unsigned BaseReg, int Offset) {
2071     if (MI.getOperand(0).getReg() != BaseReg ||
2072         MI.getOperand(1).getReg() != BaseReg)
2106   Register BaseReg = AArch64InstrInfo::getLdStBaseOp(MemMI).getReg();
2126       if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
2140   const bool BaseRegSP = BaseReg == AArch64::SP;
2158     if (isMatchingUpdateInsn(*I, MI, BaseReg, UnscaledOffset))
2168     if (!ModifiedRegUnits.available(BaseReg) ||
2169         !UsedRegUnits.available(BaseReg) ||
2184   Register BaseReg = AArch64InstrInfo::getLdStBaseOp(MemMI).getReg();
2197       if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
2202   const bool BaseRegSP = BaseReg == AArch64::SP;
2230     if (isMatchingUpdateInsn(*I, MI, BaseReg, Offset)) {
2243     if (!ModifiedRegUnits.available(BaseReg) ||
2244         !UsedRegUnits.available(BaseReg))