[MIPS GlobalISel] Select fpext and fptrunc

Select G_FPEXT and G_FPTRUNC for MIPS32.

Differential Revision: https://reviews.llvm.org/D62902

llvm-svn: 362689

[MIPS GlobalISel] Select fcmp

Select floating point compare for MIPS32.

Differential Revision: https://reviews.llvm.org/D62721

llvm-svn: 362603

[MIPS GlobalISel] Handle position independent code

Handle position independent code for MIPS32.
When callee is global address, lower call will emit callee
as G_GLOBAL_VALUE and add target flag if n

[MIPS GlobalISel] Handle position independent code

Handle position independent code for MIPS32.
When callee is global address, lower call will emit callee
as G_GLOBAL_VALUE and add target flag if needed.
Support $gp in getRegBankFromRegClass().
Select G_GLOBAL_VALUE, specially handle case when
there are target flags attached by lowerCall.

Differential Revision: https://reviews.llvm.org/D62589

llvm-svn: 362210

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[MIPS GlobalISel] Select floating point arithmetic operations

Select 32 and 64 bit floating point add, sub, mul and div for MIPS32.

Differential Revision: https://reviews.llvm.org/D60191

llvm-svn:

[MIPS GlobalISel] Select floating point arithmetic operations

Select 32 and 64 bit floating point add, sub, mul and div for MIPS32.

Differential Revision: https://reviews.llvm.org/D60191

llvm-svn: 357584

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[mips] Use AltOrders to prevent using odd FP-registers

To disable using of odd floating-point registers (O32 ABI and
-mno-odd-spreg command line option) such registers and their
super-registers adde

[mips] Use AltOrders to prevent using odd FP-registers

To disable using of odd floating-point registers (O32 ABI and
-mno-odd-spreg command line option) such registers and their
super-registers added to the set of reserved registers. In general, it
works. But there is at least one problem - in case of enabled machine
verifier pass some floating-point tests failed because live ranges of
register units that are reserved is not empty and verification pass
failed with "Live segment doesn't end at a valid instruction" error
message.

There is D35985 patch which tries to solve the problem by explicit
removing of register units. This solution did not get approval.

I would like to use another approach for prevent using odd floating
point registers - define `AltOrders` and `AltOrderSelect` for MIPS
floating point register classes. Such `AltOrders` contains reduced set
of registers. At first glance, such solution does not break any test
cases and allows enabling machine instruction verification for all MIPS
test cases.

Differential Revision: http://reviews.llvm.org/D59799

llvm-svn: 357472

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[MIPS GlobalISel] Select float constants

Select 32 and 64 bit float constants for MIPS32.

Differential Revision: https://reviews.llvm.org/D59933

llvm-svn: 357183

[MIPS GlobalISel] Add floating point register bank

Add floating point register bank for MIPS32.
Implement getRegBankFromRegClass for float register classes.

Differential Revision: https://reviews.l

[MIPS GlobalISel] Add floating point register bank

Add floating point register bank for MIPS32.
Implement getRegBankFromRegClass for float register classes.

Differential Revision: https://reviews.llvm.org/D59643

llvm-svn: 356883

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[MIPS GlobalISel] Select G_UMULH

Legalize G_UMULO and select G_UMULH for MIPS32.

Differential Revision: https://reviews.llvm.org/D58714

llvm-svn: 355177

[MIPS GlobalISel] Select branch instructions

Select G_BR and G_BRCOND for MIPS32.
Unconditional branch G_BR does not have register operand,
for that reason we only add tests.
Since conditional branc

[MIPS GlobalISel] Select branch instructions

Select G_BR and G_BRCOND for MIPS32.
Unconditional branch G_BR does not have register operand,
for that reason we only add tests.
Since conditional branch G_BRCOND compares register to zero on MIPS32,
explicit extension must be performed on i1 condition in order to set
high bits to appropriate value.

Differential Revision: https://reviews.llvm.org/D58182

llvm-svn: 354022

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[MIPS GlobalISel] Select mul

Legalize and select G_MUL for s32 and smaller types for MIPS32.

Differential Revision: https://reviews.llvm.org/D57816

llvm-svn: 353506

[MIPS GlobalISel] Select sub

Lower G_USUBO and G_USUBE. Add narrowScalar for G_SUB.
Legalize and select G_SUB for MIPS 32.

Differential Revision: https://reviews.llvm.org/D53416

llvm-svn: 352351

[MIPS GlobalISel] Select zero extending and sign extending load

Select zero extending and sign extending load for MIPS32.
Use size from MachineMemOperand to determine number of bytes to load.

Diffe

[MIPS GlobalISel] Select zero extending and sign extending load

Select zero extending and sign extending load for MIPS32.
Use size from MachineMemOperand to determine number of bytes to load.

Differential Revision: https://reviews.llvm.org/D57099

llvm-svn: 352038

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Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the ne

Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.

Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.

llvm-svn: 351636

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[MIPS GlobalISel] Select G_SELECT

Add widen scalar for type index 1 (i1 condition) for G_SELECT.
Select G_SELECT for pointer, s32(integer) and smaller low level
types on MIPS32.

Differential Revisi

[MIPS GlobalISel] Select G_SELECT

Add widen scalar for type index 1 (i1 condition) for G_SELECT.
Select G_SELECT for pointer, s32(integer) and smaller low level
types on MIPS32.

Differential Revision: https://reviews.llvm.org/D56001

llvm-svn: 350063

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[MIPS GlobalISel] Select G_SDIV, G_UDIV, G_SREM and G_UREM

Add support for s64 libcalls for G_SDIV, G_UDIV, G_SREM and G_UREM
and use integer type of correct size when creating arguments for
CLI.low

[MIPS GlobalISel] Select G_SDIV, G_UDIV, G_SREM and G_UREM

Add support for s64 libcalls for G_SDIV, G_UDIV, G_SREM and G_UREM
and use integer type of correct size when creating arguments for
CLI.lowerCall.
Select G_SDIV, G_UDIV, G_SREM and G_UREM for types s8, s16, s32 and s64
on MIPS32.

Differential Revision: https://reviews.llvm.org/D55651

llvm-svn: 349499

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[mips][microMIPS] Fix the definition of MOVEP instruction

The patch fixes definition of MOVEP instruction. Two registers are used
instead of register pairs. This is necessary as machine verifier can

[mips][microMIPS] Fix the definition of MOVEP instruction

The patch fixes definition of MOVEP instruction. Two registers are used
instead of register pairs. This is necessary as machine verifier cannot
handle register pairs.

Patch by Milena Vujosevic Janicic.

Differential revision: https://reviews.llvm.org/D52035

llvm-svn: 342571

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[MIPS GlobalISel] Select icmp

Select 32bit integer compare instructions for MIPS32.

Patch by Petar Avramovic.

Differential Revision: https://reviews.llvm.org/D51489

llvm-svn: 341840

[MIPS GlobalISel] Select bitwise instructions

Select bitwise instructions for i32.

Patch by Petar Avramovic.

Differential Revision: https://reviews.llvm.org/D50183

llvm-svn: 340258

[MIPS GlobalISel] Select global address

Select G_GLOBAL_VALUE for position dependent code.

Patch by Petar Avramovic.

Differential Revision: https://reviews.llvm.org/D49803

llvm-svn: 338499

[MIPS GlobalISel] Select instructions to load and store i32 on stack

Add code for selection of G_LOAD, G_STORE, G_GEP, G_FRAMEINDEX and
G_CONSTANT. Support loads and stores of i32 values.

Patch by

[MIPS GlobalISel] Select instructions to load and store i32 on stack

Add code for selection of G_LOAD, G_STORE, G_GEP, G_FRAMEINDEX and
G_CONSTANT. Support loads and stores of i32 values.

Patch by Petar Avramovic.

Differential Revision: https://reviews.llvm.org/D48957

llvm-svn: 337168

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[MIPS GlobalISel] remove superfluous #includes (NFC)

Remove superfluous #includes.
Minor code style change in MipsCallLowering::lowerFormalArguments().

llvm-svn: 329926

[MIPS GlobalISel] Select add i32, i32

Add the minimal support necessary to lower a function that returns the
sum of two i32 values.
Support argument/return lowering of i32 values through registers o

[MIPS GlobalISel] Select add i32, i32

Add the minimal support necessary to lower a function that returns the
sum of two i32 values.
Support argument/return lowering of i32 values through registers only.
Add tablegen for regbankselect and instructionselect.

Patch by Petar Avramovic.

Differential Revision: https://reviews.llvm.org/D44304

llvm-svn: 329819

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[MIPS GlobalISel] Adding GlobalISel

Add GlobalISel infrastructure up to the point where we can select a ret
void.

Patch by Petar Avramovic.

Differential Revision: https://reviews.llvm.org/D43583

[MIPS GlobalISel] Adding GlobalISel

Add GlobalISel infrastructure up to the point where we can select a ret
void.

Patch by Petar Avramovic.

Differential Revision: https://reviews.llvm.org/D43583

llvm-svn: 325888

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