1 //===- MipsRegisterBankInfo.cpp ---------------------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// \file 10 /// This file implements the targeting of the RegisterBankInfo class for Mips. 11 /// \todo This should be generated by TableGen. 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsInstrInfo.h" 15 #include "MipsRegisterBankInfo.h" 16 #include "llvm/CodeGen/MachineRegisterInfo.h" 17 18 #define GET_TARGET_REGBANK_IMPL 19 20 #define DEBUG_TYPE "registerbankinfo" 21 22 #include "MipsGenRegisterBank.inc" 23 24 namespace llvm { 25 namespace Mips { 26 enum PartialMappingIdx { 27 PMI_GPR, 28 PMI_Min = PMI_GPR, 29 }; 30 31 RegisterBankInfo::PartialMapping PartMappings[]{ 32 {0, 32, GPRBRegBank} 33 }; 34 35 enum ValueMappingIdx { InvalidIdx = 0, GPRIdx = 1 }; 36 37 RegisterBankInfo::ValueMapping ValueMappings[] = { 38 // invalid 39 {nullptr, 0}, 40 // 3 operands in GPRs 41 {&PartMappings[PMI_GPR - PMI_Min], 1}, 42 {&PartMappings[PMI_GPR - PMI_Min], 1}, 43 {&PartMappings[PMI_GPR - PMI_Min], 1}}; 44 45 } // end namespace Mips 46 } // end namespace llvm 47 48 using namespace llvm; 49 50 MipsRegisterBankInfo::MipsRegisterBankInfo(const TargetRegisterInfo &TRI) 51 : MipsGenRegisterBankInfo() {} 52 53 const RegisterBank &MipsRegisterBankInfo::getRegBankFromRegClass( 54 const TargetRegisterClass &RC) const { 55 using namespace Mips; 56 57 switch (RC.getID()) { 58 case Mips::GPR32RegClassID: 59 case Mips::CPU16Regs_and_GPRMM16ZeroRegClassID: 60 case Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID: 61 case Mips::SP32RegClassID: 62 return getRegBank(Mips::GPRBRegBankID); 63 default: 64 llvm_unreachable("Register class not supported"); 65 } 66 } 67 68 const RegisterBankInfo::InstructionMapping & 69 MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { 70 71 unsigned Opc = MI.getOpcode(); 72 73 const RegisterBankInfo::InstructionMapping &Mapping = getInstrMappingImpl(MI); 74 if (Mapping.isValid()) 75 return Mapping; 76 77 using namespace TargetOpcode; 78 79 unsigned NumOperands = MI.getNumOperands(); 80 const ValueMapping *OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx]; 81 82 switch (Opc) { 83 case G_ADD: 84 case G_LOAD: 85 case G_STORE: 86 case G_GEP: 87 case G_AND: 88 case G_OR: 89 case G_XOR: 90 case G_SHL: 91 case G_ASHR: 92 case G_LSHR: 93 OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx]; 94 break; 95 case G_CONSTANT: 96 case G_FRAME_INDEX: 97 case G_GLOBAL_VALUE: 98 OperandsMapping = 99 getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr}); 100 break; 101 case G_ICMP: 102 OperandsMapping = 103 getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr, 104 &Mips::ValueMappings[Mips::GPRIdx], 105 &Mips::ValueMappings[Mips::GPRIdx]}); 106 break; 107 default: 108 return getInvalidInstructionMapping(); 109 } 110 111 return getInstructionMapping(DefaultMappingID, /*Cost=*/1, OperandsMapping, 112 NumOperands); 113 } 114