1 //===- MipsRegisterBankInfo.cpp ---------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements the targeting of the RegisterBankInfo class for Mips. 10 /// \todo This should be generated by TableGen. 11 //===----------------------------------------------------------------------===// 12 13 #include "MipsInstrInfo.h" 14 #include "MipsRegisterBankInfo.h" 15 #include "llvm/CodeGen/MachineRegisterInfo.h" 16 17 #define GET_TARGET_REGBANK_IMPL 18 19 #define DEBUG_TYPE "registerbankinfo" 20 21 #include "MipsGenRegisterBank.inc" 22 23 namespace llvm { 24 namespace Mips { 25 enum PartialMappingIdx { 26 PMI_GPR, 27 PMI_Min = PMI_GPR, 28 }; 29 30 RegisterBankInfo::PartialMapping PartMappings[]{ 31 {0, 32, GPRBRegBank} 32 }; 33 34 enum ValueMappingIdx { InvalidIdx = 0, GPRIdx = 1 }; 35 36 RegisterBankInfo::ValueMapping ValueMappings[] = { 37 // invalid 38 {nullptr, 0}, 39 // 3 operands in GPRs 40 {&PartMappings[PMI_GPR - PMI_Min], 1}, 41 {&PartMappings[PMI_GPR - PMI_Min], 1}, 42 {&PartMappings[PMI_GPR - PMI_Min], 1}}; 43 44 } // end namespace Mips 45 } // end namespace llvm 46 47 using namespace llvm; 48 49 MipsRegisterBankInfo::MipsRegisterBankInfo(const TargetRegisterInfo &TRI) 50 : MipsGenRegisterBankInfo() {} 51 52 const RegisterBank &MipsRegisterBankInfo::getRegBankFromRegClass( 53 const TargetRegisterClass &RC) const { 54 using namespace Mips; 55 56 switch (RC.getID()) { 57 case Mips::GPR32RegClassID: 58 case Mips::CPU16Regs_and_GPRMM16ZeroRegClassID: 59 case Mips::GPRMM16MovePPairFirstRegClassID: 60 case Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID: 61 case Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID: 62 case Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID: 63 case Mips::SP32RegClassID: 64 return getRegBank(Mips::GPRBRegBankID); 65 case Mips::FGRCCRegClassID: 66 case Mips::FGR64RegClassID: 67 case Mips::AFGR64RegClassID: 68 case Mips::AFGR64_and_OddSPRegClassID: 69 return getRegBank(Mips::FPRBRegBankID); 70 default: 71 llvm_unreachable("Register class not supported"); 72 } 73 } 74 75 const RegisterBankInfo::InstructionMapping & 76 MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { 77 78 unsigned Opc = MI.getOpcode(); 79 80 const RegisterBankInfo::InstructionMapping &Mapping = getInstrMappingImpl(MI); 81 if (Mapping.isValid()) 82 return Mapping; 83 84 using namespace TargetOpcode; 85 86 unsigned NumOperands = MI.getNumOperands(); 87 const ValueMapping *OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx]; 88 89 switch (Opc) { 90 case G_TRUNC: 91 case G_ADD: 92 case G_SUB: 93 case G_MUL: 94 case G_UMULH: 95 case G_LOAD: 96 case G_STORE: 97 case G_ZEXTLOAD: 98 case G_SEXTLOAD: 99 case G_GEP: 100 case G_AND: 101 case G_OR: 102 case G_XOR: 103 case G_SHL: 104 case G_ASHR: 105 case G_LSHR: 106 case G_SDIV: 107 case G_UDIV: 108 case G_SREM: 109 case G_UREM: 110 OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx]; 111 break; 112 case G_CONSTANT: 113 case G_FRAME_INDEX: 114 case G_GLOBAL_VALUE: 115 case G_BRCOND: 116 OperandsMapping = 117 getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr}); 118 break; 119 case G_ICMP: 120 OperandsMapping = 121 getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr, 122 &Mips::ValueMappings[Mips::GPRIdx], 123 &Mips::ValueMappings[Mips::GPRIdx]}); 124 break; 125 case G_SELECT: 126 OperandsMapping = 127 getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], 128 &Mips::ValueMappings[Mips::GPRIdx], 129 &Mips::ValueMappings[Mips::GPRIdx], 130 &Mips::ValueMappings[Mips::GPRIdx]}); 131 break; 132 default: 133 return getInvalidInstructionMapping(); 134 } 135 136 return getInstructionMapping(DefaultMappingID, /*Cost=*/1, OperandsMapping, 137 NumOperands); 138 } 139