1 //===- MipsRegisterBankInfo.cpp ---------------------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// \file 10 /// This file implements the targeting of the RegisterBankInfo class for Mips. 11 /// \todo This should be generated by TableGen. 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsInstrInfo.h" 15 #include "MipsRegisterBankInfo.h" 16 #include "llvm/CodeGen/GlobalISel/RegisterBank.h" 17 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 18 #include "llvm/CodeGen/MachineRegisterInfo.h" 19 #include "llvm/CodeGen/TargetRegisterInfo.h" 20 21 #define GET_TARGET_REGBANK_IMPL 22 23 #define DEBUG_TYPE "registerbankinfo" 24 25 #include "MipsGenRegisterBank.inc" 26 27 namespace llvm { 28 namespace Mips { 29 enum PartialMappingIdx { 30 PMI_GPR, 31 PMI_Min = PMI_GPR, 32 }; 33 34 RegisterBankInfo::PartialMapping PartMappings[]{ 35 {0, 32, GPRBRegBank} 36 }; 37 38 enum ValueMappingIdx { InvalidIdx = 0, GPRIdx = 1 }; 39 40 RegisterBankInfo::ValueMapping ValueMappings[] = { 41 // invalid 42 {nullptr, 0}, 43 // 3 operands in GPRs 44 {&PartMappings[PMI_GPR - PMI_Min], 1}, 45 {&PartMappings[PMI_GPR - PMI_Min], 1}, 46 {&PartMappings[PMI_GPR - PMI_Min], 1}}; 47 48 } // end namespace Mips 49 } // end namespace llvm 50 51 using namespace llvm; 52 53 MipsRegisterBankInfo::MipsRegisterBankInfo(const TargetRegisterInfo &TRI) 54 : MipsGenRegisterBankInfo() {} 55 56 const RegisterBank &MipsRegisterBankInfo::getRegBankFromRegClass( 57 const TargetRegisterClass &RC) const { 58 using namespace Mips; 59 60 switch (RC.getID()) { 61 case Mips::GPR32RegClassID: 62 case Mips::CPU16Regs_and_GPRMM16ZeroRegClassID: 63 case Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID: 64 return getRegBank(Mips::GPRBRegBankID); 65 default: 66 llvm_unreachable("Register class not supported"); 67 } 68 } 69 70 const RegisterBankInfo::InstructionMapping & 71 MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { 72 73 unsigned Opc = MI.getOpcode(); 74 75 const RegisterBankInfo::InstructionMapping &Mapping = getInstrMappingImpl(MI); 76 if (Mapping.isValid()) 77 return Mapping; 78 79 using namespace TargetOpcode; 80 81 unsigned NumOperands = MI.getNumOperands(); 82 const ValueMapping *OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx]; 83 84 switch (Opc) { 85 case G_ADD: 86 OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx]; 87 break; 88 default: 89 return getInvalidInstructionMapping(); 90 } 91 92 return getInstructionMapping(DefaultMappingID, /*Cost=*/1, OperandsMapping, 93 NumOperands); 94 } 95