Thumb2 assembly parsing and encoding for LDRD(immediate).

Refactor operand handling for STRD as well. Tests for that forthcoming.

llvm-svn: 139322

Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions.

llvm-svn: 139268

Create Thumb2 versions of STC/LDC, and reenable the relevant tests.

llvm-svn: 139256

Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.

llvm-svn: 139250

Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.

llvm-svn: 139240

Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson.

llvm-svn: 139237

Merge the ARM disassembler header into the implementation file, since it is not externally exposed.

llvm-svn: 138982

Fix 80 columns violations.

llvm-svn: 138980

Fix up r137380 based on post-commit review by Jim Grosbach.

llvm-svn: 138948

The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instruc

The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps.

llvm-svn: 138910

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Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing.

llvm-svn: 138840

Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.

llvm-svn: 138675

Spelling fail.

llvm-svn: 138667

invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immedia

invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.

llvm-svn: 138653

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Update for feedback from Jim.

llvm-svn: 138642

ARMDisassembler: Always return a size, even when disassembling fails.

This should fix PR10772.

llvm-svn: 138636

Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.

llvm

Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.

llvm-svn: 138635

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Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors.
This is the last disassembly crash detected by exhaustive Thumb2 instruction s

Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors.
This is the last disassembly crash detected by exhaustive Thumb2 instruction space. Major thanks to Chandler Carruth for making this kind of exhaustive testing possible.

llvm-svn: 138625

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Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.

llvm-svn: 138575

Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space.

llvm-svn: 138507

Be careful not to walk off the end of the operand info list while updating VFP predicates.

llvm-svn: 138492

Move TargetRegistry and TargetSelect from Target to Support where they belong.
These are strictly utilities for registering targets and components.

llvm-svn: 138450

Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate.

llvm-svn: 138443

Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.

llvm-svn: 138341

Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions.

llvm-svn: 138339