1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARM.h" 13 #include "ARMRegisterInfo.h" 14 #include "MCTargetDesc/ARMAddressingModes.h" 15 #include "MCTargetDesc/ARMBaseInfo.h" 16 #include "llvm/MC/EDInstInfo.h" 17 #include "llvm/MC/MCInst.h" 18 #include "llvm/MC/MCExpr.h" 19 #include "llvm/MC/MCContext.h" 20 #include "llvm/MC/MCDisassembler.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/MemoryObject.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/TargetRegistry.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 using namespace llvm; 28 29 typedef MCDisassembler::DecodeStatus DecodeStatus; 30 31 namespace { 32 /// ARMDisassembler - ARM disassembler for all ARM platforms. 33 class ARMDisassembler : public MCDisassembler { 34 public: 35 /// Constructor - Initializes the disassembler. 36 /// 37 ARMDisassembler() : 38 MCDisassembler() { 39 } 40 41 ~ARMDisassembler() { 42 } 43 44 /// getInstruction - See MCDisassembler. 45 DecodeStatus getInstruction(MCInst &instr, 46 uint64_t &size, 47 const MemoryObject ®ion, 48 uint64_t address, 49 raw_ostream &vStream) const; 50 51 /// getEDInfo - See MCDisassembler. 52 EDInstInfo *getEDInfo() const; 53 private: 54 }; 55 56 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 57 class ThumbDisassembler : public MCDisassembler { 58 public: 59 /// Constructor - Initializes the disassembler. 60 /// 61 ThumbDisassembler() : 62 MCDisassembler() { 63 } 64 65 ~ThumbDisassembler() { 66 } 67 68 /// getInstruction - See MCDisassembler. 69 DecodeStatus getInstruction(MCInst &instr, 70 uint64_t &size, 71 const MemoryObject ®ion, 72 uint64_t address, 73 raw_ostream &vStream) const; 74 75 /// getEDInfo - See MCDisassembler. 76 EDInstInfo *getEDInfo() const; 77 private: 78 mutable std::vector<unsigned> ITBlock; 79 void AddThumbPredicate(MCInst&) const; 80 void UpdateThumbVFPPredicate(MCInst&) const; 81 }; 82 } 83 84 static bool Check(DecodeStatus &Out, DecodeStatus In) { 85 switch (In) { 86 case MCDisassembler::Success: 87 // Out stays the same. 88 return true; 89 case MCDisassembler::SoftFail: 90 Out = In; 91 return true; 92 case MCDisassembler::Fail: 93 Out = In; 94 return false; 95 } 96 return false; 97 } 98 99 // Forward declare these because the autogenerated code will reference them. 100 // Definitions are further down. 101 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 102 uint64_t Address, const void *Decoder); 103 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 104 unsigned RegNo, uint64_t Address, 105 const void *Decoder); 106 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 107 uint64_t Address, const void *Decoder); 108 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 109 uint64_t Address, const void *Decoder); 110 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 111 uint64_t Address, const void *Decoder); 112 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 113 uint64_t Address, const void *Decoder); 114 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 115 uint64_t Address, const void *Decoder); 116 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 117 uint64_t Address, const void *Decoder); 118 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 119 unsigned RegNo, 120 uint64_t Address, 121 const void *Decoder); 122 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 123 uint64_t Address, const void *Decoder); 124 125 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 126 uint64_t Address, const void *Decoder); 127 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 128 uint64_t Address, const void *Decoder); 129 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 130 uint64_t Address, const void *Decoder); 131 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 132 uint64_t Address, const void *Decoder); 133 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 134 uint64_t Address, const void *Decoder); 135 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 136 uint64_t Address, const void *Decoder); 137 138 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 139 uint64_t Address, const void *Decoder); 140 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 141 uint64_t Address, const void *Decoder); 142 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 143 unsigned Insn, 144 uint64_t Address, 145 const void *Decoder); 146 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 147 uint64_t Address, const void *Decoder); 148 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 149 uint64_t Address, const void *Decoder); 150 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 151 uint64_t Address, const void *Decoder); 152 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 153 uint64_t Address, const void *Decoder); 154 155 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 156 unsigned Insn, 157 uint64_t Adddress, 158 const void *Decoder); 159 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 160 uint64_t Address, const void *Decoder); 161 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 162 uint64_t Address, const void *Decoder); 163 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 164 uint64_t Address, const void *Decoder); 165 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 166 uint64_t Address, const void *Decoder); 167 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 168 uint64_t Address, const void *Decoder); 169 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 170 uint64_t Address, const void *Decoder); 171 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 172 uint64_t Address, const void *Decoder); 173 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 174 uint64_t Address, const void *Decoder); 175 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 176 uint64_t Address, const void *Decoder); 177 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 186 uint64_t Address, const void *Decoder); 187 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 188 uint64_t Address, const void *Decoder); 189 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 190 uint64_t Address, const void *Decoder); 191 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 192 uint64_t Address, const void *Decoder); 193 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 194 uint64_t Address, const void *Decoder); 195 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 196 uint64_t Address, const void *Decoder); 197 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 198 uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 242 uint64_t Address, const void *Decoder); 243 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 244 uint64_t Address, const void *Decoder); 245 246 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val, 293 uint64_t Address, const void *Decoder); 294 295 #include "ARMGenDisassemblerTables.inc" 296 #include "ARMGenInstrInfo.inc" 297 #include "ARMGenEDInfo.inc" 298 299 static MCDisassembler *createARMDisassembler(const Target &T) { 300 return new ARMDisassembler; 301 } 302 303 static MCDisassembler *createThumbDisassembler(const Target &T) { 304 return new ThumbDisassembler; 305 } 306 307 EDInstInfo *ARMDisassembler::getEDInfo() const { 308 return instInfoARM; 309 } 310 311 EDInstInfo *ThumbDisassembler::getEDInfo() const { 312 return instInfoARM; 313 } 314 315 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 316 const MemoryObject &Region, 317 uint64_t Address, 318 raw_ostream &os) const { 319 uint8_t bytes[4]; 320 321 // We want to read exactly 4 bytes of data. 322 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 323 Size = 0; 324 return MCDisassembler::Fail; 325 } 326 327 // Encoded as a small-endian 32-bit word in the stream. 328 uint32_t insn = (bytes[3] << 24) | 329 (bytes[2] << 16) | 330 (bytes[1] << 8) | 331 (bytes[0] << 0); 332 333 // Calling the auto-generated decoder function. 334 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this); 335 if (result != MCDisassembler::Fail) { 336 Size = 4; 337 return result; 338 } 339 340 // Instructions that are shared between ARM and Thumb modes. 341 // FIXME: This shouldn't really exist. It's an artifact of the 342 // fact that we fail to encode a few instructions properly for Thumb. 343 MI.clear(); 344 result = decodeCommonInstruction32(MI, insn, Address, this); 345 if (result != MCDisassembler::Fail) { 346 Size = 4; 347 return result; 348 } 349 350 // VFP and NEON instructions, similarly, are shared between ARM 351 // and Thumb modes. 352 MI.clear(); 353 result = decodeVFPInstruction32(MI, insn, Address, this); 354 if (result != MCDisassembler::Fail) { 355 Size = 4; 356 return result; 357 } 358 359 MI.clear(); 360 result = decodeNEONDataInstruction32(MI, insn, Address, this); 361 if (result != MCDisassembler::Fail) { 362 Size = 4; 363 // Add a fake predicate operand, because we share these instruction 364 // definitions with Thumb2 where these instructions are predicable. 365 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 366 return MCDisassembler::Fail; 367 return result; 368 } 369 370 MI.clear(); 371 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); 372 if (result != MCDisassembler::Fail) { 373 Size = 4; 374 // Add a fake predicate operand, because we share these instruction 375 // definitions with Thumb2 where these instructions are predicable. 376 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 377 return MCDisassembler::Fail; 378 return result; 379 } 380 381 MI.clear(); 382 result = decodeNEONDupInstruction32(MI, insn, Address, this); 383 if (result != MCDisassembler::Fail) { 384 Size = 4; 385 // Add a fake predicate operand, because we share these instruction 386 // definitions with Thumb2 where these instructions are predicable. 387 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 388 return MCDisassembler::Fail; 389 return result; 390 } 391 392 MI.clear(); 393 394 Size = 0; 395 return MCDisassembler::Fail; 396 } 397 398 namespace llvm { 399 extern MCInstrDesc ARMInsts[]; 400 } 401 402 // Thumb1 instructions don't have explicit S bits. Rather, they 403 // implicitly set CPSR. Since it's not represented in the encoding, the 404 // auto-generated decoder won't inject the CPSR operand. We need to fix 405 // that as a post-pass. 406 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 407 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 408 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 409 MCInst::iterator I = MI.begin(); 410 for (unsigned i = 0; i < NumOps; ++i, ++I) { 411 if (I == MI.end()) break; 412 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 413 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 414 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 415 return; 416 } 417 } 418 419 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 420 } 421 422 // Most Thumb instructions don't have explicit predicates in the 423 // encoding, but rather get their predicates from IT context. We need 424 // to fix up the predicate operands using this context information as a 425 // post-pass. 426 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 427 // A few instructions actually have predicates encoded in them. Don't 428 // try to overwrite it if we're seeing one of those. 429 switch (MI.getOpcode()) { 430 case ARM::tBcc: 431 case ARM::t2Bcc: 432 return; 433 default: 434 break; 435 } 436 437 // If we're in an IT block, base the predicate on that. Otherwise, 438 // assume a predicate of AL. 439 unsigned CC; 440 if (!ITBlock.empty()) { 441 CC = ITBlock.back(); 442 if (CC == 0xF) 443 CC = ARMCC::AL; 444 ITBlock.pop_back(); 445 } else 446 CC = ARMCC::AL; 447 448 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 449 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 450 MCInst::iterator I = MI.begin(); 451 for (unsigned i = 0; i < NumOps; ++i, ++I) { 452 if (I == MI.end()) break; 453 if (OpInfo[i].isPredicate()) { 454 I = MI.insert(I, MCOperand::CreateImm(CC)); 455 ++I; 456 if (CC == ARMCC::AL) 457 MI.insert(I, MCOperand::CreateReg(0)); 458 else 459 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 460 return; 461 } 462 } 463 464 I = MI.insert(I, MCOperand::CreateImm(CC)); 465 ++I; 466 if (CC == ARMCC::AL) 467 MI.insert(I, MCOperand::CreateReg(0)); 468 else 469 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 470 } 471 472 // Thumb VFP instructions are a special case. Because we share their 473 // encodings between ARM and Thumb modes, and they are predicable in ARM 474 // mode, the auto-generated decoder will give them an (incorrect) 475 // predicate operand. We need to rewrite these operands based on the IT 476 // context as a post-pass. 477 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 478 unsigned CC; 479 if (!ITBlock.empty()) { 480 CC = ITBlock.back(); 481 ITBlock.pop_back(); 482 } else 483 CC = ARMCC::AL; 484 485 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 486 MCInst::iterator I = MI.begin(); 487 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 488 for (unsigned i = 0; i < NumOps; ++i, ++I) { 489 if (OpInfo[i].isPredicate() ) { 490 I->setImm(CC); 491 ++I; 492 if (CC == ARMCC::AL) 493 I->setReg(0); 494 else 495 I->setReg(ARM::CPSR); 496 return; 497 } 498 } 499 } 500 501 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 502 const MemoryObject &Region, 503 uint64_t Address, 504 raw_ostream &os) const { 505 uint8_t bytes[4]; 506 507 // We want to read exactly 2 bytes of data. 508 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 509 Size = 0; 510 return MCDisassembler::Fail; 511 } 512 513 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 514 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this); 515 if (result != MCDisassembler::Fail) { 516 Size = 2; 517 AddThumbPredicate(MI); 518 return result; 519 } 520 521 MI.clear(); 522 result = decodeThumbSBitInstruction16(MI, insn16, Address, this); 523 if (result) { 524 Size = 2; 525 bool InITBlock = !ITBlock.empty(); 526 AddThumbPredicate(MI); 527 AddThumb1SBit(MI, InITBlock); 528 return result; 529 } 530 531 MI.clear(); 532 result = decodeThumb2Instruction16(MI, insn16, Address, this); 533 if (result != MCDisassembler::Fail) { 534 Size = 2; 535 AddThumbPredicate(MI); 536 537 // If we find an IT instruction, we need to parse its condition 538 // code and mask operands so that we can apply them correctly 539 // to the subsequent instructions. 540 if (MI.getOpcode() == ARM::t2IT) { 541 // (3 - the number of trailing zeros) is the number of then / else. 542 unsigned firstcond = MI.getOperand(0).getImm(); 543 unsigned Mask = MI.getOperand(1).getImm(); 544 unsigned CondBit0 = Mask >> 4 & 1; 545 unsigned NumTZ = CountTrailingZeros_32(Mask); 546 assert(NumTZ <= 3 && "Invalid IT mask!"); 547 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 548 bool T = ((Mask >> Pos) & 1) == CondBit0; 549 if (T) 550 ITBlock.insert(ITBlock.begin(), firstcond); 551 else 552 ITBlock.insert(ITBlock.begin(), firstcond ^ 1); 553 } 554 555 ITBlock.push_back(firstcond); 556 } 557 558 return result; 559 } 560 561 // We want to read exactly 4 bytes of data. 562 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 563 Size = 0; 564 return MCDisassembler::Fail; 565 } 566 567 uint32_t insn32 = (bytes[3] << 8) | 568 (bytes[2] << 0) | 569 (bytes[1] << 24) | 570 (bytes[0] << 16); 571 MI.clear(); 572 result = decodeThumbInstruction32(MI, insn32, Address, this); 573 if (result != MCDisassembler::Fail) { 574 Size = 4; 575 bool InITBlock = ITBlock.size(); 576 AddThumbPredicate(MI); 577 AddThumb1SBit(MI, InITBlock); 578 return result; 579 } 580 581 MI.clear(); 582 result = decodeThumb2Instruction32(MI, insn32, Address, this); 583 if (result != MCDisassembler::Fail) { 584 Size = 4; 585 AddThumbPredicate(MI); 586 return result; 587 } 588 589 MI.clear(); 590 result = decodeCommonInstruction32(MI, insn32, Address, this); 591 if (result != MCDisassembler::Fail) { 592 Size = 4; 593 AddThumbPredicate(MI); 594 return result; 595 } 596 597 MI.clear(); 598 result = decodeVFPInstruction32(MI, insn32, Address, this); 599 if (result != MCDisassembler::Fail) { 600 Size = 4; 601 UpdateThumbVFPPredicate(MI); 602 return result; 603 } 604 605 MI.clear(); 606 result = decodeNEONDupInstruction32(MI, insn32, Address, this); 607 if (result != MCDisassembler::Fail) { 608 Size = 4; 609 AddThumbPredicate(MI); 610 return result; 611 } 612 613 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 614 MI.clear(); 615 uint32_t NEONLdStInsn = insn32; 616 NEONLdStInsn &= 0xF0FFFFFF; 617 NEONLdStInsn |= 0x04000000; 618 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this); 619 if (result != MCDisassembler::Fail) { 620 Size = 4; 621 AddThumbPredicate(MI); 622 return result; 623 } 624 } 625 626 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 627 MI.clear(); 628 uint32_t NEONDataInsn = insn32; 629 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 630 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 631 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 632 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this); 633 if (result != MCDisassembler::Fail) { 634 Size = 4; 635 AddThumbPredicate(MI); 636 return result; 637 } 638 } 639 640 Size = 0; 641 return MCDisassembler::Fail; 642 } 643 644 645 extern "C" void LLVMInitializeARMDisassembler() { 646 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 647 createARMDisassembler); 648 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 649 createThumbDisassembler); 650 } 651 652 static const unsigned GPRDecoderTable[] = { 653 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 654 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 655 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 656 ARM::R12, ARM::SP, ARM::LR, ARM::PC 657 }; 658 659 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 660 uint64_t Address, const void *Decoder) { 661 if (RegNo > 15) 662 return MCDisassembler::Fail; 663 664 unsigned Register = GPRDecoderTable[RegNo]; 665 Inst.addOperand(MCOperand::CreateReg(Register)); 666 return MCDisassembler::Success; 667 } 668 669 static DecodeStatus 670 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 671 uint64_t Address, const void *Decoder) { 672 if (RegNo == 15) return MCDisassembler::Fail; 673 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 674 } 675 676 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 677 uint64_t Address, const void *Decoder) { 678 if (RegNo > 7) 679 return MCDisassembler::Fail; 680 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 681 } 682 683 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 684 uint64_t Address, const void *Decoder) { 685 unsigned Register = 0; 686 switch (RegNo) { 687 case 0: 688 Register = ARM::R0; 689 break; 690 case 1: 691 Register = ARM::R1; 692 break; 693 case 2: 694 Register = ARM::R2; 695 break; 696 case 3: 697 Register = ARM::R3; 698 break; 699 case 9: 700 Register = ARM::R9; 701 break; 702 case 12: 703 Register = ARM::R12; 704 break; 705 default: 706 return MCDisassembler::Fail; 707 } 708 709 Inst.addOperand(MCOperand::CreateReg(Register)); 710 return MCDisassembler::Success; 711 } 712 713 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 714 uint64_t Address, const void *Decoder) { 715 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 716 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 717 } 718 719 static const unsigned SPRDecoderTable[] = { 720 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 721 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 722 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 723 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 724 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 725 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 726 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 727 ARM::S28, ARM::S29, ARM::S30, ARM::S31 728 }; 729 730 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 731 uint64_t Address, const void *Decoder) { 732 if (RegNo > 31) 733 return MCDisassembler::Fail; 734 735 unsigned Register = SPRDecoderTable[RegNo]; 736 Inst.addOperand(MCOperand::CreateReg(Register)); 737 return MCDisassembler::Success; 738 } 739 740 static const unsigned DPRDecoderTable[] = { 741 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 742 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 743 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 744 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 745 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 746 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 747 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 748 ARM::D28, ARM::D29, ARM::D30, ARM::D31 749 }; 750 751 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 752 uint64_t Address, const void *Decoder) { 753 if (RegNo > 31) 754 return MCDisassembler::Fail; 755 756 unsigned Register = DPRDecoderTable[RegNo]; 757 Inst.addOperand(MCOperand::CreateReg(Register)); 758 return MCDisassembler::Success; 759 } 760 761 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 762 uint64_t Address, const void *Decoder) { 763 if (RegNo > 7) 764 return MCDisassembler::Fail; 765 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 766 } 767 768 static DecodeStatus 769 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 770 uint64_t Address, const void *Decoder) { 771 if (RegNo > 15) 772 return MCDisassembler::Fail; 773 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 774 } 775 776 static const unsigned QPRDecoderTable[] = { 777 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 778 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 779 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 780 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 781 }; 782 783 784 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 785 uint64_t Address, const void *Decoder) { 786 if (RegNo > 31) 787 return MCDisassembler::Fail; 788 RegNo >>= 1; 789 790 unsigned Register = QPRDecoderTable[RegNo]; 791 Inst.addOperand(MCOperand::CreateReg(Register)); 792 return MCDisassembler::Success; 793 } 794 795 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 796 uint64_t Address, const void *Decoder) { 797 if (Val == 0xF) return MCDisassembler::Fail; 798 // AL predicate is not allowed on Thumb1 branches. 799 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 800 return MCDisassembler::Fail; 801 Inst.addOperand(MCOperand::CreateImm(Val)); 802 if (Val == ARMCC::AL) { 803 Inst.addOperand(MCOperand::CreateReg(0)); 804 } else 805 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 806 return MCDisassembler::Success; 807 } 808 809 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 810 uint64_t Address, const void *Decoder) { 811 if (Val) 812 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 813 else 814 Inst.addOperand(MCOperand::CreateReg(0)); 815 return MCDisassembler::Success; 816 } 817 818 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 819 uint64_t Address, const void *Decoder) { 820 uint32_t imm = Val & 0xFF; 821 uint32_t rot = (Val & 0xF00) >> 7; 822 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 823 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 824 return MCDisassembler::Success; 825 } 826 827 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 828 uint64_t Address, const void *Decoder) { 829 DecodeStatus S = MCDisassembler::Success; 830 831 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 832 unsigned type = fieldFromInstruction32(Val, 5, 2); 833 unsigned imm = fieldFromInstruction32(Val, 7, 5); 834 835 // Register-immediate 836 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 837 return MCDisassembler::Fail; 838 839 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 840 switch (type) { 841 case 0: 842 Shift = ARM_AM::lsl; 843 break; 844 case 1: 845 Shift = ARM_AM::lsr; 846 break; 847 case 2: 848 Shift = ARM_AM::asr; 849 break; 850 case 3: 851 Shift = ARM_AM::ror; 852 break; 853 } 854 855 if (Shift == ARM_AM::ror && imm == 0) 856 Shift = ARM_AM::rrx; 857 858 unsigned Op = Shift | (imm << 3); 859 Inst.addOperand(MCOperand::CreateImm(Op)); 860 861 return S; 862 } 863 864 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 865 uint64_t Address, const void *Decoder) { 866 DecodeStatus S = MCDisassembler::Success; 867 868 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 869 unsigned type = fieldFromInstruction32(Val, 5, 2); 870 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 871 872 // Register-register 873 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 874 return MCDisassembler::Fail; 875 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 876 return MCDisassembler::Fail; 877 878 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 879 switch (type) { 880 case 0: 881 Shift = ARM_AM::lsl; 882 break; 883 case 1: 884 Shift = ARM_AM::lsr; 885 break; 886 case 2: 887 Shift = ARM_AM::asr; 888 break; 889 case 3: 890 Shift = ARM_AM::ror; 891 break; 892 } 893 894 Inst.addOperand(MCOperand::CreateImm(Shift)); 895 896 return S; 897 } 898 899 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 900 uint64_t Address, const void *Decoder) { 901 DecodeStatus S = MCDisassembler::Success; 902 903 // Empty register lists are not allowed. 904 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 905 for (unsigned i = 0; i < 16; ++i) { 906 if (Val & (1 << i)) { 907 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 908 return MCDisassembler::Fail; 909 } 910 } 911 912 return S; 913 } 914 915 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 916 uint64_t Address, const void *Decoder) { 917 DecodeStatus S = MCDisassembler::Success; 918 919 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 920 unsigned regs = Val & 0xFF; 921 922 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 923 return MCDisassembler::Fail; 924 for (unsigned i = 0; i < (regs - 1); ++i) { 925 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 926 return MCDisassembler::Fail; 927 } 928 929 return S; 930 } 931 932 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 933 uint64_t Address, const void *Decoder) { 934 DecodeStatus S = MCDisassembler::Success; 935 936 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 937 unsigned regs = (Val & 0xFF) / 2; 938 939 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 940 return MCDisassembler::Fail; 941 for (unsigned i = 0; i < (regs - 1); ++i) { 942 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 943 return MCDisassembler::Fail; 944 } 945 946 return S; 947 } 948 949 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 950 uint64_t Address, const void *Decoder) { 951 // This operand encodes a mask of contiguous zeros between a specified MSB 952 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 953 // the mask of all bits LSB-and-lower, and then xor them to create 954 // the mask of that's all ones on [msb, lsb]. Finally we not it to 955 // create the final mask. 956 unsigned msb = fieldFromInstruction32(Val, 5, 5); 957 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 958 uint32_t msb_mask = (1 << (msb+1)) - 1; 959 uint32_t lsb_mask = (1 << lsb) - 1; 960 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 961 return MCDisassembler::Success; 962 } 963 964 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 965 uint64_t Address, const void *Decoder) { 966 DecodeStatus S = MCDisassembler::Success; 967 968 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 969 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 970 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 971 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 972 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 973 unsigned U = fieldFromInstruction32(Insn, 23, 1); 974 975 switch (Inst.getOpcode()) { 976 case ARM::LDC_OFFSET: 977 case ARM::LDC_PRE: 978 case ARM::LDC_POST: 979 case ARM::LDC_OPTION: 980 case ARM::LDCL_OFFSET: 981 case ARM::LDCL_PRE: 982 case ARM::LDCL_POST: 983 case ARM::LDCL_OPTION: 984 case ARM::STC_OFFSET: 985 case ARM::STC_PRE: 986 case ARM::STC_POST: 987 case ARM::STC_OPTION: 988 case ARM::STCL_OFFSET: 989 case ARM::STCL_PRE: 990 case ARM::STCL_POST: 991 case ARM::STCL_OPTION: 992 if (coproc == 0xA || coproc == 0xB) 993 return MCDisassembler::Fail; 994 break; 995 default: 996 break; 997 } 998 999 Inst.addOperand(MCOperand::CreateImm(coproc)); 1000 Inst.addOperand(MCOperand::CreateImm(CRd)); 1001 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1002 return MCDisassembler::Fail; 1003 switch (Inst.getOpcode()) { 1004 case ARM::LDC_OPTION: 1005 case ARM::LDCL_OPTION: 1006 case ARM::LDC2_OPTION: 1007 case ARM::LDC2L_OPTION: 1008 case ARM::STC_OPTION: 1009 case ARM::STCL_OPTION: 1010 case ARM::STC2_OPTION: 1011 case ARM::STC2L_OPTION: 1012 case ARM::LDCL_POST: 1013 case ARM::STCL_POST: 1014 case ARM::LDC2L_POST: 1015 case ARM::STC2L_POST: 1016 break; 1017 default: 1018 Inst.addOperand(MCOperand::CreateReg(0)); 1019 break; 1020 } 1021 1022 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1023 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1024 1025 bool writeback = (P == 0) || (W == 1); 1026 unsigned idx_mode = 0; 1027 if (P && writeback) 1028 idx_mode = ARMII::IndexModePre; 1029 else if (!P && writeback) 1030 idx_mode = ARMII::IndexModePost; 1031 1032 switch (Inst.getOpcode()) { 1033 case ARM::LDCL_POST: 1034 case ARM::STCL_POST: 1035 case ARM::LDC2L_POST: 1036 case ARM::STC2L_POST: 1037 imm |= U << 8; 1038 case ARM::LDC_OPTION: 1039 case ARM::LDCL_OPTION: 1040 case ARM::LDC2_OPTION: 1041 case ARM::LDC2L_OPTION: 1042 case ARM::STC_OPTION: 1043 case ARM::STCL_OPTION: 1044 case ARM::STC2_OPTION: 1045 case ARM::STC2L_OPTION: 1046 Inst.addOperand(MCOperand::CreateImm(imm)); 1047 break; 1048 default: 1049 if (U) 1050 Inst.addOperand(MCOperand::CreateImm( 1051 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 1052 else 1053 Inst.addOperand(MCOperand::CreateImm( 1054 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 1055 break; 1056 } 1057 1058 switch (Inst.getOpcode()) { 1059 case ARM::LDC_OFFSET: 1060 case ARM::LDC_PRE: 1061 case ARM::LDC_POST: 1062 case ARM::LDC_OPTION: 1063 case ARM::LDCL_OFFSET: 1064 case ARM::LDCL_PRE: 1065 case ARM::LDCL_POST: 1066 case ARM::LDCL_OPTION: 1067 case ARM::STC_OFFSET: 1068 case ARM::STC_PRE: 1069 case ARM::STC_POST: 1070 case ARM::STC_OPTION: 1071 case ARM::STCL_OFFSET: 1072 case ARM::STCL_PRE: 1073 case ARM::STCL_POST: 1074 case ARM::STCL_OPTION: 1075 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1076 return MCDisassembler::Fail; 1077 break; 1078 default: 1079 break; 1080 } 1081 1082 return S; 1083 } 1084 1085 static DecodeStatus 1086 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 1087 uint64_t Address, const void *Decoder) { 1088 DecodeStatus S = MCDisassembler::Success; 1089 1090 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1091 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1092 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1093 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1094 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1095 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1096 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1097 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1098 1099 // On stores, the writeback operand precedes Rt. 1100 switch (Inst.getOpcode()) { 1101 case ARM::STR_POST_IMM: 1102 case ARM::STR_POST_REG: 1103 case ARM::STRB_POST_IMM: 1104 case ARM::STRB_POST_REG: 1105 case ARM::STRT_POST_REG: 1106 case ARM::STRT_POST_IMM: 1107 case ARM::STRBT_POST_REG: 1108 case ARM::STRBT_POST_IMM: 1109 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1110 return MCDisassembler::Fail; 1111 break; 1112 default: 1113 break; 1114 } 1115 1116 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1117 return MCDisassembler::Fail; 1118 1119 // On loads, the writeback operand comes after Rt. 1120 switch (Inst.getOpcode()) { 1121 case ARM::LDR_POST_IMM: 1122 case ARM::LDR_POST_REG: 1123 case ARM::LDRB_POST_IMM: 1124 case ARM::LDRB_POST_REG: 1125 case ARM::LDRBT_POST_REG: 1126 case ARM::LDRBT_POST_IMM: 1127 case ARM::LDRT_POST_REG: 1128 case ARM::LDRT_POST_IMM: 1129 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1130 return MCDisassembler::Fail; 1131 break; 1132 default: 1133 break; 1134 } 1135 1136 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1137 return MCDisassembler::Fail; 1138 1139 ARM_AM::AddrOpc Op = ARM_AM::add; 1140 if (!fieldFromInstruction32(Insn, 23, 1)) 1141 Op = ARM_AM::sub; 1142 1143 bool writeback = (P == 0) || (W == 1); 1144 unsigned idx_mode = 0; 1145 if (P && writeback) 1146 idx_mode = ARMII::IndexModePre; 1147 else if (!P && writeback) 1148 idx_mode = ARMII::IndexModePost; 1149 1150 if (writeback && (Rn == 15 || Rn == Rt)) 1151 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1152 1153 if (reg) { 1154 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1155 return MCDisassembler::Fail; 1156 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1157 switch( fieldFromInstruction32(Insn, 5, 2)) { 1158 case 0: 1159 Opc = ARM_AM::lsl; 1160 break; 1161 case 1: 1162 Opc = ARM_AM::lsr; 1163 break; 1164 case 2: 1165 Opc = ARM_AM::asr; 1166 break; 1167 case 3: 1168 Opc = ARM_AM::ror; 1169 break; 1170 default: 1171 return MCDisassembler::Fail; 1172 } 1173 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1174 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1175 1176 Inst.addOperand(MCOperand::CreateImm(imm)); 1177 } else { 1178 Inst.addOperand(MCOperand::CreateReg(0)); 1179 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1180 Inst.addOperand(MCOperand::CreateImm(tmp)); 1181 } 1182 1183 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1184 return MCDisassembler::Fail; 1185 1186 return S; 1187 } 1188 1189 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1190 uint64_t Address, const void *Decoder) { 1191 DecodeStatus S = MCDisassembler::Success; 1192 1193 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1194 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1195 unsigned type = fieldFromInstruction32(Val, 5, 2); 1196 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1197 unsigned U = fieldFromInstruction32(Val, 12, 1); 1198 1199 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1200 switch (type) { 1201 case 0: 1202 ShOp = ARM_AM::lsl; 1203 break; 1204 case 1: 1205 ShOp = ARM_AM::lsr; 1206 break; 1207 case 2: 1208 ShOp = ARM_AM::asr; 1209 break; 1210 case 3: 1211 ShOp = ARM_AM::ror; 1212 break; 1213 } 1214 1215 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1216 return MCDisassembler::Fail; 1217 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1218 return MCDisassembler::Fail; 1219 unsigned shift; 1220 if (U) 1221 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1222 else 1223 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1224 Inst.addOperand(MCOperand::CreateImm(shift)); 1225 1226 return S; 1227 } 1228 1229 static DecodeStatus 1230 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1231 uint64_t Address, const void *Decoder) { 1232 DecodeStatus S = MCDisassembler::Success; 1233 1234 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1235 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1236 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1237 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1238 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1239 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1240 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1241 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1242 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1243 1244 bool writeback = (W == 1) | (P == 0); 1245 1246 // For {LD,ST}RD, Rt must be even, else undefined. 1247 switch (Inst.getOpcode()) { 1248 case ARM::STRD: 1249 case ARM::STRD_PRE: 1250 case ARM::STRD_POST: 1251 case ARM::LDRD: 1252 case ARM::LDRD_PRE: 1253 case ARM::LDRD_POST: 1254 if (Rt & 0x1) return MCDisassembler::Fail; 1255 break; 1256 default: 1257 break; 1258 } 1259 1260 if (writeback) { // Writeback 1261 if (P) 1262 U |= ARMII::IndexModePre << 9; 1263 else 1264 U |= ARMII::IndexModePost << 9; 1265 1266 // On stores, the writeback operand precedes Rt. 1267 switch (Inst.getOpcode()) { 1268 case ARM::STRD: 1269 case ARM::STRD_PRE: 1270 case ARM::STRD_POST: 1271 case ARM::STRH: 1272 case ARM::STRH_PRE: 1273 case ARM::STRH_POST: 1274 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1275 return MCDisassembler::Fail; 1276 break; 1277 default: 1278 break; 1279 } 1280 } 1281 1282 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1283 return MCDisassembler::Fail; 1284 switch (Inst.getOpcode()) { 1285 case ARM::STRD: 1286 case ARM::STRD_PRE: 1287 case ARM::STRD_POST: 1288 case ARM::LDRD: 1289 case ARM::LDRD_PRE: 1290 case ARM::LDRD_POST: 1291 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1292 return MCDisassembler::Fail; 1293 break; 1294 default: 1295 break; 1296 } 1297 1298 if (writeback) { 1299 // On loads, the writeback operand comes after Rt. 1300 switch (Inst.getOpcode()) { 1301 case ARM::LDRD: 1302 case ARM::LDRD_PRE: 1303 case ARM::LDRD_POST: 1304 case ARM::LDRH: 1305 case ARM::LDRH_PRE: 1306 case ARM::LDRH_POST: 1307 case ARM::LDRSH: 1308 case ARM::LDRSH_PRE: 1309 case ARM::LDRSH_POST: 1310 case ARM::LDRSB: 1311 case ARM::LDRSB_PRE: 1312 case ARM::LDRSB_POST: 1313 case ARM::LDRHTr: 1314 case ARM::LDRSBTr: 1315 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1316 return MCDisassembler::Fail; 1317 break; 1318 default: 1319 break; 1320 } 1321 } 1322 1323 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1324 return MCDisassembler::Fail; 1325 1326 if (type) { 1327 Inst.addOperand(MCOperand::CreateReg(0)); 1328 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1329 } else { 1330 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1331 return MCDisassembler::Fail; 1332 Inst.addOperand(MCOperand::CreateImm(U)); 1333 } 1334 1335 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1336 return MCDisassembler::Fail; 1337 1338 return S; 1339 } 1340 1341 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1342 uint64_t Address, const void *Decoder) { 1343 DecodeStatus S = MCDisassembler::Success; 1344 1345 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1346 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1347 1348 switch (mode) { 1349 case 0: 1350 mode = ARM_AM::da; 1351 break; 1352 case 1: 1353 mode = ARM_AM::ia; 1354 break; 1355 case 2: 1356 mode = ARM_AM::db; 1357 break; 1358 case 3: 1359 mode = ARM_AM::ib; 1360 break; 1361 } 1362 1363 Inst.addOperand(MCOperand::CreateImm(mode)); 1364 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1365 return MCDisassembler::Fail; 1366 1367 return S; 1368 } 1369 1370 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1371 unsigned Insn, 1372 uint64_t Address, const void *Decoder) { 1373 DecodeStatus S = MCDisassembler::Success; 1374 1375 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1376 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1377 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1378 1379 if (pred == 0xF) { 1380 switch (Inst.getOpcode()) { 1381 case ARM::LDMDA: 1382 Inst.setOpcode(ARM::RFEDA); 1383 break; 1384 case ARM::LDMDA_UPD: 1385 Inst.setOpcode(ARM::RFEDA_UPD); 1386 break; 1387 case ARM::LDMDB: 1388 Inst.setOpcode(ARM::RFEDB); 1389 break; 1390 case ARM::LDMDB_UPD: 1391 Inst.setOpcode(ARM::RFEDB_UPD); 1392 break; 1393 case ARM::LDMIA: 1394 Inst.setOpcode(ARM::RFEIA); 1395 break; 1396 case ARM::LDMIA_UPD: 1397 Inst.setOpcode(ARM::RFEIA_UPD); 1398 break; 1399 case ARM::LDMIB: 1400 Inst.setOpcode(ARM::RFEIB); 1401 break; 1402 case ARM::LDMIB_UPD: 1403 Inst.setOpcode(ARM::RFEIB_UPD); 1404 break; 1405 case ARM::STMDA: 1406 Inst.setOpcode(ARM::SRSDA); 1407 break; 1408 case ARM::STMDA_UPD: 1409 Inst.setOpcode(ARM::SRSDA_UPD); 1410 break; 1411 case ARM::STMDB: 1412 Inst.setOpcode(ARM::SRSDB); 1413 break; 1414 case ARM::STMDB_UPD: 1415 Inst.setOpcode(ARM::SRSDB_UPD); 1416 break; 1417 case ARM::STMIA: 1418 Inst.setOpcode(ARM::SRSIA); 1419 break; 1420 case ARM::STMIA_UPD: 1421 Inst.setOpcode(ARM::SRSIA_UPD); 1422 break; 1423 case ARM::STMIB: 1424 Inst.setOpcode(ARM::SRSIB); 1425 break; 1426 case ARM::STMIB_UPD: 1427 Inst.setOpcode(ARM::SRSIB_UPD); 1428 break; 1429 default: 1430 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1431 } 1432 1433 // For stores (which become SRS's, the only operand is the mode. 1434 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1435 Inst.addOperand( 1436 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1437 return S; 1438 } 1439 1440 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1441 } 1442 1443 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1444 return MCDisassembler::Fail; 1445 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1446 return MCDisassembler::Fail; // Tied 1447 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1448 return MCDisassembler::Fail; 1449 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1450 return MCDisassembler::Fail; 1451 1452 return S; 1453 } 1454 1455 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1456 uint64_t Address, const void *Decoder) { 1457 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1458 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1459 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1460 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1461 1462 DecodeStatus S = MCDisassembler::Success; 1463 1464 // imod == '01' --> UNPREDICTABLE 1465 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1466 // return failure here. The '01' imod value is unprintable, so there's 1467 // nothing useful we could do even if we returned UNPREDICTABLE. 1468 1469 if (imod == 1) return MCDisassembler::Fail; 1470 1471 if (imod && M) { 1472 Inst.setOpcode(ARM::CPS3p); 1473 Inst.addOperand(MCOperand::CreateImm(imod)); 1474 Inst.addOperand(MCOperand::CreateImm(iflags)); 1475 Inst.addOperand(MCOperand::CreateImm(mode)); 1476 } else if (imod && !M) { 1477 Inst.setOpcode(ARM::CPS2p); 1478 Inst.addOperand(MCOperand::CreateImm(imod)); 1479 Inst.addOperand(MCOperand::CreateImm(iflags)); 1480 if (mode) S = MCDisassembler::SoftFail; 1481 } else if (!imod && M) { 1482 Inst.setOpcode(ARM::CPS1p); 1483 Inst.addOperand(MCOperand::CreateImm(mode)); 1484 if (iflags) S = MCDisassembler::SoftFail; 1485 } else { 1486 // imod == '00' && M == '0' --> UNPREDICTABLE 1487 Inst.setOpcode(ARM::CPS1p); 1488 Inst.addOperand(MCOperand::CreateImm(mode)); 1489 S = MCDisassembler::SoftFail; 1490 } 1491 1492 return S; 1493 } 1494 1495 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1496 uint64_t Address, const void *Decoder) { 1497 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1498 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1499 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1500 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1501 1502 DecodeStatus S = MCDisassembler::Success; 1503 1504 // imod == '01' --> UNPREDICTABLE 1505 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1506 // return failure here. The '01' imod value is unprintable, so there's 1507 // nothing useful we could do even if we returned UNPREDICTABLE. 1508 1509 if (imod == 1) return MCDisassembler::Fail; 1510 1511 if (imod && M) { 1512 Inst.setOpcode(ARM::t2CPS3p); 1513 Inst.addOperand(MCOperand::CreateImm(imod)); 1514 Inst.addOperand(MCOperand::CreateImm(iflags)); 1515 Inst.addOperand(MCOperand::CreateImm(mode)); 1516 } else if (imod && !M) { 1517 Inst.setOpcode(ARM::t2CPS2p); 1518 Inst.addOperand(MCOperand::CreateImm(imod)); 1519 Inst.addOperand(MCOperand::CreateImm(iflags)); 1520 if (mode) S = MCDisassembler::SoftFail; 1521 } else if (!imod && M) { 1522 Inst.setOpcode(ARM::t2CPS1p); 1523 Inst.addOperand(MCOperand::CreateImm(mode)); 1524 if (iflags) S = MCDisassembler::SoftFail; 1525 } else { 1526 // imod == '00' && M == '0' --> UNPREDICTABLE 1527 Inst.setOpcode(ARM::t2CPS1p); 1528 Inst.addOperand(MCOperand::CreateImm(mode)); 1529 S = MCDisassembler::SoftFail; 1530 } 1531 1532 return S; 1533 } 1534 1535 1536 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1537 uint64_t Address, const void *Decoder) { 1538 DecodeStatus S = MCDisassembler::Success; 1539 1540 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1541 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1542 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1543 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1544 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1545 1546 if (pred == 0xF) 1547 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1548 1549 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1550 return MCDisassembler::Fail; 1551 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1552 return MCDisassembler::Fail; 1553 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1554 return MCDisassembler::Fail; 1555 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1556 return MCDisassembler::Fail; 1557 1558 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1559 return MCDisassembler::Fail; 1560 1561 return S; 1562 } 1563 1564 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1565 uint64_t Address, const void *Decoder) { 1566 DecodeStatus S = MCDisassembler::Success; 1567 1568 unsigned add = fieldFromInstruction32(Val, 12, 1); 1569 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1570 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1571 1572 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1573 return MCDisassembler::Fail; 1574 1575 if (!add) imm *= -1; 1576 if (imm == 0 && !add) imm = INT32_MIN; 1577 Inst.addOperand(MCOperand::CreateImm(imm)); 1578 1579 return S; 1580 } 1581 1582 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1583 uint64_t Address, const void *Decoder) { 1584 DecodeStatus S = MCDisassembler::Success; 1585 1586 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1587 unsigned U = fieldFromInstruction32(Val, 8, 1); 1588 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1589 1590 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1591 return MCDisassembler::Fail; 1592 1593 if (U) 1594 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1595 else 1596 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1597 1598 return S; 1599 } 1600 1601 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1602 uint64_t Address, const void *Decoder) { 1603 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1604 } 1605 1606 static DecodeStatus 1607 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1608 uint64_t Address, const void *Decoder) { 1609 DecodeStatus S = MCDisassembler::Success; 1610 1611 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1612 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1613 1614 if (pred == 0xF) { 1615 Inst.setOpcode(ARM::BLXi); 1616 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1617 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1618 return S; 1619 } 1620 1621 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1622 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1623 return MCDisassembler::Fail; 1624 1625 return S; 1626 } 1627 1628 1629 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1630 uint64_t Address, const void *Decoder) { 1631 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1632 return MCDisassembler::Success; 1633 } 1634 1635 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1636 uint64_t Address, const void *Decoder) { 1637 DecodeStatus S = MCDisassembler::Success; 1638 1639 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1640 unsigned align = fieldFromInstruction32(Val, 4, 2); 1641 1642 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1643 return MCDisassembler::Fail; 1644 if (!align) 1645 Inst.addOperand(MCOperand::CreateImm(0)); 1646 else 1647 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1648 1649 return S; 1650 } 1651 1652 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1653 uint64_t Address, const void *Decoder) { 1654 DecodeStatus S = MCDisassembler::Success; 1655 1656 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1657 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1658 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1659 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1660 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1661 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1662 1663 // First output register 1664 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 1665 return MCDisassembler::Fail; 1666 1667 // Second output register 1668 switch (Inst.getOpcode()) { 1669 case ARM::VLD1q8: 1670 case ARM::VLD1q16: 1671 case ARM::VLD1q32: 1672 case ARM::VLD1q64: 1673 case ARM::VLD1q8_UPD: 1674 case ARM::VLD1q16_UPD: 1675 case ARM::VLD1q32_UPD: 1676 case ARM::VLD1q64_UPD: 1677 case ARM::VLD1d8T: 1678 case ARM::VLD1d16T: 1679 case ARM::VLD1d32T: 1680 case ARM::VLD1d64T: 1681 case ARM::VLD1d8T_UPD: 1682 case ARM::VLD1d16T_UPD: 1683 case ARM::VLD1d32T_UPD: 1684 case ARM::VLD1d64T_UPD: 1685 case ARM::VLD1d8Q: 1686 case ARM::VLD1d16Q: 1687 case ARM::VLD1d32Q: 1688 case ARM::VLD1d64Q: 1689 case ARM::VLD1d8Q_UPD: 1690 case ARM::VLD1d16Q_UPD: 1691 case ARM::VLD1d32Q_UPD: 1692 case ARM::VLD1d64Q_UPD: 1693 case ARM::VLD2d8: 1694 case ARM::VLD2d16: 1695 case ARM::VLD2d32: 1696 case ARM::VLD2d8_UPD: 1697 case ARM::VLD2d16_UPD: 1698 case ARM::VLD2d32_UPD: 1699 case ARM::VLD2q8: 1700 case ARM::VLD2q16: 1701 case ARM::VLD2q32: 1702 case ARM::VLD2q8_UPD: 1703 case ARM::VLD2q16_UPD: 1704 case ARM::VLD2q32_UPD: 1705 case ARM::VLD3d8: 1706 case ARM::VLD3d16: 1707 case ARM::VLD3d32: 1708 case ARM::VLD3d8_UPD: 1709 case ARM::VLD3d16_UPD: 1710 case ARM::VLD3d32_UPD: 1711 case ARM::VLD4d8: 1712 case ARM::VLD4d16: 1713 case ARM::VLD4d32: 1714 case ARM::VLD4d8_UPD: 1715 case ARM::VLD4d16_UPD: 1716 case ARM::VLD4d32_UPD: 1717 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 1718 return MCDisassembler::Fail; 1719 break; 1720 case ARM::VLD2b8: 1721 case ARM::VLD2b16: 1722 case ARM::VLD2b32: 1723 case ARM::VLD2b8_UPD: 1724 case ARM::VLD2b16_UPD: 1725 case ARM::VLD2b32_UPD: 1726 case ARM::VLD3q8: 1727 case ARM::VLD3q16: 1728 case ARM::VLD3q32: 1729 case ARM::VLD3q8_UPD: 1730 case ARM::VLD3q16_UPD: 1731 case ARM::VLD3q32_UPD: 1732 case ARM::VLD4q8: 1733 case ARM::VLD4q16: 1734 case ARM::VLD4q32: 1735 case ARM::VLD4q8_UPD: 1736 case ARM::VLD4q16_UPD: 1737 case ARM::VLD4q32_UPD: 1738 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1739 return MCDisassembler::Fail; 1740 default: 1741 break; 1742 } 1743 1744 // Third output register 1745 switch(Inst.getOpcode()) { 1746 case ARM::VLD1d8T: 1747 case ARM::VLD1d16T: 1748 case ARM::VLD1d32T: 1749 case ARM::VLD1d64T: 1750 case ARM::VLD1d8T_UPD: 1751 case ARM::VLD1d16T_UPD: 1752 case ARM::VLD1d32T_UPD: 1753 case ARM::VLD1d64T_UPD: 1754 case ARM::VLD1d8Q: 1755 case ARM::VLD1d16Q: 1756 case ARM::VLD1d32Q: 1757 case ARM::VLD1d64Q: 1758 case ARM::VLD1d8Q_UPD: 1759 case ARM::VLD1d16Q_UPD: 1760 case ARM::VLD1d32Q_UPD: 1761 case ARM::VLD1d64Q_UPD: 1762 case ARM::VLD2q8: 1763 case ARM::VLD2q16: 1764 case ARM::VLD2q32: 1765 case ARM::VLD2q8_UPD: 1766 case ARM::VLD2q16_UPD: 1767 case ARM::VLD2q32_UPD: 1768 case ARM::VLD3d8: 1769 case ARM::VLD3d16: 1770 case ARM::VLD3d32: 1771 case ARM::VLD3d8_UPD: 1772 case ARM::VLD3d16_UPD: 1773 case ARM::VLD3d32_UPD: 1774 case ARM::VLD4d8: 1775 case ARM::VLD4d16: 1776 case ARM::VLD4d32: 1777 case ARM::VLD4d8_UPD: 1778 case ARM::VLD4d16_UPD: 1779 case ARM::VLD4d32_UPD: 1780 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1781 return MCDisassembler::Fail; 1782 break; 1783 case ARM::VLD3q8: 1784 case ARM::VLD3q16: 1785 case ARM::VLD3q32: 1786 case ARM::VLD3q8_UPD: 1787 case ARM::VLD3q16_UPD: 1788 case ARM::VLD3q32_UPD: 1789 case ARM::VLD4q8: 1790 case ARM::VLD4q16: 1791 case ARM::VLD4q32: 1792 case ARM::VLD4q8_UPD: 1793 case ARM::VLD4q16_UPD: 1794 case ARM::VLD4q32_UPD: 1795 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 1796 return MCDisassembler::Fail; 1797 break; 1798 default: 1799 break; 1800 } 1801 1802 // Fourth output register 1803 switch (Inst.getOpcode()) { 1804 case ARM::VLD1d8Q: 1805 case ARM::VLD1d16Q: 1806 case ARM::VLD1d32Q: 1807 case ARM::VLD1d64Q: 1808 case ARM::VLD1d8Q_UPD: 1809 case ARM::VLD1d16Q_UPD: 1810 case ARM::VLD1d32Q_UPD: 1811 case ARM::VLD1d64Q_UPD: 1812 case ARM::VLD2q8: 1813 case ARM::VLD2q16: 1814 case ARM::VLD2q32: 1815 case ARM::VLD2q8_UPD: 1816 case ARM::VLD2q16_UPD: 1817 case ARM::VLD2q32_UPD: 1818 case ARM::VLD4d8: 1819 case ARM::VLD4d16: 1820 case ARM::VLD4d32: 1821 case ARM::VLD4d8_UPD: 1822 case ARM::VLD4d16_UPD: 1823 case ARM::VLD4d32_UPD: 1824 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 1825 return MCDisassembler::Fail; 1826 break; 1827 case ARM::VLD4q8: 1828 case ARM::VLD4q16: 1829 case ARM::VLD4q32: 1830 case ARM::VLD4q8_UPD: 1831 case ARM::VLD4q16_UPD: 1832 case ARM::VLD4q32_UPD: 1833 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 1834 return MCDisassembler::Fail; 1835 break; 1836 default: 1837 break; 1838 } 1839 1840 // Writeback operand 1841 switch (Inst.getOpcode()) { 1842 case ARM::VLD1d8_UPD: 1843 case ARM::VLD1d16_UPD: 1844 case ARM::VLD1d32_UPD: 1845 case ARM::VLD1d64_UPD: 1846 case ARM::VLD1q8_UPD: 1847 case ARM::VLD1q16_UPD: 1848 case ARM::VLD1q32_UPD: 1849 case ARM::VLD1q64_UPD: 1850 case ARM::VLD1d8T_UPD: 1851 case ARM::VLD1d16T_UPD: 1852 case ARM::VLD1d32T_UPD: 1853 case ARM::VLD1d64T_UPD: 1854 case ARM::VLD1d8Q_UPD: 1855 case ARM::VLD1d16Q_UPD: 1856 case ARM::VLD1d32Q_UPD: 1857 case ARM::VLD1d64Q_UPD: 1858 case ARM::VLD2d8_UPD: 1859 case ARM::VLD2d16_UPD: 1860 case ARM::VLD2d32_UPD: 1861 case ARM::VLD2q8_UPD: 1862 case ARM::VLD2q16_UPD: 1863 case ARM::VLD2q32_UPD: 1864 case ARM::VLD2b8_UPD: 1865 case ARM::VLD2b16_UPD: 1866 case ARM::VLD2b32_UPD: 1867 case ARM::VLD3d8_UPD: 1868 case ARM::VLD3d16_UPD: 1869 case ARM::VLD3d32_UPD: 1870 case ARM::VLD3q8_UPD: 1871 case ARM::VLD3q16_UPD: 1872 case ARM::VLD3q32_UPD: 1873 case ARM::VLD4d8_UPD: 1874 case ARM::VLD4d16_UPD: 1875 case ARM::VLD4d32_UPD: 1876 case ARM::VLD4q8_UPD: 1877 case ARM::VLD4q16_UPD: 1878 case ARM::VLD4q32_UPD: 1879 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 1880 return MCDisassembler::Fail; 1881 break; 1882 default: 1883 break; 1884 } 1885 1886 // AddrMode6 Base (register+alignment) 1887 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 1888 return MCDisassembler::Fail; 1889 1890 // AddrMode6 Offset (register) 1891 if (Rm == 0xD) 1892 Inst.addOperand(MCOperand::CreateReg(0)); 1893 else if (Rm != 0xF) { 1894 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1895 return MCDisassembler::Fail; 1896 } 1897 1898 return S; 1899 } 1900 1901 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1902 uint64_t Address, const void *Decoder) { 1903 DecodeStatus S = MCDisassembler::Success; 1904 1905 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1906 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1907 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1908 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1909 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1910 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1911 1912 // Writeback Operand 1913 switch (Inst.getOpcode()) { 1914 case ARM::VST1d8_UPD: 1915 case ARM::VST1d16_UPD: 1916 case ARM::VST1d32_UPD: 1917 case ARM::VST1d64_UPD: 1918 case ARM::VST1q8_UPD: 1919 case ARM::VST1q16_UPD: 1920 case ARM::VST1q32_UPD: 1921 case ARM::VST1q64_UPD: 1922 case ARM::VST1d8T_UPD: 1923 case ARM::VST1d16T_UPD: 1924 case ARM::VST1d32T_UPD: 1925 case ARM::VST1d64T_UPD: 1926 case ARM::VST1d8Q_UPD: 1927 case ARM::VST1d16Q_UPD: 1928 case ARM::VST1d32Q_UPD: 1929 case ARM::VST1d64Q_UPD: 1930 case ARM::VST2d8_UPD: 1931 case ARM::VST2d16_UPD: 1932 case ARM::VST2d32_UPD: 1933 case ARM::VST2q8_UPD: 1934 case ARM::VST2q16_UPD: 1935 case ARM::VST2q32_UPD: 1936 case ARM::VST2b8_UPD: 1937 case ARM::VST2b16_UPD: 1938 case ARM::VST2b32_UPD: 1939 case ARM::VST3d8_UPD: 1940 case ARM::VST3d16_UPD: 1941 case ARM::VST3d32_UPD: 1942 case ARM::VST3q8_UPD: 1943 case ARM::VST3q16_UPD: 1944 case ARM::VST3q32_UPD: 1945 case ARM::VST4d8_UPD: 1946 case ARM::VST4d16_UPD: 1947 case ARM::VST4d32_UPD: 1948 case ARM::VST4q8_UPD: 1949 case ARM::VST4q16_UPD: 1950 case ARM::VST4q32_UPD: 1951 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 1952 return MCDisassembler::Fail; 1953 break; 1954 default: 1955 break; 1956 } 1957 1958 // AddrMode6 Base (register+alignment) 1959 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 1960 return MCDisassembler::Fail; 1961 1962 // AddrMode6 Offset (register) 1963 if (Rm == 0xD) 1964 Inst.addOperand(MCOperand::CreateReg(0)); 1965 else if (Rm != 0xF) { 1966 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1967 return MCDisassembler::Fail; 1968 } 1969 1970 // First input register 1971 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 1972 return MCDisassembler::Fail; 1973 1974 // Second input register 1975 switch (Inst.getOpcode()) { 1976 case ARM::VST1q8: 1977 case ARM::VST1q16: 1978 case ARM::VST1q32: 1979 case ARM::VST1q64: 1980 case ARM::VST1q8_UPD: 1981 case ARM::VST1q16_UPD: 1982 case ARM::VST1q32_UPD: 1983 case ARM::VST1q64_UPD: 1984 case ARM::VST1d8T: 1985 case ARM::VST1d16T: 1986 case ARM::VST1d32T: 1987 case ARM::VST1d64T: 1988 case ARM::VST1d8T_UPD: 1989 case ARM::VST1d16T_UPD: 1990 case ARM::VST1d32T_UPD: 1991 case ARM::VST1d64T_UPD: 1992 case ARM::VST1d8Q: 1993 case ARM::VST1d16Q: 1994 case ARM::VST1d32Q: 1995 case ARM::VST1d64Q: 1996 case ARM::VST1d8Q_UPD: 1997 case ARM::VST1d16Q_UPD: 1998 case ARM::VST1d32Q_UPD: 1999 case ARM::VST1d64Q_UPD: 2000 case ARM::VST2d8: 2001 case ARM::VST2d16: 2002 case ARM::VST2d32: 2003 case ARM::VST2d8_UPD: 2004 case ARM::VST2d16_UPD: 2005 case ARM::VST2d32_UPD: 2006 case ARM::VST2q8: 2007 case ARM::VST2q16: 2008 case ARM::VST2q32: 2009 case ARM::VST2q8_UPD: 2010 case ARM::VST2q16_UPD: 2011 case ARM::VST2q32_UPD: 2012 case ARM::VST3d8: 2013 case ARM::VST3d16: 2014 case ARM::VST3d32: 2015 case ARM::VST3d8_UPD: 2016 case ARM::VST3d16_UPD: 2017 case ARM::VST3d32_UPD: 2018 case ARM::VST4d8: 2019 case ARM::VST4d16: 2020 case ARM::VST4d32: 2021 case ARM::VST4d8_UPD: 2022 case ARM::VST4d16_UPD: 2023 case ARM::VST4d32_UPD: 2024 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2025 return MCDisassembler::Fail; 2026 break; 2027 case ARM::VST2b8: 2028 case ARM::VST2b16: 2029 case ARM::VST2b32: 2030 case ARM::VST2b8_UPD: 2031 case ARM::VST2b16_UPD: 2032 case ARM::VST2b32_UPD: 2033 case ARM::VST3q8: 2034 case ARM::VST3q16: 2035 case ARM::VST3q32: 2036 case ARM::VST3q8_UPD: 2037 case ARM::VST3q16_UPD: 2038 case ARM::VST3q32_UPD: 2039 case ARM::VST4q8: 2040 case ARM::VST4q16: 2041 case ARM::VST4q32: 2042 case ARM::VST4q8_UPD: 2043 case ARM::VST4q16_UPD: 2044 case ARM::VST4q32_UPD: 2045 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2046 return MCDisassembler::Fail; 2047 break; 2048 default: 2049 break; 2050 } 2051 2052 // Third input register 2053 switch (Inst.getOpcode()) { 2054 case ARM::VST1d8T: 2055 case ARM::VST1d16T: 2056 case ARM::VST1d32T: 2057 case ARM::VST1d64T: 2058 case ARM::VST1d8T_UPD: 2059 case ARM::VST1d16T_UPD: 2060 case ARM::VST1d32T_UPD: 2061 case ARM::VST1d64T_UPD: 2062 case ARM::VST1d8Q: 2063 case ARM::VST1d16Q: 2064 case ARM::VST1d32Q: 2065 case ARM::VST1d64Q: 2066 case ARM::VST1d8Q_UPD: 2067 case ARM::VST1d16Q_UPD: 2068 case ARM::VST1d32Q_UPD: 2069 case ARM::VST1d64Q_UPD: 2070 case ARM::VST2q8: 2071 case ARM::VST2q16: 2072 case ARM::VST2q32: 2073 case ARM::VST2q8_UPD: 2074 case ARM::VST2q16_UPD: 2075 case ARM::VST2q32_UPD: 2076 case ARM::VST3d8: 2077 case ARM::VST3d16: 2078 case ARM::VST3d32: 2079 case ARM::VST3d8_UPD: 2080 case ARM::VST3d16_UPD: 2081 case ARM::VST3d32_UPD: 2082 case ARM::VST4d8: 2083 case ARM::VST4d16: 2084 case ARM::VST4d32: 2085 case ARM::VST4d8_UPD: 2086 case ARM::VST4d16_UPD: 2087 case ARM::VST4d32_UPD: 2088 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2089 return MCDisassembler::Fail; 2090 break; 2091 case ARM::VST3q8: 2092 case ARM::VST3q16: 2093 case ARM::VST3q32: 2094 case ARM::VST3q8_UPD: 2095 case ARM::VST3q16_UPD: 2096 case ARM::VST3q32_UPD: 2097 case ARM::VST4q8: 2098 case ARM::VST4q16: 2099 case ARM::VST4q32: 2100 case ARM::VST4q8_UPD: 2101 case ARM::VST4q16_UPD: 2102 case ARM::VST4q32_UPD: 2103 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2104 return MCDisassembler::Fail; 2105 break; 2106 default: 2107 break; 2108 } 2109 2110 // Fourth input register 2111 switch (Inst.getOpcode()) { 2112 case ARM::VST1d8Q: 2113 case ARM::VST1d16Q: 2114 case ARM::VST1d32Q: 2115 case ARM::VST1d64Q: 2116 case ARM::VST1d8Q_UPD: 2117 case ARM::VST1d16Q_UPD: 2118 case ARM::VST1d32Q_UPD: 2119 case ARM::VST1d64Q_UPD: 2120 case ARM::VST2q8: 2121 case ARM::VST2q16: 2122 case ARM::VST2q32: 2123 case ARM::VST2q8_UPD: 2124 case ARM::VST2q16_UPD: 2125 case ARM::VST2q32_UPD: 2126 case ARM::VST4d8: 2127 case ARM::VST4d16: 2128 case ARM::VST4d32: 2129 case ARM::VST4d8_UPD: 2130 case ARM::VST4d16_UPD: 2131 case ARM::VST4d32_UPD: 2132 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2133 return MCDisassembler::Fail; 2134 break; 2135 case ARM::VST4q8: 2136 case ARM::VST4q16: 2137 case ARM::VST4q32: 2138 case ARM::VST4q8_UPD: 2139 case ARM::VST4q16_UPD: 2140 case ARM::VST4q32_UPD: 2141 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2142 return MCDisassembler::Fail; 2143 break; 2144 default: 2145 break; 2146 } 2147 2148 return S; 2149 } 2150 2151 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2152 uint64_t Address, const void *Decoder) { 2153 DecodeStatus S = MCDisassembler::Success; 2154 2155 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2156 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2157 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2158 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2159 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2160 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2161 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 2162 2163 align *= (1 << size); 2164 2165 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2166 return MCDisassembler::Fail; 2167 if (regs == 2) { 2168 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2169 return MCDisassembler::Fail; 2170 } 2171 if (Rm != 0xF) { 2172 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2173 return MCDisassembler::Fail; 2174 } 2175 2176 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2177 return MCDisassembler::Fail; 2178 Inst.addOperand(MCOperand::CreateImm(align)); 2179 2180 if (Rm == 0xD) 2181 Inst.addOperand(MCOperand::CreateReg(0)); 2182 else if (Rm != 0xF) { 2183 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2184 return MCDisassembler::Fail; 2185 } 2186 2187 return S; 2188 } 2189 2190 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2191 uint64_t Address, const void *Decoder) { 2192 DecodeStatus S = MCDisassembler::Success; 2193 2194 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2195 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2196 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2197 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2198 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2199 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2200 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2201 align *= 2*size; 2202 2203 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2204 return MCDisassembler::Fail; 2205 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2206 return MCDisassembler::Fail; 2207 if (Rm != 0xF) { 2208 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2209 return MCDisassembler::Fail; 2210 } 2211 2212 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2213 return MCDisassembler::Fail; 2214 Inst.addOperand(MCOperand::CreateImm(align)); 2215 2216 if (Rm == 0xD) 2217 Inst.addOperand(MCOperand::CreateReg(0)); 2218 else if (Rm != 0xF) { 2219 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2220 return MCDisassembler::Fail; 2221 } 2222 2223 return S; 2224 } 2225 2226 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2227 uint64_t Address, const void *Decoder) { 2228 DecodeStatus S = MCDisassembler::Success; 2229 2230 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2231 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2232 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2233 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2234 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2235 2236 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2237 return MCDisassembler::Fail; 2238 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2239 return MCDisassembler::Fail; 2240 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2241 return MCDisassembler::Fail; 2242 if (Rm != 0xF) { 2243 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2244 return MCDisassembler::Fail; 2245 } 2246 2247 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2248 return MCDisassembler::Fail; 2249 Inst.addOperand(MCOperand::CreateImm(0)); 2250 2251 if (Rm == 0xD) 2252 Inst.addOperand(MCOperand::CreateReg(0)); 2253 else if (Rm != 0xF) { 2254 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2255 return MCDisassembler::Fail; 2256 } 2257 2258 return S; 2259 } 2260 2261 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2262 uint64_t Address, const void *Decoder) { 2263 DecodeStatus S = MCDisassembler::Success; 2264 2265 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2266 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2267 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2268 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2269 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2270 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2271 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2272 2273 if (size == 0x3) { 2274 size = 4; 2275 align = 16; 2276 } else { 2277 if (size == 2) { 2278 size = 1 << size; 2279 align *= 8; 2280 } else { 2281 size = 1 << size; 2282 align *= 4*size; 2283 } 2284 } 2285 2286 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2287 return MCDisassembler::Fail; 2288 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2289 return MCDisassembler::Fail; 2290 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2291 return MCDisassembler::Fail; 2292 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2293 return MCDisassembler::Fail; 2294 if (Rm != 0xF) { 2295 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2296 return MCDisassembler::Fail; 2297 } 2298 2299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2300 return MCDisassembler::Fail; 2301 Inst.addOperand(MCOperand::CreateImm(align)); 2302 2303 if (Rm == 0xD) 2304 Inst.addOperand(MCOperand::CreateReg(0)); 2305 else if (Rm != 0xF) { 2306 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2307 return MCDisassembler::Fail; 2308 } 2309 2310 return S; 2311 } 2312 2313 static DecodeStatus 2314 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2315 uint64_t Address, const void *Decoder) { 2316 DecodeStatus S = MCDisassembler::Success; 2317 2318 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2319 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2320 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2321 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2322 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2323 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2324 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2325 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2326 2327 if (Q) { 2328 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2329 return MCDisassembler::Fail; 2330 } else { 2331 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2332 return MCDisassembler::Fail; 2333 } 2334 2335 Inst.addOperand(MCOperand::CreateImm(imm)); 2336 2337 switch (Inst.getOpcode()) { 2338 case ARM::VORRiv4i16: 2339 case ARM::VORRiv2i32: 2340 case ARM::VBICiv4i16: 2341 case ARM::VBICiv2i32: 2342 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2343 return MCDisassembler::Fail; 2344 break; 2345 case ARM::VORRiv8i16: 2346 case ARM::VORRiv4i32: 2347 case ARM::VBICiv8i16: 2348 case ARM::VBICiv4i32: 2349 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2350 return MCDisassembler::Fail; 2351 break; 2352 default: 2353 break; 2354 } 2355 2356 return S; 2357 } 2358 2359 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2360 uint64_t Address, const void *Decoder) { 2361 DecodeStatus S = MCDisassembler::Success; 2362 2363 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2364 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2365 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2366 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2367 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2368 2369 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2370 return MCDisassembler::Fail; 2371 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2372 return MCDisassembler::Fail; 2373 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2374 2375 return S; 2376 } 2377 2378 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2379 uint64_t Address, const void *Decoder) { 2380 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2381 return MCDisassembler::Success; 2382 } 2383 2384 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2385 uint64_t Address, const void *Decoder) { 2386 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2387 return MCDisassembler::Success; 2388 } 2389 2390 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2391 uint64_t Address, const void *Decoder) { 2392 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2393 return MCDisassembler::Success; 2394 } 2395 2396 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2397 uint64_t Address, const void *Decoder) { 2398 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2399 return MCDisassembler::Success; 2400 } 2401 2402 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2403 uint64_t Address, const void *Decoder) { 2404 DecodeStatus S = MCDisassembler::Success; 2405 2406 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2407 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2408 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2409 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2410 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2411 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2412 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2413 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2414 2415 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2416 return MCDisassembler::Fail; 2417 if (op) { 2418 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2419 return MCDisassembler::Fail; // Writeback 2420 } 2421 2422 for (unsigned i = 0; i < length; ++i) { 2423 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder))) 2424 return MCDisassembler::Fail; 2425 } 2426 2427 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2428 return MCDisassembler::Fail; 2429 2430 return S; 2431 } 2432 2433 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2434 uint64_t Address, const void *Decoder) { 2435 // The immediate needs to be a fully instantiated float. However, the 2436 // auto-generated decoder is only able to fill in some of the bits 2437 // necessary. For instance, the 'b' bit is replicated multiple times, 2438 // and is even present in inverted form in one bit. We do a little 2439 // binary parsing here to fill in those missing bits, and then 2440 // reinterpret it all as a float. 2441 union { 2442 uint32_t integer; 2443 float fp; 2444 } fp_conv; 2445 2446 fp_conv.integer = Val; 2447 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2448 fp_conv.integer |= b << 26; 2449 fp_conv.integer |= b << 27; 2450 fp_conv.integer |= b << 28; 2451 fp_conv.integer |= b << 29; 2452 fp_conv.integer |= (~b & 0x1) << 30; 2453 2454 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2455 return MCDisassembler::Success; 2456 } 2457 2458 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2459 uint64_t Address, const void *Decoder) { 2460 DecodeStatus S = MCDisassembler::Success; 2461 2462 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2463 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2464 2465 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2466 return MCDisassembler::Fail; 2467 2468 switch(Inst.getOpcode()) { 2469 default: 2470 return MCDisassembler::Fail; 2471 case ARM::tADR: 2472 break; // tADR does not explicitly represent the PC as an operand. 2473 case ARM::tADDrSPi: 2474 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2475 break; 2476 } 2477 2478 Inst.addOperand(MCOperand::CreateImm(imm)); 2479 return S; 2480 } 2481 2482 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2483 uint64_t Address, const void *Decoder) { 2484 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2485 return MCDisassembler::Success; 2486 } 2487 2488 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2489 uint64_t Address, const void *Decoder) { 2490 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2491 return MCDisassembler::Success; 2492 } 2493 2494 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2495 uint64_t Address, const void *Decoder) { 2496 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2497 return MCDisassembler::Success; 2498 } 2499 2500 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2501 uint64_t Address, const void *Decoder) { 2502 DecodeStatus S = MCDisassembler::Success; 2503 2504 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2505 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2506 2507 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2508 return MCDisassembler::Fail; 2509 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 2510 return MCDisassembler::Fail; 2511 2512 return S; 2513 } 2514 2515 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2516 uint64_t Address, const void *Decoder) { 2517 DecodeStatus S = MCDisassembler::Success; 2518 2519 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2520 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2521 2522 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2523 return MCDisassembler::Fail; 2524 Inst.addOperand(MCOperand::CreateImm(imm)); 2525 2526 return S; 2527 } 2528 2529 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2530 uint64_t Address, const void *Decoder) { 2531 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2532 2533 return MCDisassembler::Success; 2534 } 2535 2536 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2537 uint64_t Address, const void *Decoder) { 2538 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2539 Inst.addOperand(MCOperand::CreateImm(Val)); 2540 2541 return MCDisassembler::Success; 2542 } 2543 2544 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2545 uint64_t Address, const void *Decoder) { 2546 DecodeStatus S = MCDisassembler::Success; 2547 2548 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2549 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2550 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2551 2552 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2553 return MCDisassembler::Fail; 2554 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 2555 return MCDisassembler::Fail; 2556 Inst.addOperand(MCOperand::CreateImm(imm)); 2557 2558 return S; 2559 } 2560 2561 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2562 uint64_t Address, const void *Decoder) { 2563 DecodeStatus S = MCDisassembler::Success; 2564 2565 switch (Inst.getOpcode()) { 2566 case ARM::t2PLDs: 2567 case ARM::t2PLDWs: 2568 case ARM::t2PLIs: 2569 break; 2570 default: { 2571 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2572 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2573 return MCDisassembler::Fail; 2574 } 2575 } 2576 2577 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2578 if (Rn == 0xF) { 2579 switch (Inst.getOpcode()) { 2580 case ARM::t2LDRBs: 2581 Inst.setOpcode(ARM::t2LDRBpci); 2582 break; 2583 case ARM::t2LDRHs: 2584 Inst.setOpcode(ARM::t2LDRHpci); 2585 break; 2586 case ARM::t2LDRSHs: 2587 Inst.setOpcode(ARM::t2LDRSHpci); 2588 break; 2589 case ARM::t2LDRSBs: 2590 Inst.setOpcode(ARM::t2LDRSBpci); 2591 break; 2592 case ARM::t2PLDs: 2593 Inst.setOpcode(ARM::t2PLDi12); 2594 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2595 break; 2596 default: 2597 return MCDisassembler::Fail; 2598 } 2599 2600 int imm = fieldFromInstruction32(Insn, 0, 12); 2601 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2602 Inst.addOperand(MCOperand::CreateImm(imm)); 2603 2604 return S; 2605 } 2606 2607 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2608 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2609 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2610 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 2611 return MCDisassembler::Fail; 2612 2613 return S; 2614 } 2615 2616 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2617 uint64_t Address, const void *Decoder) { 2618 int imm = Val & 0xFF; 2619 if (!(Val & 0x100)) imm *= -1; 2620 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2621 2622 return MCDisassembler::Success; 2623 } 2624 2625 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2626 uint64_t Address, const void *Decoder) { 2627 DecodeStatus S = MCDisassembler::Success; 2628 2629 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2630 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2631 2632 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2633 return MCDisassembler::Fail; 2634 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 2635 return MCDisassembler::Fail; 2636 2637 return S; 2638 } 2639 2640 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2641 uint64_t Address, const void *Decoder) { 2642 int imm = Val & 0xFF; 2643 if (!(Val & 0x100)) imm *= -1; 2644 Inst.addOperand(MCOperand::CreateImm(imm)); 2645 2646 return MCDisassembler::Success; 2647 } 2648 2649 2650 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2651 uint64_t Address, const void *Decoder) { 2652 DecodeStatus S = MCDisassembler::Success; 2653 2654 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2655 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2656 2657 // Some instructions always use an additive offset. 2658 switch (Inst.getOpcode()) { 2659 case ARM::t2LDRT: 2660 case ARM::t2LDRBT: 2661 case ARM::t2LDRHT: 2662 case ARM::t2LDRSBT: 2663 case ARM::t2LDRSHT: 2664 imm |= 0x100; 2665 break; 2666 default: 2667 break; 2668 } 2669 2670 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2671 return MCDisassembler::Fail; 2672 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 2673 return MCDisassembler::Fail; 2674 2675 return S; 2676 } 2677 2678 2679 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2680 uint64_t Address, const void *Decoder) { 2681 DecodeStatus S = MCDisassembler::Success; 2682 2683 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2684 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2685 2686 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2687 return MCDisassembler::Fail; 2688 Inst.addOperand(MCOperand::CreateImm(imm)); 2689 2690 return S; 2691 } 2692 2693 2694 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2695 uint64_t Address, const void *Decoder) { 2696 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2697 2698 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2699 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2700 Inst.addOperand(MCOperand::CreateImm(imm)); 2701 2702 return MCDisassembler::Success; 2703 } 2704 2705 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2706 uint64_t Address, const void *Decoder) { 2707 DecodeStatus S = MCDisassembler::Success; 2708 2709 if (Inst.getOpcode() == ARM::tADDrSP) { 2710 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2711 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2712 2713 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2714 return MCDisassembler::Fail; 2715 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2716 return MCDisassembler::Fail; 2717 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2718 } else if (Inst.getOpcode() == ARM::tADDspr) { 2719 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2720 2721 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2722 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2723 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2724 return MCDisassembler::Fail; 2725 } 2726 2727 return S; 2728 } 2729 2730 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2731 uint64_t Address, const void *Decoder) { 2732 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2733 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2734 2735 Inst.addOperand(MCOperand::CreateImm(imod)); 2736 Inst.addOperand(MCOperand::CreateImm(flags)); 2737 2738 return MCDisassembler::Success; 2739 } 2740 2741 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2742 uint64_t Address, const void *Decoder) { 2743 DecodeStatus S = MCDisassembler::Success; 2744 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2745 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2746 2747 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2748 return MCDisassembler::Fail; 2749 Inst.addOperand(MCOperand::CreateImm(add)); 2750 2751 return S; 2752 } 2753 2754 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2755 uint64_t Address, const void *Decoder) { 2756 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2757 return MCDisassembler::Success; 2758 } 2759 2760 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2761 uint64_t Address, const void *Decoder) { 2762 if (Val == 0xA || Val == 0xB) 2763 return MCDisassembler::Fail; 2764 2765 Inst.addOperand(MCOperand::CreateImm(Val)); 2766 return MCDisassembler::Success; 2767 } 2768 2769 static DecodeStatus 2770 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2771 uint64_t Address, const void *Decoder) { 2772 DecodeStatus S = MCDisassembler::Success; 2773 2774 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2775 if (pred == 0xE || pred == 0xF) { 2776 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 2777 switch (opc) { 2778 default: 2779 return MCDisassembler::Fail; 2780 case 0xf3bf8f4: 2781 Inst.setOpcode(ARM::t2DSB); 2782 break; 2783 case 0xf3bf8f5: 2784 Inst.setOpcode(ARM::t2DMB); 2785 break; 2786 case 0xf3bf8f6: 2787 Inst.setOpcode(ARM::t2ISB); 2788 return MCDisassembler::Success; 2789 } 2790 2791 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2792 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2793 } 2794 2795 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2796 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2797 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2798 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2799 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2800 2801 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 2802 return MCDisassembler::Fail; 2803 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2804 return MCDisassembler::Fail; 2805 2806 return S; 2807 } 2808 2809 // Decode a shifted immediate operand. These basically consist 2810 // of an 8-bit value, and a 4-bit directive that specifies either 2811 // a splat operation or a rotation. 2812 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2813 uint64_t Address, const void *Decoder) { 2814 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2815 if (ctrl == 0) { 2816 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2817 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2818 switch (byte) { 2819 case 0: 2820 Inst.addOperand(MCOperand::CreateImm(imm)); 2821 break; 2822 case 1: 2823 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2824 break; 2825 case 2: 2826 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2827 break; 2828 case 3: 2829 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2830 (imm << 8) | imm)); 2831 break; 2832 } 2833 } else { 2834 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2835 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2836 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2837 Inst.addOperand(MCOperand::CreateImm(imm)); 2838 } 2839 2840 return MCDisassembler::Success; 2841 } 2842 2843 static DecodeStatus 2844 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2845 uint64_t Address, const void *Decoder){ 2846 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2847 return MCDisassembler::Success; 2848 } 2849 2850 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2851 uint64_t Address, const void *Decoder){ 2852 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2853 return MCDisassembler::Success; 2854 } 2855 2856 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2857 uint64_t Address, const void *Decoder) { 2858 switch (Val) { 2859 default: 2860 return MCDisassembler::Fail; 2861 case 0xF: // SY 2862 case 0xE: // ST 2863 case 0xB: // ISH 2864 case 0xA: // ISHST 2865 case 0x7: // NSH 2866 case 0x6: // NSHST 2867 case 0x3: // OSH 2868 case 0x2: // OSHST 2869 break; 2870 } 2871 2872 Inst.addOperand(MCOperand::CreateImm(Val)); 2873 return MCDisassembler::Success; 2874 } 2875 2876 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 2877 uint64_t Address, const void *Decoder) { 2878 if (!Val) return MCDisassembler::Fail; 2879 Inst.addOperand(MCOperand::CreateImm(Val)); 2880 return MCDisassembler::Success; 2881 } 2882 2883 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 2884 uint64_t Address, const void *Decoder) { 2885 DecodeStatus S = MCDisassembler::Success; 2886 2887 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2888 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2889 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2890 2891 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 2892 2893 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2894 return MCDisassembler::Fail; 2895 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2896 return MCDisassembler::Fail; 2897 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2898 return MCDisassembler::Fail; 2899 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2900 return MCDisassembler::Fail; 2901 2902 return S; 2903 } 2904 2905 2906 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 2907 uint64_t Address, const void *Decoder){ 2908 DecodeStatus S = MCDisassembler::Success; 2909 2910 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2911 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 2912 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2913 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2914 2915 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2916 return MCDisassembler::Fail; 2917 2918 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 2919 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 2920 2921 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2922 return MCDisassembler::Fail; 2923 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2924 return MCDisassembler::Fail; 2925 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2926 return MCDisassembler::Fail; 2927 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2928 return MCDisassembler::Fail; 2929 2930 return S; 2931 } 2932 2933 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 2934 uint64_t Address, const void *Decoder) { 2935 DecodeStatus S = MCDisassembler::Success; 2936 2937 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2938 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2939 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2940 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2941 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2942 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2943 2944 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 2945 2946 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2947 return MCDisassembler::Fail; 2948 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2949 return MCDisassembler::Fail; 2950 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 2951 return MCDisassembler::Fail; 2952 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2953 return MCDisassembler::Fail; 2954 2955 return S; 2956 } 2957 2958 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 2959 uint64_t Address, const void *Decoder) { 2960 DecodeStatus S = MCDisassembler::Success; 2961 2962 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2963 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2964 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2965 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2966 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2967 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2968 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2969 2970 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 2971 if (Rm == 0xF) S = MCDisassembler::SoftFail; 2972 2973 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2974 return MCDisassembler::Fail; 2975 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2976 return MCDisassembler::Fail; 2977 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 2978 return MCDisassembler::Fail; 2979 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2980 return MCDisassembler::Fail; 2981 2982 return S; 2983 } 2984 2985 2986 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 2987 uint64_t Address, const void *Decoder) { 2988 DecodeStatus S = MCDisassembler::Success; 2989 2990 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2991 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2992 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2993 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2994 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2995 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2996 2997 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 2998 2999 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3000 return MCDisassembler::Fail; 3001 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3002 return MCDisassembler::Fail; 3003 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3004 return MCDisassembler::Fail; 3005 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3006 return MCDisassembler::Fail; 3007 3008 return S; 3009 } 3010 3011 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 3012 uint64_t Address, const void *Decoder) { 3013 DecodeStatus S = MCDisassembler::Success; 3014 3015 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3016 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3017 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3018 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3019 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3020 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3021 3022 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3023 3024 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3025 return MCDisassembler::Fail; 3026 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3027 return MCDisassembler::Fail; 3028 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3029 return MCDisassembler::Fail; 3030 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3031 return MCDisassembler::Fail; 3032 3033 return S; 3034 } 3035 3036 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 3037 uint64_t Address, const void *Decoder) { 3038 DecodeStatus S = MCDisassembler::Success; 3039 3040 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3041 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3042 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3043 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3044 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3045 3046 unsigned align = 0; 3047 unsigned index = 0; 3048 switch (size) { 3049 default: 3050 return MCDisassembler::Fail; 3051 case 0: 3052 if (fieldFromInstruction32(Insn, 4, 1)) 3053 return MCDisassembler::Fail; // UNDEFINED 3054 index = fieldFromInstruction32(Insn, 5, 3); 3055 break; 3056 case 1: 3057 if (fieldFromInstruction32(Insn, 5, 1)) 3058 return MCDisassembler::Fail; // UNDEFINED 3059 index = fieldFromInstruction32(Insn, 6, 2); 3060 if (fieldFromInstruction32(Insn, 4, 1)) 3061 align = 2; 3062 break; 3063 case 2: 3064 if (fieldFromInstruction32(Insn, 6, 1)) 3065 return MCDisassembler::Fail; // UNDEFINED 3066 index = fieldFromInstruction32(Insn, 7, 1); 3067 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3068 align = 4; 3069 } 3070 3071 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3072 return MCDisassembler::Fail; 3073 if (Rm != 0xF) { // Writeback 3074 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3075 return MCDisassembler::Fail; 3076 } 3077 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3078 return MCDisassembler::Fail; 3079 Inst.addOperand(MCOperand::CreateImm(align)); 3080 if (Rm != 0xF) { 3081 if (Rm != 0xD) { 3082 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3083 return MCDisassembler::Fail; 3084 } else 3085 Inst.addOperand(MCOperand::CreateReg(0)); 3086 } 3087 3088 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3089 return MCDisassembler::Fail; 3090 Inst.addOperand(MCOperand::CreateImm(index)); 3091 3092 return S; 3093 } 3094 3095 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 3096 uint64_t Address, const void *Decoder) { 3097 DecodeStatus S = MCDisassembler::Success; 3098 3099 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3100 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3101 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3102 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3103 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3104 3105 unsigned align = 0; 3106 unsigned index = 0; 3107 switch (size) { 3108 default: 3109 return MCDisassembler::Fail; 3110 case 0: 3111 if (fieldFromInstruction32(Insn, 4, 1)) 3112 return MCDisassembler::Fail; // UNDEFINED 3113 index = fieldFromInstruction32(Insn, 5, 3); 3114 break; 3115 case 1: 3116 if (fieldFromInstruction32(Insn, 5, 1)) 3117 return MCDisassembler::Fail; // UNDEFINED 3118 index = fieldFromInstruction32(Insn, 6, 2); 3119 if (fieldFromInstruction32(Insn, 4, 1)) 3120 align = 2; 3121 break; 3122 case 2: 3123 if (fieldFromInstruction32(Insn, 6, 1)) 3124 return MCDisassembler::Fail; // UNDEFINED 3125 index = fieldFromInstruction32(Insn, 7, 1); 3126 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3127 align = 4; 3128 } 3129 3130 if (Rm != 0xF) { // Writeback 3131 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3132 return MCDisassembler::Fail; 3133 } 3134 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3135 return MCDisassembler::Fail; 3136 Inst.addOperand(MCOperand::CreateImm(align)); 3137 if (Rm != 0xF) { 3138 if (Rm != 0xD) { 3139 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3140 return MCDisassembler::Fail; 3141 } else 3142 Inst.addOperand(MCOperand::CreateReg(0)); 3143 } 3144 3145 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3146 return MCDisassembler::Fail; 3147 Inst.addOperand(MCOperand::CreateImm(index)); 3148 3149 return S; 3150 } 3151 3152 3153 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 3154 uint64_t Address, const void *Decoder) { 3155 DecodeStatus S = MCDisassembler::Success; 3156 3157 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3158 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3159 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3160 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3161 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3162 3163 unsigned align = 0; 3164 unsigned index = 0; 3165 unsigned inc = 1; 3166 switch (size) { 3167 default: 3168 return MCDisassembler::Fail; 3169 case 0: 3170 index = fieldFromInstruction32(Insn, 5, 3); 3171 if (fieldFromInstruction32(Insn, 4, 1)) 3172 align = 2; 3173 break; 3174 case 1: 3175 index = fieldFromInstruction32(Insn, 6, 2); 3176 if (fieldFromInstruction32(Insn, 4, 1)) 3177 align = 4; 3178 if (fieldFromInstruction32(Insn, 5, 1)) 3179 inc = 2; 3180 break; 3181 case 2: 3182 if (fieldFromInstruction32(Insn, 5, 1)) 3183 return MCDisassembler::Fail; // UNDEFINED 3184 index = fieldFromInstruction32(Insn, 7, 1); 3185 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3186 align = 8; 3187 if (fieldFromInstruction32(Insn, 6, 1)) 3188 inc = 2; 3189 break; 3190 } 3191 3192 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3193 return MCDisassembler::Fail; 3194 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3195 return MCDisassembler::Fail; 3196 if (Rm != 0xF) { // Writeback 3197 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3198 return MCDisassembler::Fail; 3199 } 3200 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3201 return MCDisassembler::Fail; 3202 Inst.addOperand(MCOperand::CreateImm(align)); 3203 if (Rm != 0xF) { 3204 if (Rm != 0xD) { 3205 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3206 return MCDisassembler::Fail; 3207 } else 3208 Inst.addOperand(MCOperand::CreateReg(0)); 3209 } 3210 3211 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3212 return MCDisassembler::Fail; 3213 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3214 return MCDisassembler::Fail; 3215 Inst.addOperand(MCOperand::CreateImm(index)); 3216 3217 return S; 3218 } 3219 3220 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 3221 uint64_t Address, const void *Decoder) { 3222 DecodeStatus S = MCDisassembler::Success; 3223 3224 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3225 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3226 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3227 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3228 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3229 3230 unsigned align = 0; 3231 unsigned index = 0; 3232 unsigned inc = 1; 3233 switch (size) { 3234 default: 3235 return MCDisassembler::Fail; 3236 case 0: 3237 index = fieldFromInstruction32(Insn, 5, 3); 3238 if (fieldFromInstruction32(Insn, 4, 1)) 3239 align = 2; 3240 break; 3241 case 1: 3242 index = fieldFromInstruction32(Insn, 6, 2); 3243 if (fieldFromInstruction32(Insn, 4, 1)) 3244 align = 4; 3245 if (fieldFromInstruction32(Insn, 5, 1)) 3246 inc = 2; 3247 break; 3248 case 2: 3249 if (fieldFromInstruction32(Insn, 5, 1)) 3250 return MCDisassembler::Fail; // UNDEFINED 3251 index = fieldFromInstruction32(Insn, 7, 1); 3252 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3253 align = 8; 3254 if (fieldFromInstruction32(Insn, 6, 1)) 3255 inc = 2; 3256 break; 3257 } 3258 3259 if (Rm != 0xF) { // Writeback 3260 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3261 return MCDisassembler::Fail; 3262 } 3263 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3264 return MCDisassembler::Fail; 3265 Inst.addOperand(MCOperand::CreateImm(align)); 3266 if (Rm != 0xF) { 3267 if (Rm != 0xD) { 3268 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3269 return MCDisassembler::Fail; 3270 } else 3271 Inst.addOperand(MCOperand::CreateReg(0)); 3272 } 3273 3274 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3275 return MCDisassembler::Fail; 3276 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3277 return MCDisassembler::Fail; 3278 Inst.addOperand(MCOperand::CreateImm(index)); 3279 3280 return S; 3281 } 3282 3283 3284 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 3285 uint64_t Address, const void *Decoder) { 3286 DecodeStatus S = MCDisassembler::Success; 3287 3288 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3289 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3290 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3291 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3292 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3293 3294 unsigned align = 0; 3295 unsigned index = 0; 3296 unsigned inc = 1; 3297 switch (size) { 3298 default: 3299 return MCDisassembler::Fail; 3300 case 0: 3301 if (fieldFromInstruction32(Insn, 4, 1)) 3302 return MCDisassembler::Fail; // UNDEFINED 3303 index = fieldFromInstruction32(Insn, 5, 3); 3304 break; 3305 case 1: 3306 if (fieldFromInstruction32(Insn, 4, 1)) 3307 return MCDisassembler::Fail; // UNDEFINED 3308 index = fieldFromInstruction32(Insn, 6, 2); 3309 if (fieldFromInstruction32(Insn, 5, 1)) 3310 inc = 2; 3311 break; 3312 case 2: 3313 if (fieldFromInstruction32(Insn, 4, 2)) 3314 return MCDisassembler::Fail; // UNDEFINED 3315 index = fieldFromInstruction32(Insn, 7, 1); 3316 if (fieldFromInstruction32(Insn, 6, 1)) 3317 inc = 2; 3318 break; 3319 } 3320 3321 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3322 return MCDisassembler::Fail; 3323 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3324 return MCDisassembler::Fail; 3325 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3326 return MCDisassembler::Fail; 3327 3328 if (Rm != 0xF) { // Writeback 3329 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3330 return MCDisassembler::Fail; 3331 } 3332 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3333 return MCDisassembler::Fail; 3334 Inst.addOperand(MCOperand::CreateImm(align)); 3335 if (Rm != 0xF) { 3336 if (Rm != 0xD) { 3337 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3338 return MCDisassembler::Fail; 3339 } else 3340 Inst.addOperand(MCOperand::CreateReg(0)); 3341 } 3342 3343 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3344 return MCDisassembler::Fail; 3345 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3346 return MCDisassembler::Fail; 3347 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3348 return MCDisassembler::Fail; 3349 Inst.addOperand(MCOperand::CreateImm(index)); 3350 3351 return S; 3352 } 3353 3354 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3355 uint64_t Address, const void *Decoder) { 3356 DecodeStatus S = MCDisassembler::Success; 3357 3358 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3359 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3360 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3361 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3362 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3363 3364 unsigned align = 0; 3365 unsigned index = 0; 3366 unsigned inc = 1; 3367 switch (size) { 3368 default: 3369 return MCDisassembler::Fail; 3370 case 0: 3371 if (fieldFromInstruction32(Insn, 4, 1)) 3372 return MCDisassembler::Fail; // UNDEFINED 3373 index = fieldFromInstruction32(Insn, 5, 3); 3374 break; 3375 case 1: 3376 if (fieldFromInstruction32(Insn, 4, 1)) 3377 return MCDisassembler::Fail; // UNDEFINED 3378 index = fieldFromInstruction32(Insn, 6, 2); 3379 if (fieldFromInstruction32(Insn, 5, 1)) 3380 inc = 2; 3381 break; 3382 case 2: 3383 if (fieldFromInstruction32(Insn, 4, 2)) 3384 return MCDisassembler::Fail; // UNDEFINED 3385 index = fieldFromInstruction32(Insn, 7, 1); 3386 if (fieldFromInstruction32(Insn, 6, 1)) 3387 inc = 2; 3388 break; 3389 } 3390 3391 if (Rm != 0xF) { // Writeback 3392 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3393 return MCDisassembler::Fail; 3394 } 3395 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3396 return MCDisassembler::Fail; 3397 Inst.addOperand(MCOperand::CreateImm(align)); 3398 if (Rm != 0xF) { 3399 if (Rm != 0xD) { 3400 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3401 return MCDisassembler::Fail; 3402 } else 3403 Inst.addOperand(MCOperand::CreateReg(0)); 3404 } 3405 3406 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3407 return MCDisassembler::Fail; 3408 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3409 return MCDisassembler::Fail; 3410 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3411 return MCDisassembler::Fail; 3412 Inst.addOperand(MCOperand::CreateImm(index)); 3413 3414 return S; 3415 } 3416 3417 3418 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3419 uint64_t Address, const void *Decoder) { 3420 DecodeStatus S = MCDisassembler::Success; 3421 3422 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3423 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3424 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3425 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3426 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3427 3428 unsigned align = 0; 3429 unsigned index = 0; 3430 unsigned inc = 1; 3431 switch (size) { 3432 default: 3433 return MCDisassembler::Fail; 3434 case 0: 3435 if (fieldFromInstruction32(Insn, 4, 1)) 3436 align = 4; 3437 index = fieldFromInstruction32(Insn, 5, 3); 3438 break; 3439 case 1: 3440 if (fieldFromInstruction32(Insn, 4, 1)) 3441 align = 8; 3442 index = fieldFromInstruction32(Insn, 6, 2); 3443 if (fieldFromInstruction32(Insn, 5, 1)) 3444 inc = 2; 3445 break; 3446 case 2: 3447 if (fieldFromInstruction32(Insn, 4, 2)) 3448 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3449 index = fieldFromInstruction32(Insn, 7, 1); 3450 if (fieldFromInstruction32(Insn, 6, 1)) 3451 inc = 2; 3452 break; 3453 } 3454 3455 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3456 return MCDisassembler::Fail; 3457 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3458 return MCDisassembler::Fail; 3459 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3460 return MCDisassembler::Fail; 3461 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3462 return MCDisassembler::Fail; 3463 3464 if (Rm != 0xF) { // Writeback 3465 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3466 return MCDisassembler::Fail; 3467 } 3468 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3469 return MCDisassembler::Fail; 3470 Inst.addOperand(MCOperand::CreateImm(align)); 3471 if (Rm != 0xF) { 3472 if (Rm != 0xD) { 3473 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3474 return MCDisassembler::Fail; 3475 } else 3476 Inst.addOperand(MCOperand::CreateReg(0)); 3477 } 3478 3479 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3480 return MCDisassembler::Fail; 3481 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3482 return MCDisassembler::Fail; 3483 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3484 return MCDisassembler::Fail; 3485 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3486 return MCDisassembler::Fail; 3487 Inst.addOperand(MCOperand::CreateImm(index)); 3488 3489 return S; 3490 } 3491 3492 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3493 uint64_t Address, const void *Decoder) { 3494 DecodeStatus S = MCDisassembler::Success; 3495 3496 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3497 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3498 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3499 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3500 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3501 3502 unsigned align = 0; 3503 unsigned index = 0; 3504 unsigned inc = 1; 3505 switch (size) { 3506 default: 3507 return MCDisassembler::Fail; 3508 case 0: 3509 if (fieldFromInstruction32(Insn, 4, 1)) 3510 align = 4; 3511 index = fieldFromInstruction32(Insn, 5, 3); 3512 break; 3513 case 1: 3514 if (fieldFromInstruction32(Insn, 4, 1)) 3515 align = 8; 3516 index = fieldFromInstruction32(Insn, 6, 2); 3517 if (fieldFromInstruction32(Insn, 5, 1)) 3518 inc = 2; 3519 break; 3520 case 2: 3521 if (fieldFromInstruction32(Insn, 4, 2)) 3522 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3523 index = fieldFromInstruction32(Insn, 7, 1); 3524 if (fieldFromInstruction32(Insn, 6, 1)) 3525 inc = 2; 3526 break; 3527 } 3528 3529 if (Rm != 0xF) { // Writeback 3530 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3531 return MCDisassembler::Fail; 3532 } 3533 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3534 return MCDisassembler::Fail; 3535 Inst.addOperand(MCOperand::CreateImm(align)); 3536 if (Rm != 0xF) { 3537 if (Rm != 0xD) { 3538 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3539 return MCDisassembler::Fail; 3540 } else 3541 Inst.addOperand(MCOperand::CreateReg(0)); 3542 } 3543 3544 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3545 return MCDisassembler::Fail; 3546 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3547 return MCDisassembler::Fail; 3548 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3549 return MCDisassembler::Fail; 3550 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3551 return MCDisassembler::Fail; 3552 Inst.addOperand(MCOperand::CreateImm(index)); 3553 3554 return S; 3555 } 3556 3557 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 3558 uint64_t Address, const void *Decoder) { 3559 DecodeStatus S = MCDisassembler::Success; 3560 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3561 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3562 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3563 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3564 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3565 3566 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3567 S = MCDisassembler::SoftFail; 3568 3569 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3570 return MCDisassembler::Fail; 3571 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3572 return MCDisassembler::Fail; 3573 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3574 return MCDisassembler::Fail; 3575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3576 return MCDisassembler::Fail; 3577 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3578 return MCDisassembler::Fail; 3579 3580 return S; 3581 } 3582 3583 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 3584 uint64_t Address, const void *Decoder) { 3585 DecodeStatus S = MCDisassembler::Success; 3586 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3587 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3588 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3589 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3590 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3591 3592 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3593 S = MCDisassembler::SoftFail; 3594 3595 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3596 return MCDisassembler::Fail; 3597 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3598 return MCDisassembler::Fail; 3599 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3600 return MCDisassembler::Fail; 3601 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3602 return MCDisassembler::Fail; 3603 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3604 return MCDisassembler::Fail; 3605 3606 return S; 3607 } 3608 3609 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn, 3610 uint64_t Address, const void *Decoder) { 3611 DecodeStatus S = MCDisassembler::Success; 3612 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 3613 // The InstPrinter needs to have the low bit of the predicate in 3614 // the mask operand to be able to print it properly. 3615 unsigned mask = fieldFromInstruction16(Insn, 0, 5); 3616 3617 if (pred == 0xF) { 3618 pred = 0xE; 3619 S = MCDisassembler::SoftFail; 3620 } 3621 3622 if ((mask & 0xF) == 0) { 3623 // Preserve the high bit of the mask, which is the low bit of 3624 // the predicate. 3625 mask &= 0x10; 3626 mask |= 0x8; 3627 S = MCDisassembler::SoftFail; 3628 } 3629 3630 Inst.addOperand(MCOperand::CreateImm(pred)); 3631 Inst.addOperand(MCOperand::CreateImm(mask)); 3632 return S; 3633 } 3634