1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARM.h" 13 #include "ARMRegisterInfo.h" 14 #include "ARMSubtarget.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCDisassembler.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 28 using namespace llvm; 29 30 typedef MCDisassembler::DecodeStatus DecodeStatus; 31 32 namespace { 33 /// ARMDisassembler - ARM disassembler for all ARM platforms. 34 class ARMDisassembler : public MCDisassembler { 35 public: 36 /// Constructor - Initializes the disassembler. 37 /// 38 ARMDisassembler(const MCSubtargetInfo &STI) : 39 MCDisassembler(STI) { 40 } 41 42 ~ARMDisassembler() { 43 } 44 45 /// getInstruction - See MCDisassembler. 46 DecodeStatus getInstruction(MCInst &instr, 47 uint64_t &size, 48 const MemoryObject ®ion, 49 uint64_t address, 50 raw_ostream &vStream) const; 51 52 /// getEDInfo - See MCDisassembler. 53 EDInstInfo *getEDInfo() const; 54 private: 55 }; 56 57 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 58 class ThumbDisassembler : public MCDisassembler { 59 public: 60 /// Constructor - Initializes the disassembler. 61 /// 62 ThumbDisassembler(const MCSubtargetInfo &STI) : 63 MCDisassembler(STI) { 64 } 65 66 ~ThumbDisassembler() { 67 } 68 69 /// getInstruction - See MCDisassembler. 70 DecodeStatus getInstruction(MCInst &instr, 71 uint64_t &size, 72 const MemoryObject ®ion, 73 uint64_t address, 74 raw_ostream &vStream) const; 75 76 /// getEDInfo - See MCDisassembler. 77 EDInstInfo *getEDInfo() const; 78 private: 79 mutable std::vector<unsigned> ITBlock; 80 void AddThumbPredicate(MCInst&) const; 81 void UpdateThumbVFPPredicate(MCInst&) const; 82 }; 83 } 84 85 static bool Check(DecodeStatus &Out, DecodeStatus In) { 86 switch (In) { 87 case MCDisassembler::Success: 88 // Out stays the same. 89 return true; 90 case MCDisassembler::SoftFail: 91 Out = In; 92 return true; 93 case MCDisassembler::Fail: 94 Out = In; 95 return false; 96 } 97 return false; 98 } 99 100 101 // Forward declare these because the autogenerated code will reference them. 102 // Definitions are further down. 103 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 104 uint64_t Address, const void *Decoder); 105 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 106 unsigned RegNo, uint64_t Address, 107 const void *Decoder); 108 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 109 uint64_t Address, const void *Decoder); 110 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 111 uint64_t Address, const void *Decoder); 112 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 113 uint64_t Address, const void *Decoder); 114 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 115 uint64_t Address, const void *Decoder); 116 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 117 uint64_t Address, const void *Decoder); 118 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 119 uint64_t Address, const void *Decoder); 120 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 121 unsigned RegNo, 122 uint64_t Address, 123 const void *Decoder); 124 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 125 uint64_t Address, const void *Decoder); 126 127 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 128 uint64_t Address, const void *Decoder); 129 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 130 uint64_t Address, const void *Decoder); 131 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 132 uint64_t Address, const void *Decoder); 133 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 134 uint64_t Address, const void *Decoder); 135 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 136 uint64_t Address, const void *Decoder); 137 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 138 uint64_t Address, const void *Decoder); 139 140 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 141 uint64_t Address, const void *Decoder); 142 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 143 uint64_t Address, const void *Decoder); 144 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 145 unsigned Insn, 146 uint64_t Address, 147 const void *Decoder); 148 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 149 uint64_t Address, const void *Decoder); 150 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 151 uint64_t Address, const void *Decoder); 152 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 153 uint64_t Address, const void *Decoder); 154 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 155 uint64_t Address, const void *Decoder); 156 157 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 158 unsigned Insn, 159 uint64_t Adddress, 160 const void *Decoder); 161 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 162 uint64_t Address, const void *Decoder); 163 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 164 uint64_t Address, const void *Decoder); 165 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 166 uint64_t Address, const void *Decoder); 167 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 168 uint64_t Address, const void *Decoder); 169 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 170 uint64_t Address, const void *Decoder); 171 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 172 uint64_t Address, const void *Decoder); 173 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 174 uint64_t Address, const void *Decoder); 175 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 176 uint64_t Address, const void *Decoder); 177 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 186 uint64_t Address, const void *Decoder); 187 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 188 uint64_t Address, const void *Decoder); 189 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 190 uint64_t Address, const void *Decoder); 191 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 192 uint64_t Address, const void *Decoder); 193 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 194 uint64_t Address, const void *Decoder); 195 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 196 uint64_t Address, const void *Decoder); 197 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 198 uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 242 uint64_t Address, const void *Decoder); 243 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 244 uint64_t Address, const void *Decoder); 245 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 246 uint64_t Address, const void *Decoder); 247 248 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 301 #include "ARMGenDisassemblerTables.inc" 302 #include "ARMGenInstrInfo.inc" 303 #include "ARMGenEDInfo.inc" 304 305 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 306 return new ARMDisassembler(STI); 307 } 308 309 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 310 return new ThumbDisassembler(STI); 311 } 312 313 EDInstInfo *ARMDisassembler::getEDInfo() const { 314 return instInfoARM; 315 } 316 317 EDInstInfo *ThumbDisassembler::getEDInfo() const { 318 return instInfoARM; 319 } 320 321 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 322 const MemoryObject &Region, 323 uint64_t Address, 324 raw_ostream &os) const { 325 uint8_t bytes[4]; 326 327 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 328 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 329 330 // We want to read exactly 4 bytes of data. 331 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 332 Size = 0; 333 return MCDisassembler::Fail; 334 } 335 336 // Encoded as a small-endian 32-bit word in the stream. 337 uint32_t insn = (bytes[3] << 24) | 338 (bytes[2] << 16) | 339 (bytes[1] << 8) | 340 (bytes[0] << 0); 341 342 // Calling the auto-generated decoder function. 343 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 344 if (result != MCDisassembler::Fail) { 345 Size = 4; 346 return result; 347 } 348 349 // VFP and NEON instructions, similarly, are shared between ARM 350 // and Thumb modes. 351 MI.clear(); 352 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 353 if (result != MCDisassembler::Fail) { 354 Size = 4; 355 return result; 356 } 357 358 MI.clear(); 359 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 360 if (result != MCDisassembler::Fail) { 361 Size = 4; 362 // Add a fake predicate operand, because we share these instruction 363 // definitions with Thumb2 where these instructions are predicable. 364 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 365 return MCDisassembler::Fail; 366 return result; 367 } 368 369 MI.clear(); 370 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 371 if (result != MCDisassembler::Fail) { 372 Size = 4; 373 // Add a fake predicate operand, because we share these instruction 374 // definitions with Thumb2 where these instructions are predicable. 375 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 376 return MCDisassembler::Fail; 377 return result; 378 } 379 380 MI.clear(); 381 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 382 if (result != MCDisassembler::Fail) { 383 Size = 4; 384 // Add a fake predicate operand, because we share these instruction 385 // definitions with Thumb2 where these instructions are predicable. 386 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 387 return MCDisassembler::Fail; 388 return result; 389 } 390 391 MI.clear(); 392 393 Size = 0; 394 return MCDisassembler::Fail; 395 } 396 397 namespace llvm { 398 extern MCInstrDesc ARMInsts[]; 399 } 400 401 // Thumb1 instructions don't have explicit S bits. Rather, they 402 // implicitly set CPSR. Since it's not represented in the encoding, the 403 // auto-generated decoder won't inject the CPSR operand. We need to fix 404 // that as a post-pass. 405 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 406 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 407 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 408 MCInst::iterator I = MI.begin(); 409 for (unsigned i = 0; i < NumOps; ++i, ++I) { 410 if (I == MI.end()) break; 411 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 412 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 413 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 414 return; 415 } 416 } 417 418 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 419 } 420 421 // Most Thumb instructions don't have explicit predicates in the 422 // encoding, but rather get their predicates from IT context. We need 423 // to fix up the predicate operands using this context information as a 424 // post-pass. 425 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 426 // A few instructions actually have predicates encoded in them. Don't 427 // try to overwrite it if we're seeing one of those. 428 switch (MI.getOpcode()) { 429 case ARM::tBcc: 430 case ARM::t2Bcc: 431 return; 432 default: 433 break; 434 } 435 436 // If we're in an IT block, base the predicate on that. Otherwise, 437 // assume a predicate of AL. 438 unsigned CC; 439 if (!ITBlock.empty()) { 440 CC = ITBlock.back(); 441 if (CC == 0xF) 442 CC = ARMCC::AL; 443 ITBlock.pop_back(); 444 } else 445 CC = ARMCC::AL; 446 447 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 448 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 449 MCInst::iterator I = MI.begin(); 450 for (unsigned i = 0; i < NumOps; ++i, ++I) { 451 if (I == MI.end()) break; 452 if (OpInfo[i].isPredicate()) { 453 I = MI.insert(I, MCOperand::CreateImm(CC)); 454 ++I; 455 if (CC == ARMCC::AL) 456 MI.insert(I, MCOperand::CreateReg(0)); 457 else 458 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 459 return; 460 } 461 } 462 463 I = MI.insert(I, MCOperand::CreateImm(CC)); 464 ++I; 465 if (CC == ARMCC::AL) 466 MI.insert(I, MCOperand::CreateReg(0)); 467 else 468 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 469 } 470 471 // Thumb VFP instructions are a special case. Because we share their 472 // encodings between ARM and Thumb modes, and they are predicable in ARM 473 // mode, the auto-generated decoder will give them an (incorrect) 474 // predicate operand. We need to rewrite these operands based on the IT 475 // context as a post-pass. 476 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 477 unsigned CC; 478 if (!ITBlock.empty()) { 479 CC = ITBlock.back(); 480 ITBlock.pop_back(); 481 } else 482 CC = ARMCC::AL; 483 484 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 485 MCInst::iterator I = MI.begin(); 486 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 487 for (unsigned i = 0; i < NumOps; ++i, ++I) { 488 if (OpInfo[i].isPredicate() ) { 489 I->setImm(CC); 490 ++I; 491 if (CC == ARMCC::AL) 492 I->setReg(0); 493 else 494 I->setReg(ARM::CPSR); 495 return; 496 } 497 } 498 } 499 500 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 501 const MemoryObject &Region, 502 uint64_t Address, 503 raw_ostream &os) const { 504 uint8_t bytes[4]; 505 506 assert((STI.getFeatureBits() & ARM::ModeThumb) && 507 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 508 509 // We want to read exactly 2 bytes of data. 510 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 511 Size = 0; 512 return MCDisassembler::Fail; 513 } 514 515 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 516 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 517 if (result != MCDisassembler::Fail) { 518 Size = 2; 519 AddThumbPredicate(MI); 520 return result; 521 } 522 523 MI.clear(); 524 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 525 if (result) { 526 Size = 2; 527 bool InITBlock = !ITBlock.empty(); 528 AddThumbPredicate(MI); 529 AddThumb1SBit(MI, InITBlock); 530 return result; 531 } 532 533 MI.clear(); 534 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 535 if (result != MCDisassembler::Fail) { 536 Size = 2; 537 AddThumbPredicate(MI); 538 539 // If we find an IT instruction, we need to parse its condition 540 // code and mask operands so that we can apply them correctly 541 // to the subsequent instructions. 542 if (MI.getOpcode() == ARM::t2IT) { 543 // (3 - the number of trailing zeros) is the number of then / else. 544 unsigned firstcond = MI.getOperand(0).getImm(); 545 unsigned Mask = MI.getOperand(1).getImm(); 546 unsigned CondBit0 = Mask >> 4 & 1; 547 unsigned NumTZ = CountTrailingZeros_32(Mask); 548 assert(NumTZ <= 3 && "Invalid IT mask!"); 549 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 550 bool T = ((Mask >> Pos) & 1) == CondBit0; 551 if (T) 552 ITBlock.insert(ITBlock.begin(), firstcond); 553 else 554 ITBlock.insert(ITBlock.begin(), firstcond ^ 1); 555 } 556 557 ITBlock.push_back(firstcond); 558 } 559 560 return result; 561 } 562 563 // We want to read exactly 4 bytes of data. 564 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 565 Size = 0; 566 return MCDisassembler::Fail; 567 } 568 569 uint32_t insn32 = (bytes[3] << 8) | 570 (bytes[2] << 0) | 571 (bytes[1] << 24) | 572 (bytes[0] << 16); 573 MI.clear(); 574 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 575 if (result != MCDisassembler::Fail) { 576 Size = 4; 577 bool InITBlock = ITBlock.size(); 578 AddThumbPredicate(MI); 579 AddThumb1SBit(MI, InITBlock); 580 return result; 581 } 582 583 MI.clear(); 584 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 585 if (result != MCDisassembler::Fail) { 586 Size = 4; 587 AddThumbPredicate(MI); 588 return result; 589 } 590 591 MI.clear(); 592 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 593 if (result != MCDisassembler::Fail) { 594 Size = 4; 595 UpdateThumbVFPPredicate(MI); 596 return result; 597 } 598 599 MI.clear(); 600 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 601 if (result != MCDisassembler::Fail) { 602 Size = 4; 603 AddThumbPredicate(MI); 604 return result; 605 } 606 607 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 608 MI.clear(); 609 uint32_t NEONLdStInsn = insn32; 610 NEONLdStInsn &= 0xF0FFFFFF; 611 NEONLdStInsn |= 0x04000000; 612 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 613 if (result != MCDisassembler::Fail) { 614 Size = 4; 615 AddThumbPredicate(MI); 616 return result; 617 } 618 } 619 620 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 621 MI.clear(); 622 uint32_t NEONDataInsn = insn32; 623 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 624 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 625 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 626 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 627 if (result != MCDisassembler::Fail) { 628 Size = 4; 629 AddThumbPredicate(MI); 630 return result; 631 } 632 } 633 634 Size = 0; 635 return MCDisassembler::Fail; 636 } 637 638 639 extern "C" void LLVMInitializeARMDisassembler() { 640 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 641 createARMDisassembler); 642 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 643 createThumbDisassembler); 644 } 645 646 static const unsigned GPRDecoderTable[] = { 647 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 648 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 649 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 650 ARM::R12, ARM::SP, ARM::LR, ARM::PC 651 }; 652 653 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 654 uint64_t Address, const void *Decoder) { 655 if (RegNo > 15) 656 return MCDisassembler::Fail; 657 658 unsigned Register = GPRDecoderTable[RegNo]; 659 Inst.addOperand(MCOperand::CreateReg(Register)); 660 return MCDisassembler::Success; 661 } 662 663 static DecodeStatus 664 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 665 uint64_t Address, const void *Decoder) { 666 if (RegNo == 15) return MCDisassembler::Fail; 667 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 668 } 669 670 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 671 uint64_t Address, const void *Decoder) { 672 if (RegNo > 7) 673 return MCDisassembler::Fail; 674 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 675 } 676 677 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 678 uint64_t Address, const void *Decoder) { 679 unsigned Register = 0; 680 switch (RegNo) { 681 case 0: 682 Register = ARM::R0; 683 break; 684 case 1: 685 Register = ARM::R1; 686 break; 687 case 2: 688 Register = ARM::R2; 689 break; 690 case 3: 691 Register = ARM::R3; 692 break; 693 case 9: 694 Register = ARM::R9; 695 break; 696 case 12: 697 Register = ARM::R12; 698 break; 699 default: 700 return MCDisassembler::Fail; 701 } 702 703 Inst.addOperand(MCOperand::CreateReg(Register)); 704 return MCDisassembler::Success; 705 } 706 707 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 708 uint64_t Address, const void *Decoder) { 709 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 710 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 711 } 712 713 static const unsigned SPRDecoderTable[] = { 714 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 715 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 716 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 717 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 718 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 719 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 720 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 721 ARM::S28, ARM::S29, ARM::S30, ARM::S31 722 }; 723 724 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 725 uint64_t Address, const void *Decoder) { 726 if (RegNo > 31) 727 return MCDisassembler::Fail; 728 729 unsigned Register = SPRDecoderTable[RegNo]; 730 Inst.addOperand(MCOperand::CreateReg(Register)); 731 return MCDisassembler::Success; 732 } 733 734 static const unsigned DPRDecoderTable[] = { 735 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 736 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 737 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 738 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 739 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 740 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 741 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 742 ARM::D28, ARM::D29, ARM::D30, ARM::D31 743 }; 744 745 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 746 uint64_t Address, const void *Decoder) { 747 if (RegNo > 31) 748 return MCDisassembler::Fail; 749 750 unsigned Register = DPRDecoderTable[RegNo]; 751 Inst.addOperand(MCOperand::CreateReg(Register)); 752 return MCDisassembler::Success; 753 } 754 755 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 756 uint64_t Address, const void *Decoder) { 757 if (RegNo > 7) 758 return MCDisassembler::Fail; 759 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 760 } 761 762 static DecodeStatus 763 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 764 uint64_t Address, const void *Decoder) { 765 if (RegNo > 15) 766 return MCDisassembler::Fail; 767 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 768 } 769 770 static const unsigned QPRDecoderTable[] = { 771 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 772 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 773 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 774 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 775 }; 776 777 778 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 779 uint64_t Address, const void *Decoder) { 780 if (RegNo > 31) 781 return MCDisassembler::Fail; 782 RegNo >>= 1; 783 784 unsigned Register = QPRDecoderTable[RegNo]; 785 Inst.addOperand(MCOperand::CreateReg(Register)); 786 return MCDisassembler::Success; 787 } 788 789 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 790 uint64_t Address, const void *Decoder) { 791 if (Val == 0xF) return MCDisassembler::Fail; 792 // AL predicate is not allowed on Thumb1 branches. 793 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 794 return MCDisassembler::Fail; 795 Inst.addOperand(MCOperand::CreateImm(Val)); 796 if (Val == ARMCC::AL) { 797 Inst.addOperand(MCOperand::CreateReg(0)); 798 } else 799 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 800 return MCDisassembler::Success; 801 } 802 803 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 804 uint64_t Address, const void *Decoder) { 805 if (Val) 806 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 807 else 808 Inst.addOperand(MCOperand::CreateReg(0)); 809 return MCDisassembler::Success; 810 } 811 812 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 813 uint64_t Address, const void *Decoder) { 814 uint32_t imm = Val & 0xFF; 815 uint32_t rot = (Val & 0xF00) >> 7; 816 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 817 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 818 return MCDisassembler::Success; 819 } 820 821 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 822 uint64_t Address, const void *Decoder) { 823 DecodeStatus S = MCDisassembler::Success; 824 825 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 826 unsigned type = fieldFromInstruction32(Val, 5, 2); 827 unsigned imm = fieldFromInstruction32(Val, 7, 5); 828 829 // Register-immediate 830 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 831 return MCDisassembler::Fail; 832 833 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 834 switch (type) { 835 case 0: 836 Shift = ARM_AM::lsl; 837 break; 838 case 1: 839 Shift = ARM_AM::lsr; 840 break; 841 case 2: 842 Shift = ARM_AM::asr; 843 break; 844 case 3: 845 Shift = ARM_AM::ror; 846 break; 847 } 848 849 if (Shift == ARM_AM::ror && imm == 0) 850 Shift = ARM_AM::rrx; 851 852 unsigned Op = Shift | (imm << 3); 853 Inst.addOperand(MCOperand::CreateImm(Op)); 854 855 return S; 856 } 857 858 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 859 uint64_t Address, const void *Decoder) { 860 DecodeStatus S = MCDisassembler::Success; 861 862 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 863 unsigned type = fieldFromInstruction32(Val, 5, 2); 864 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 865 866 // Register-register 867 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 868 return MCDisassembler::Fail; 869 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 870 return MCDisassembler::Fail; 871 872 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 873 switch (type) { 874 case 0: 875 Shift = ARM_AM::lsl; 876 break; 877 case 1: 878 Shift = ARM_AM::lsr; 879 break; 880 case 2: 881 Shift = ARM_AM::asr; 882 break; 883 case 3: 884 Shift = ARM_AM::ror; 885 break; 886 } 887 888 Inst.addOperand(MCOperand::CreateImm(Shift)); 889 890 return S; 891 } 892 893 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 894 uint64_t Address, const void *Decoder) { 895 DecodeStatus S = MCDisassembler::Success; 896 897 // Empty register lists are not allowed. 898 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 899 for (unsigned i = 0; i < 16; ++i) { 900 if (Val & (1 << i)) { 901 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 902 return MCDisassembler::Fail; 903 } 904 } 905 906 return S; 907 } 908 909 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 910 uint64_t Address, const void *Decoder) { 911 DecodeStatus S = MCDisassembler::Success; 912 913 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 914 unsigned regs = Val & 0xFF; 915 916 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 917 return MCDisassembler::Fail; 918 for (unsigned i = 0; i < (regs - 1); ++i) { 919 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 920 return MCDisassembler::Fail; 921 } 922 923 return S; 924 } 925 926 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 927 uint64_t Address, const void *Decoder) { 928 DecodeStatus S = MCDisassembler::Success; 929 930 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 931 unsigned regs = (Val & 0xFF) / 2; 932 933 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 934 return MCDisassembler::Fail; 935 for (unsigned i = 0; i < (regs - 1); ++i) { 936 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 937 return MCDisassembler::Fail; 938 } 939 940 return S; 941 } 942 943 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 944 uint64_t Address, const void *Decoder) { 945 // This operand encodes a mask of contiguous zeros between a specified MSB 946 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 947 // the mask of all bits LSB-and-lower, and then xor them to create 948 // the mask of that's all ones on [msb, lsb]. Finally we not it to 949 // create the final mask. 950 unsigned msb = fieldFromInstruction32(Val, 5, 5); 951 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 952 uint32_t msb_mask = (1 << (msb+1)) - 1; 953 uint32_t lsb_mask = (1 << lsb) - 1; 954 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 955 return MCDisassembler::Success; 956 } 957 958 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 959 uint64_t Address, const void *Decoder) { 960 DecodeStatus S = MCDisassembler::Success; 961 962 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 963 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 964 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 965 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 966 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 967 unsigned U = fieldFromInstruction32(Insn, 23, 1); 968 969 switch (Inst.getOpcode()) { 970 case ARM::LDC_OFFSET: 971 case ARM::LDC_PRE: 972 case ARM::LDC_POST: 973 case ARM::LDC_OPTION: 974 case ARM::LDCL_OFFSET: 975 case ARM::LDCL_PRE: 976 case ARM::LDCL_POST: 977 case ARM::LDCL_OPTION: 978 case ARM::STC_OFFSET: 979 case ARM::STC_PRE: 980 case ARM::STC_POST: 981 case ARM::STC_OPTION: 982 case ARM::STCL_OFFSET: 983 case ARM::STCL_PRE: 984 case ARM::STCL_POST: 985 case ARM::STCL_OPTION: 986 case ARM::t2LDC_OFFSET: 987 case ARM::t2LDC_PRE: 988 case ARM::t2LDC_POST: 989 case ARM::t2LDC_OPTION: 990 case ARM::t2LDCL_OFFSET: 991 case ARM::t2LDCL_PRE: 992 case ARM::t2LDCL_POST: 993 case ARM::t2LDCL_OPTION: 994 case ARM::t2STC_OFFSET: 995 case ARM::t2STC_PRE: 996 case ARM::t2STC_POST: 997 case ARM::t2STC_OPTION: 998 case ARM::t2STCL_OFFSET: 999 case ARM::t2STCL_PRE: 1000 case ARM::t2STCL_POST: 1001 case ARM::t2STCL_OPTION: 1002 if (coproc == 0xA || coproc == 0xB) 1003 return MCDisassembler::Fail; 1004 break; 1005 default: 1006 break; 1007 } 1008 1009 Inst.addOperand(MCOperand::CreateImm(coproc)); 1010 Inst.addOperand(MCOperand::CreateImm(CRd)); 1011 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1012 return MCDisassembler::Fail; 1013 switch (Inst.getOpcode()) { 1014 case ARM::LDC_OPTION: 1015 case ARM::LDCL_OPTION: 1016 case ARM::LDC2_OPTION: 1017 case ARM::LDC2L_OPTION: 1018 case ARM::STC_OPTION: 1019 case ARM::STCL_OPTION: 1020 case ARM::STC2_OPTION: 1021 case ARM::STC2L_OPTION: 1022 case ARM::LDCL_POST: 1023 case ARM::STCL_POST: 1024 case ARM::LDC2L_POST: 1025 case ARM::STC2L_POST: 1026 case ARM::t2LDC_OPTION: 1027 case ARM::t2LDCL_OPTION: 1028 case ARM::t2STC_OPTION: 1029 case ARM::t2STCL_OPTION: 1030 case ARM::t2LDCL_POST: 1031 case ARM::t2STCL_POST: 1032 break; 1033 default: 1034 Inst.addOperand(MCOperand::CreateReg(0)); 1035 break; 1036 } 1037 1038 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1039 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1040 1041 bool writeback = (P == 0) || (W == 1); 1042 unsigned idx_mode = 0; 1043 if (P && writeback) 1044 idx_mode = ARMII::IndexModePre; 1045 else if (!P && writeback) 1046 idx_mode = ARMII::IndexModePost; 1047 1048 switch (Inst.getOpcode()) { 1049 case ARM::LDCL_POST: 1050 case ARM::STCL_POST: 1051 case ARM::t2LDCL_POST: 1052 case ARM::t2STCL_POST: 1053 case ARM::LDC2L_POST: 1054 case ARM::STC2L_POST: 1055 imm |= U << 8; 1056 case ARM::LDC_OPTION: 1057 case ARM::LDCL_OPTION: 1058 case ARM::LDC2_OPTION: 1059 case ARM::LDC2L_OPTION: 1060 case ARM::STC_OPTION: 1061 case ARM::STCL_OPTION: 1062 case ARM::STC2_OPTION: 1063 case ARM::STC2L_OPTION: 1064 case ARM::t2LDC_OPTION: 1065 case ARM::t2LDCL_OPTION: 1066 case ARM::t2STC_OPTION: 1067 case ARM::t2STCL_OPTION: 1068 Inst.addOperand(MCOperand::CreateImm(imm)); 1069 break; 1070 default: 1071 if (U) 1072 Inst.addOperand(MCOperand::CreateImm( 1073 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 1074 else 1075 Inst.addOperand(MCOperand::CreateImm( 1076 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 1077 break; 1078 } 1079 1080 switch (Inst.getOpcode()) { 1081 case ARM::LDC_OFFSET: 1082 case ARM::LDC_PRE: 1083 case ARM::LDC_POST: 1084 case ARM::LDC_OPTION: 1085 case ARM::LDCL_OFFSET: 1086 case ARM::LDCL_PRE: 1087 case ARM::LDCL_POST: 1088 case ARM::LDCL_OPTION: 1089 case ARM::STC_OFFSET: 1090 case ARM::STC_PRE: 1091 case ARM::STC_POST: 1092 case ARM::STC_OPTION: 1093 case ARM::STCL_OFFSET: 1094 case ARM::STCL_PRE: 1095 case ARM::STCL_POST: 1096 case ARM::STCL_OPTION: 1097 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1098 return MCDisassembler::Fail; 1099 break; 1100 default: 1101 break; 1102 } 1103 1104 return S; 1105 } 1106 1107 static DecodeStatus 1108 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 1109 uint64_t Address, const void *Decoder) { 1110 DecodeStatus S = MCDisassembler::Success; 1111 1112 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1113 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1114 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1115 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1116 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1117 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1118 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1119 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1120 1121 // On stores, the writeback operand precedes Rt. 1122 switch (Inst.getOpcode()) { 1123 case ARM::STR_POST_IMM: 1124 case ARM::STR_POST_REG: 1125 case ARM::STRB_POST_IMM: 1126 case ARM::STRB_POST_REG: 1127 case ARM::STRT_POST_REG: 1128 case ARM::STRT_POST_IMM: 1129 case ARM::STRBT_POST_REG: 1130 case ARM::STRBT_POST_IMM: 1131 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1132 return MCDisassembler::Fail; 1133 break; 1134 default: 1135 break; 1136 } 1137 1138 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1139 return MCDisassembler::Fail; 1140 1141 // On loads, the writeback operand comes after Rt. 1142 switch (Inst.getOpcode()) { 1143 case ARM::LDR_POST_IMM: 1144 case ARM::LDR_POST_REG: 1145 case ARM::LDRB_POST_IMM: 1146 case ARM::LDRB_POST_REG: 1147 case ARM::LDRBT_POST_REG: 1148 case ARM::LDRBT_POST_IMM: 1149 case ARM::LDRT_POST_REG: 1150 case ARM::LDRT_POST_IMM: 1151 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1152 return MCDisassembler::Fail; 1153 break; 1154 default: 1155 break; 1156 } 1157 1158 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1159 return MCDisassembler::Fail; 1160 1161 ARM_AM::AddrOpc Op = ARM_AM::add; 1162 if (!fieldFromInstruction32(Insn, 23, 1)) 1163 Op = ARM_AM::sub; 1164 1165 bool writeback = (P == 0) || (W == 1); 1166 unsigned idx_mode = 0; 1167 if (P && writeback) 1168 idx_mode = ARMII::IndexModePre; 1169 else if (!P && writeback) 1170 idx_mode = ARMII::IndexModePost; 1171 1172 if (writeback && (Rn == 15 || Rn == Rt)) 1173 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1174 1175 if (reg) { 1176 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1177 return MCDisassembler::Fail; 1178 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1179 switch( fieldFromInstruction32(Insn, 5, 2)) { 1180 case 0: 1181 Opc = ARM_AM::lsl; 1182 break; 1183 case 1: 1184 Opc = ARM_AM::lsr; 1185 break; 1186 case 2: 1187 Opc = ARM_AM::asr; 1188 break; 1189 case 3: 1190 Opc = ARM_AM::ror; 1191 break; 1192 default: 1193 return MCDisassembler::Fail; 1194 } 1195 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1196 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1197 1198 Inst.addOperand(MCOperand::CreateImm(imm)); 1199 } else { 1200 Inst.addOperand(MCOperand::CreateReg(0)); 1201 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1202 Inst.addOperand(MCOperand::CreateImm(tmp)); 1203 } 1204 1205 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1206 return MCDisassembler::Fail; 1207 1208 return S; 1209 } 1210 1211 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1212 uint64_t Address, const void *Decoder) { 1213 DecodeStatus S = MCDisassembler::Success; 1214 1215 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1216 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1217 unsigned type = fieldFromInstruction32(Val, 5, 2); 1218 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1219 unsigned U = fieldFromInstruction32(Val, 12, 1); 1220 1221 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1222 switch (type) { 1223 case 0: 1224 ShOp = ARM_AM::lsl; 1225 break; 1226 case 1: 1227 ShOp = ARM_AM::lsr; 1228 break; 1229 case 2: 1230 ShOp = ARM_AM::asr; 1231 break; 1232 case 3: 1233 ShOp = ARM_AM::ror; 1234 break; 1235 } 1236 1237 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1238 return MCDisassembler::Fail; 1239 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1240 return MCDisassembler::Fail; 1241 unsigned shift; 1242 if (U) 1243 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1244 else 1245 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1246 Inst.addOperand(MCOperand::CreateImm(shift)); 1247 1248 return S; 1249 } 1250 1251 static DecodeStatus 1252 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1253 uint64_t Address, const void *Decoder) { 1254 DecodeStatus S = MCDisassembler::Success; 1255 1256 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1257 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1258 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1259 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1260 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1261 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1262 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1263 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1264 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1265 1266 bool writeback = (W == 1) | (P == 0); 1267 1268 // For {LD,ST}RD, Rt must be even, else undefined. 1269 switch (Inst.getOpcode()) { 1270 case ARM::STRD: 1271 case ARM::STRD_PRE: 1272 case ARM::STRD_POST: 1273 case ARM::LDRD: 1274 case ARM::LDRD_PRE: 1275 case ARM::LDRD_POST: 1276 if (Rt & 0x1) return MCDisassembler::Fail; 1277 break; 1278 default: 1279 break; 1280 } 1281 1282 if (writeback) { // Writeback 1283 if (P) 1284 U |= ARMII::IndexModePre << 9; 1285 else 1286 U |= ARMII::IndexModePost << 9; 1287 1288 // On stores, the writeback operand precedes Rt. 1289 switch (Inst.getOpcode()) { 1290 case ARM::STRD: 1291 case ARM::STRD_PRE: 1292 case ARM::STRD_POST: 1293 case ARM::STRH: 1294 case ARM::STRH_PRE: 1295 case ARM::STRH_POST: 1296 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1297 return MCDisassembler::Fail; 1298 break; 1299 default: 1300 break; 1301 } 1302 } 1303 1304 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1305 return MCDisassembler::Fail; 1306 switch (Inst.getOpcode()) { 1307 case ARM::STRD: 1308 case ARM::STRD_PRE: 1309 case ARM::STRD_POST: 1310 case ARM::LDRD: 1311 case ARM::LDRD_PRE: 1312 case ARM::LDRD_POST: 1313 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1314 return MCDisassembler::Fail; 1315 break; 1316 default: 1317 break; 1318 } 1319 1320 if (writeback) { 1321 // On loads, the writeback operand comes after Rt. 1322 switch (Inst.getOpcode()) { 1323 case ARM::LDRD: 1324 case ARM::LDRD_PRE: 1325 case ARM::LDRD_POST: 1326 case ARM::LDRH: 1327 case ARM::LDRH_PRE: 1328 case ARM::LDRH_POST: 1329 case ARM::LDRSH: 1330 case ARM::LDRSH_PRE: 1331 case ARM::LDRSH_POST: 1332 case ARM::LDRSB: 1333 case ARM::LDRSB_PRE: 1334 case ARM::LDRSB_POST: 1335 case ARM::LDRHTr: 1336 case ARM::LDRSBTr: 1337 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1338 return MCDisassembler::Fail; 1339 break; 1340 default: 1341 break; 1342 } 1343 } 1344 1345 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1346 return MCDisassembler::Fail; 1347 1348 if (type) { 1349 Inst.addOperand(MCOperand::CreateReg(0)); 1350 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1351 } else { 1352 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1353 return MCDisassembler::Fail; 1354 Inst.addOperand(MCOperand::CreateImm(U)); 1355 } 1356 1357 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1358 return MCDisassembler::Fail; 1359 1360 return S; 1361 } 1362 1363 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1364 uint64_t Address, const void *Decoder) { 1365 DecodeStatus S = MCDisassembler::Success; 1366 1367 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1368 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1369 1370 switch (mode) { 1371 case 0: 1372 mode = ARM_AM::da; 1373 break; 1374 case 1: 1375 mode = ARM_AM::ia; 1376 break; 1377 case 2: 1378 mode = ARM_AM::db; 1379 break; 1380 case 3: 1381 mode = ARM_AM::ib; 1382 break; 1383 } 1384 1385 Inst.addOperand(MCOperand::CreateImm(mode)); 1386 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1387 return MCDisassembler::Fail; 1388 1389 return S; 1390 } 1391 1392 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1393 unsigned Insn, 1394 uint64_t Address, const void *Decoder) { 1395 DecodeStatus S = MCDisassembler::Success; 1396 1397 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1398 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1399 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1400 1401 if (pred == 0xF) { 1402 switch (Inst.getOpcode()) { 1403 case ARM::LDMDA: 1404 Inst.setOpcode(ARM::RFEDA); 1405 break; 1406 case ARM::LDMDA_UPD: 1407 Inst.setOpcode(ARM::RFEDA_UPD); 1408 break; 1409 case ARM::LDMDB: 1410 Inst.setOpcode(ARM::RFEDB); 1411 break; 1412 case ARM::LDMDB_UPD: 1413 Inst.setOpcode(ARM::RFEDB_UPD); 1414 break; 1415 case ARM::LDMIA: 1416 Inst.setOpcode(ARM::RFEIA); 1417 break; 1418 case ARM::LDMIA_UPD: 1419 Inst.setOpcode(ARM::RFEIA_UPD); 1420 break; 1421 case ARM::LDMIB: 1422 Inst.setOpcode(ARM::RFEIB); 1423 break; 1424 case ARM::LDMIB_UPD: 1425 Inst.setOpcode(ARM::RFEIB_UPD); 1426 break; 1427 case ARM::STMDA: 1428 Inst.setOpcode(ARM::SRSDA); 1429 break; 1430 case ARM::STMDA_UPD: 1431 Inst.setOpcode(ARM::SRSDA_UPD); 1432 break; 1433 case ARM::STMDB: 1434 Inst.setOpcode(ARM::SRSDB); 1435 break; 1436 case ARM::STMDB_UPD: 1437 Inst.setOpcode(ARM::SRSDB_UPD); 1438 break; 1439 case ARM::STMIA: 1440 Inst.setOpcode(ARM::SRSIA); 1441 break; 1442 case ARM::STMIA_UPD: 1443 Inst.setOpcode(ARM::SRSIA_UPD); 1444 break; 1445 case ARM::STMIB: 1446 Inst.setOpcode(ARM::SRSIB); 1447 break; 1448 case ARM::STMIB_UPD: 1449 Inst.setOpcode(ARM::SRSIB_UPD); 1450 break; 1451 default: 1452 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1453 } 1454 1455 // For stores (which become SRS's, the only operand is the mode. 1456 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1457 Inst.addOperand( 1458 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1459 return S; 1460 } 1461 1462 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1463 } 1464 1465 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1466 return MCDisassembler::Fail; 1467 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1468 return MCDisassembler::Fail; // Tied 1469 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1470 return MCDisassembler::Fail; 1471 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1472 return MCDisassembler::Fail; 1473 1474 return S; 1475 } 1476 1477 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1478 uint64_t Address, const void *Decoder) { 1479 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1480 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1481 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1482 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1483 1484 DecodeStatus S = MCDisassembler::Success; 1485 1486 // imod == '01' --> UNPREDICTABLE 1487 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1488 // return failure here. The '01' imod value is unprintable, so there's 1489 // nothing useful we could do even if we returned UNPREDICTABLE. 1490 1491 if (imod == 1) return MCDisassembler::Fail; 1492 1493 if (imod && M) { 1494 Inst.setOpcode(ARM::CPS3p); 1495 Inst.addOperand(MCOperand::CreateImm(imod)); 1496 Inst.addOperand(MCOperand::CreateImm(iflags)); 1497 Inst.addOperand(MCOperand::CreateImm(mode)); 1498 } else if (imod && !M) { 1499 Inst.setOpcode(ARM::CPS2p); 1500 Inst.addOperand(MCOperand::CreateImm(imod)); 1501 Inst.addOperand(MCOperand::CreateImm(iflags)); 1502 if (mode) S = MCDisassembler::SoftFail; 1503 } else if (!imod && M) { 1504 Inst.setOpcode(ARM::CPS1p); 1505 Inst.addOperand(MCOperand::CreateImm(mode)); 1506 if (iflags) S = MCDisassembler::SoftFail; 1507 } else { 1508 // imod == '00' && M == '0' --> UNPREDICTABLE 1509 Inst.setOpcode(ARM::CPS1p); 1510 Inst.addOperand(MCOperand::CreateImm(mode)); 1511 S = MCDisassembler::SoftFail; 1512 } 1513 1514 return S; 1515 } 1516 1517 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1518 uint64_t Address, const void *Decoder) { 1519 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1520 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1521 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1522 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1523 1524 DecodeStatus S = MCDisassembler::Success; 1525 1526 // imod == '01' --> UNPREDICTABLE 1527 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1528 // return failure here. The '01' imod value is unprintable, so there's 1529 // nothing useful we could do even if we returned UNPREDICTABLE. 1530 1531 if (imod == 1) return MCDisassembler::Fail; 1532 1533 if (imod && M) { 1534 Inst.setOpcode(ARM::t2CPS3p); 1535 Inst.addOperand(MCOperand::CreateImm(imod)); 1536 Inst.addOperand(MCOperand::CreateImm(iflags)); 1537 Inst.addOperand(MCOperand::CreateImm(mode)); 1538 } else if (imod && !M) { 1539 Inst.setOpcode(ARM::t2CPS2p); 1540 Inst.addOperand(MCOperand::CreateImm(imod)); 1541 Inst.addOperand(MCOperand::CreateImm(iflags)); 1542 if (mode) S = MCDisassembler::SoftFail; 1543 } else if (!imod && M) { 1544 Inst.setOpcode(ARM::t2CPS1p); 1545 Inst.addOperand(MCOperand::CreateImm(mode)); 1546 if (iflags) S = MCDisassembler::SoftFail; 1547 } else { 1548 // imod == '00' && M == '0' --> UNPREDICTABLE 1549 Inst.setOpcode(ARM::t2CPS1p); 1550 Inst.addOperand(MCOperand::CreateImm(mode)); 1551 S = MCDisassembler::SoftFail; 1552 } 1553 1554 return S; 1555 } 1556 1557 1558 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1559 uint64_t Address, const void *Decoder) { 1560 DecodeStatus S = MCDisassembler::Success; 1561 1562 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1563 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1564 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1565 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1566 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1567 1568 if (pred == 0xF) 1569 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1570 1571 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1572 return MCDisassembler::Fail; 1573 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1574 return MCDisassembler::Fail; 1575 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1576 return MCDisassembler::Fail; 1577 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1578 return MCDisassembler::Fail; 1579 1580 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1581 return MCDisassembler::Fail; 1582 1583 return S; 1584 } 1585 1586 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1587 uint64_t Address, const void *Decoder) { 1588 DecodeStatus S = MCDisassembler::Success; 1589 1590 unsigned add = fieldFromInstruction32(Val, 12, 1); 1591 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1592 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1593 1594 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1595 return MCDisassembler::Fail; 1596 1597 if (!add) imm *= -1; 1598 if (imm == 0 && !add) imm = INT32_MIN; 1599 Inst.addOperand(MCOperand::CreateImm(imm)); 1600 1601 return S; 1602 } 1603 1604 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1605 uint64_t Address, const void *Decoder) { 1606 DecodeStatus S = MCDisassembler::Success; 1607 1608 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1609 unsigned U = fieldFromInstruction32(Val, 8, 1); 1610 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1611 1612 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1613 return MCDisassembler::Fail; 1614 1615 if (U) 1616 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1617 else 1618 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1619 1620 return S; 1621 } 1622 1623 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1624 uint64_t Address, const void *Decoder) { 1625 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1626 } 1627 1628 static DecodeStatus 1629 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1630 uint64_t Address, const void *Decoder) { 1631 DecodeStatus S = MCDisassembler::Success; 1632 1633 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1634 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1635 1636 if (pred == 0xF) { 1637 Inst.setOpcode(ARM::BLXi); 1638 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1639 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1640 return S; 1641 } 1642 1643 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1644 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1645 return MCDisassembler::Fail; 1646 1647 return S; 1648 } 1649 1650 1651 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1652 uint64_t Address, const void *Decoder) { 1653 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1654 return MCDisassembler::Success; 1655 } 1656 1657 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1658 uint64_t Address, const void *Decoder) { 1659 DecodeStatus S = MCDisassembler::Success; 1660 1661 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1662 unsigned align = fieldFromInstruction32(Val, 4, 2); 1663 1664 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1665 return MCDisassembler::Fail; 1666 if (!align) 1667 Inst.addOperand(MCOperand::CreateImm(0)); 1668 else 1669 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1670 1671 return S; 1672 } 1673 1674 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1675 uint64_t Address, const void *Decoder) { 1676 DecodeStatus S = MCDisassembler::Success; 1677 1678 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1679 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1680 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1681 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1682 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1683 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1684 1685 // First output register 1686 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 1687 return MCDisassembler::Fail; 1688 1689 // Second output register 1690 switch (Inst.getOpcode()) { 1691 case ARM::VLD1q8: 1692 case ARM::VLD1q16: 1693 case ARM::VLD1q32: 1694 case ARM::VLD1q64: 1695 case ARM::VLD1q8_UPD: 1696 case ARM::VLD1q16_UPD: 1697 case ARM::VLD1q32_UPD: 1698 case ARM::VLD1q64_UPD: 1699 case ARM::VLD1d8T: 1700 case ARM::VLD1d16T: 1701 case ARM::VLD1d32T: 1702 case ARM::VLD1d64T: 1703 case ARM::VLD1d8T_UPD: 1704 case ARM::VLD1d16T_UPD: 1705 case ARM::VLD1d32T_UPD: 1706 case ARM::VLD1d64T_UPD: 1707 case ARM::VLD1d8Q: 1708 case ARM::VLD1d16Q: 1709 case ARM::VLD1d32Q: 1710 case ARM::VLD1d64Q: 1711 case ARM::VLD1d8Q_UPD: 1712 case ARM::VLD1d16Q_UPD: 1713 case ARM::VLD1d32Q_UPD: 1714 case ARM::VLD1d64Q_UPD: 1715 case ARM::VLD2d8: 1716 case ARM::VLD2d16: 1717 case ARM::VLD2d32: 1718 case ARM::VLD2d8_UPD: 1719 case ARM::VLD2d16_UPD: 1720 case ARM::VLD2d32_UPD: 1721 case ARM::VLD2q8: 1722 case ARM::VLD2q16: 1723 case ARM::VLD2q32: 1724 case ARM::VLD2q8_UPD: 1725 case ARM::VLD2q16_UPD: 1726 case ARM::VLD2q32_UPD: 1727 case ARM::VLD3d8: 1728 case ARM::VLD3d16: 1729 case ARM::VLD3d32: 1730 case ARM::VLD3d8_UPD: 1731 case ARM::VLD3d16_UPD: 1732 case ARM::VLD3d32_UPD: 1733 case ARM::VLD4d8: 1734 case ARM::VLD4d16: 1735 case ARM::VLD4d32: 1736 case ARM::VLD4d8_UPD: 1737 case ARM::VLD4d16_UPD: 1738 case ARM::VLD4d32_UPD: 1739 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 1740 return MCDisassembler::Fail; 1741 break; 1742 case ARM::VLD2b8: 1743 case ARM::VLD2b16: 1744 case ARM::VLD2b32: 1745 case ARM::VLD2b8_UPD: 1746 case ARM::VLD2b16_UPD: 1747 case ARM::VLD2b32_UPD: 1748 case ARM::VLD3q8: 1749 case ARM::VLD3q16: 1750 case ARM::VLD3q32: 1751 case ARM::VLD3q8_UPD: 1752 case ARM::VLD3q16_UPD: 1753 case ARM::VLD3q32_UPD: 1754 case ARM::VLD4q8: 1755 case ARM::VLD4q16: 1756 case ARM::VLD4q32: 1757 case ARM::VLD4q8_UPD: 1758 case ARM::VLD4q16_UPD: 1759 case ARM::VLD4q32_UPD: 1760 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1761 return MCDisassembler::Fail; 1762 default: 1763 break; 1764 } 1765 1766 // Third output register 1767 switch(Inst.getOpcode()) { 1768 case ARM::VLD1d8T: 1769 case ARM::VLD1d16T: 1770 case ARM::VLD1d32T: 1771 case ARM::VLD1d64T: 1772 case ARM::VLD1d8T_UPD: 1773 case ARM::VLD1d16T_UPD: 1774 case ARM::VLD1d32T_UPD: 1775 case ARM::VLD1d64T_UPD: 1776 case ARM::VLD1d8Q: 1777 case ARM::VLD1d16Q: 1778 case ARM::VLD1d32Q: 1779 case ARM::VLD1d64Q: 1780 case ARM::VLD1d8Q_UPD: 1781 case ARM::VLD1d16Q_UPD: 1782 case ARM::VLD1d32Q_UPD: 1783 case ARM::VLD1d64Q_UPD: 1784 case ARM::VLD2q8: 1785 case ARM::VLD2q16: 1786 case ARM::VLD2q32: 1787 case ARM::VLD2q8_UPD: 1788 case ARM::VLD2q16_UPD: 1789 case ARM::VLD2q32_UPD: 1790 case ARM::VLD3d8: 1791 case ARM::VLD3d16: 1792 case ARM::VLD3d32: 1793 case ARM::VLD3d8_UPD: 1794 case ARM::VLD3d16_UPD: 1795 case ARM::VLD3d32_UPD: 1796 case ARM::VLD4d8: 1797 case ARM::VLD4d16: 1798 case ARM::VLD4d32: 1799 case ARM::VLD4d8_UPD: 1800 case ARM::VLD4d16_UPD: 1801 case ARM::VLD4d32_UPD: 1802 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1803 return MCDisassembler::Fail; 1804 break; 1805 case ARM::VLD3q8: 1806 case ARM::VLD3q16: 1807 case ARM::VLD3q32: 1808 case ARM::VLD3q8_UPD: 1809 case ARM::VLD3q16_UPD: 1810 case ARM::VLD3q32_UPD: 1811 case ARM::VLD4q8: 1812 case ARM::VLD4q16: 1813 case ARM::VLD4q32: 1814 case ARM::VLD4q8_UPD: 1815 case ARM::VLD4q16_UPD: 1816 case ARM::VLD4q32_UPD: 1817 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 1818 return MCDisassembler::Fail; 1819 break; 1820 default: 1821 break; 1822 } 1823 1824 // Fourth output register 1825 switch (Inst.getOpcode()) { 1826 case ARM::VLD1d8Q: 1827 case ARM::VLD1d16Q: 1828 case ARM::VLD1d32Q: 1829 case ARM::VLD1d64Q: 1830 case ARM::VLD1d8Q_UPD: 1831 case ARM::VLD1d16Q_UPD: 1832 case ARM::VLD1d32Q_UPD: 1833 case ARM::VLD1d64Q_UPD: 1834 case ARM::VLD2q8: 1835 case ARM::VLD2q16: 1836 case ARM::VLD2q32: 1837 case ARM::VLD2q8_UPD: 1838 case ARM::VLD2q16_UPD: 1839 case ARM::VLD2q32_UPD: 1840 case ARM::VLD4d8: 1841 case ARM::VLD4d16: 1842 case ARM::VLD4d32: 1843 case ARM::VLD4d8_UPD: 1844 case ARM::VLD4d16_UPD: 1845 case ARM::VLD4d32_UPD: 1846 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 1847 return MCDisassembler::Fail; 1848 break; 1849 case ARM::VLD4q8: 1850 case ARM::VLD4q16: 1851 case ARM::VLD4q32: 1852 case ARM::VLD4q8_UPD: 1853 case ARM::VLD4q16_UPD: 1854 case ARM::VLD4q32_UPD: 1855 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 1856 return MCDisassembler::Fail; 1857 break; 1858 default: 1859 break; 1860 } 1861 1862 // Writeback operand 1863 switch (Inst.getOpcode()) { 1864 case ARM::VLD1d8_UPD: 1865 case ARM::VLD1d16_UPD: 1866 case ARM::VLD1d32_UPD: 1867 case ARM::VLD1d64_UPD: 1868 case ARM::VLD1q8_UPD: 1869 case ARM::VLD1q16_UPD: 1870 case ARM::VLD1q32_UPD: 1871 case ARM::VLD1q64_UPD: 1872 case ARM::VLD1d8T_UPD: 1873 case ARM::VLD1d16T_UPD: 1874 case ARM::VLD1d32T_UPD: 1875 case ARM::VLD1d64T_UPD: 1876 case ARM::VLD1d8Q_UPD: 1877 case ARM::VLD1d16Q_UPD: 1878 case ARM::VLD1d32Q_UPD: 1879 case ARM::VLD1d64Q_UPD: 1880 case ARM::VLD2d8_UPD: 1881 case ARM::VLD2d16_UPD: 1882 case ARM::VLD2d32_UPD: 1883 case ARM::VLD2q8_UPD: 1884 case ARM::VLD2q16_UPD: 1885 case ARM::VLD2q32_UPD: 1886 case ARM::VLD2b8_UPD: 1887 case ARM::VLD2b16_UPD: 1888 case ARM::VLD2b32_UPD: 1889 case ARM::VLD3d8_UPD: 1890 case ARM::VLD3d16_UPD: 1891 case ARM::VLD3d32_UPD: 1892 case ARM::VLD3q8_UPD: 1893 case ARM::VLD3q16_UPD: 1894 case ARM::VLD3q32_UPD: 1895 case ARM::VLD4d8_UPD: 1896 case ARM::VLD4d16_UPD: 1897 case ARM::VLD4d32_UPD: 1898 case ARM::VLD4q8_UPD: 1899 case ARM::VLD4q16_UPD: 1900 case ARM::VLD4q32_UPD: 1901 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 1902 return MCDisassembler::Fail; 1903 break; 1904 default: 1905 break; 1906 } 1907 1908 // AddrMode6 Base (register+alignment) 1909 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 1910 return MCDisassembler::Fail; 1911 1912 // AddrMode6 Offset (register) 1913 if (Rm == 0xD) 1914 Inst.addOperand(MCOperand::CreateReg(0)); 1915 else if (Rm != 0xF) { 1916 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1917 return MCDisassembler::Fail; 1918 } 1919 1920 return S; 1921 } 1922 1923 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1924 uint64_t Address, const void *Decoder) { 1925 DecodeStatus S = MCDisassembler::Success; 1926 1927 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1928 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1929 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1930 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1931 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1932 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1933 1934 // Writeback Operand 1935 switch (Inst.getOpcode()) { 1936 case ARM::VST1d8_UPD: 1937 case ARM::VST1d16_UPD: 1938 case ARM::VST1d32_UPD: 1939 case ARM::VST1d64_UPD: 1940 case ARM::VST1q8_UPD: 1941 case ARM::VST1q16_UPD: 1942 case ARM::VST1q32_UPD: 1943 case ARM::VST1q64_UPD: 1944 case ARM::VST1d8T_UPD: 1945 case ARM::VST1d16T_UPD: 1946 case ARM::VST1d32T_UPD: 1947 case ARM::VST1d64T_UPD: 1948 case ARM::VST1d8Q_UPD: 1949 case ARM::VST1d16Q_UPD: 1950 case ARM::VST1d32Q_UPD: 1951 case ARM::VST1d64Q_UPD: 1952 case ARM::VST2d8_UPD: 1953 case ARM::VST2d16_UPD: 1954 case ARM::VST2d32_UPD: 1955 case ARM::VST2q8_UPD: 1956 case ARM::VST2q16_UPD: 1957 case ARM::VST2q32_UPD: 1958 case ARM::VST2b8_UPD: 1959 case ARM::VST2b16_UPD: 1960 case ARM::VST2b32_UPD: 1961 case ARM::VST3d8_UPD: 1962 case ARM::VST3d16_UPD: 1963 case ARM::VST3d32_UPD: 1964 case ARM::VST3q8_UPD: 1965 case ARM::VST3q16_UPD: 1966 case ARM::VST3q32_UPD: 1967 case ARM::VST4d8_UPD: 1968 case ARM::VST4d16_UPD: 1969 case ARM::VST4d32_UPD: 1970 case ARM::VST4q8_UPD: 1971 case ARM::VST4q16_UPD: 1972 case ARM::VST4q32_UPD: 1973 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 1974 return MCDisassembler::Fail; 1975 break; 1976 default: 1977 break; 1978 } 1979 1980 // AddrMode6 Base (register+alignment) 1981 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 1982 return MCDisassembler::Fail; 1983 1984 // AddrMode6 Offset (register) 1985 if (Rm == 0xD) 1986 Inst.addOperand(MCOperand::CreateReg(0)); 1987 else if (Rm != 0xF) { 1988 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1989 return MCDisassembler::Fail; 1990 } 1991 1992 // First input register 1993 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 1994 return MCDisassembler::Fail; 1995 1996 // Second input register 1997 switch (Inst.getOpcode()) { 1998 case ARM::VST1q8: 1999 case ARM::VST1q16: 2000 case ARM::VST1q32: 2001 case ARM::VST1q64: 2002 case ARM::VST1q8_UPD: 2003 case ARM::VST1q16_UPD: 2004 case ARM::VST1q32_UPD: 2005 case ARM::VST1q64_UPD: 2006 case ARM::VST1d8T: 2007 case ARM::VST1d16T: 2008 case ARM::VST1d32T: 2009 case ARM::VST1d64T: 2010 case ARM::VST1d8T_UPD: 2011 case ARM::VST1d16T_UPD: 2012 case ARM::VST1d32T_UPD: 2013 case ARM::VST1d64T_UPD: 2014 case ARM::VST1d8Q: 2015 case ARM::VST1d16Q: 2016 case ARM::VST1d32Q: 2017 case ARM::VST1d64Q: 2018 case ARM::VST1d8Q_UPD: 2019 case ARM::VST1d16Q_UPD: 2020 case ARM::VST1d32Q_UPD: 2021 case ARM::VST1d64Q_UPD: 2022 case ARM::VST2d8: 2023 case ARM::VST2d16: 2024 case ARM::VST2d32: 2025 case ARM::VST2d8_UPD: 2026 case ARM::VST2d16_UPD: 2027 case ARM::VST2d32_UPD: 2028 case ARM::VST2q8: 2029 case ARM::VST2q16: 2030 case ARM::VST2q32: 2031 case ARM::VST2q8_UPD: 2032 case ARM::VST2q16_UPD: 2033 case ARM::VST2q32_UPD: 2034 case ARM::VST3d8: 2035 case ARM::VST3d16: 2036 case ARM::VST3d32: 2037 case ARM::VST3d8_UPD: 2038 case ARM::VST3d16_UPD: 2039 case ARM::VST3d32_UPD: 2040 case ARM::VST4d8: 2041 case ARM::VST4d16: 2042 case ARM::VST4d32: 2043 case ARM::VST4d8_UPD: 2044 case ARM::VST4d16_UPD: 2045 case ARM::VST4d32_UPD: 2046 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2047 return MCDisassembler::Fail; 2048 break; 2049 case ARM::VST2b8: 2050 case ARM::VST2b16: 2051 case ARM::VST2b32: 2052 case ARM::VST2b8_UPD: 2053 case ARM::VST2b16_UPD: 2054 case ARM::VST2b32_UPD: 2055 case ARM::VST3q8: 2056 case ARM::VST3q16: 2057 case ARM::VST3q32: 2058 case ARM::VST3q8_UPD: 2059 case ARM::VST3q16_UPD: 2060 case ARM::VST3q32_UPD: 2061 case ARM::VST4q8: 2062 case ARM::VST4q16: 2063 case ARM::VST4q32: 2064 case ARM::VST4q8_UPD: 2065 case ARM::VST4q16_UPD: 2066 case ARM::VST4q32_UPD: 2067 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2068 return MCDisassembler::Fail; 2069 break; 2070 default: 2071 break; 2072 } 2073 2074 // Third input register 2075 switch (Inst.getOpcode()) { 2076 case ARM::VST1d8T: 2077 case ARM::VST1d16T: 2078 case ARM::VST1d32T: 2079 case ARM::VST1d64T: 2080 case ARM::VST1d8T_UPD: 2081 case ARM::VST1d16T_UPD: 2082 case ARM::VST1d32T_UPD: 2083 case ARM::VST1d64T_UPD: 2084 case ARM::VST1d8Q: 2085 case ARM::VST1d16Q: 2086 case ARM::VST1d32Q: 2087 case ARM::VST1d64Q: 2088 case ARM::VST1d8Q_UPD: 2089 case ARM::VST1d16Q_UPD: 2090 case ARM::VST1d32Q_UPD: 2091 case ARM::VST1d64Q_UPD: 2092 case ARM::VST2q8: 2093 case ARM::VST2q16: 2094 case ARM::VST2q32: 2095 case ARM::VST2q8_UPD: 2096 case ARM::VST2q16_UPD: 2097 case ARM::VST2q32_UPD: 2098 case ARM::VST3d8: 2099 case ARM::VST3d16: 2100 case ARM::VST3d32: 2101 case ARM::VST3d8_UPD: 2102 case ARM::VST3d16_UPD: 2103 case ARM::VST3d32_UPD: 2104 case ARM::VST4d8: 2105 case ARM::VST4d16: 2106 case ARM::VST4d32: 2107 case ARM::VST4d8_UPD: 2108 case ARM::VST4d16_UPD: 2109 case ARM::VST4d32_UPD: 2110 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2111 return MCDisassembler::Fail; 2112 break; 2113 case ARM::VST3q8: 2114 case ARM::VST3q16: 2115 case ARM::VST3q32: 2116 case ARM::VST3q8_UPD: 2117 case ARM::VST3q16_UPD: 2118 case ARM::VST3q32_UPD: 2119 case ARM::VST4q8: 2120 case ARM::VST4q16: 2121 case ARM::VST4q32: 2122 case ARM::VST4q8_UPD: 2123 case ARM::VST4q16_UPD: 2124 case ARM::VST4q32_UPD: 2125 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2126 return MCDisassembler::Fail; 2127 break; 2128 default: 2129 break; 2130 } 2131 2132 // Fourth input register 2133 switch (Inst.getOpcode()) { 2134 case ARM::VST1d8Q: 2135 case ARM::VST1d16Q: 2136 case ARM::VST1d32Q: 2137 case ARM::VST1d64Q: 2138 case ARM::VST1d8Q_UPD: 2139 case ARM::VST1d16Q_UPD: 2140 case ARM::VST1d32Q_UPD: 2141 case ARM::VST1d64Q_UPD: 2142 case ARM::VST2q8: 2143 case ARM::VST2q16: 2144 case ARM::VST2q32: 2145 case ARM::VST2q8_UPD: 2146 case ARM::VST2q16_UPD: 2147 case ARM::VST2q32_UPD: 2148 case ARM::VST4d8: 2149 case ARM::VST4d16: 2150 case ARM::VST4d32: 2151 case ARM::VST4d8_UPD: 2152 case ARM::VST4d16_UPD: 2153 case ARM::VST4d32_UPD: 2154 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2155 return MCDisassembler::Fail; 2156 break; 2157 case ARM::VST4q8: 2158 case ARM::VST4q16: 2159 case ARM::VST4q32: 2160 case ARM::VST4q8_UPD: 2161 case ARM::VST4q16_UPD: 2162 case ARM::VST4q32_UPD: 2163 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2164 return MCDisassembler::Fail; 2165 break; 2166 default: 2167 break; 2168 } 2169 2170 return S; 2171 } 2172 2173 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2174 uint64_t Address, const void *Decoder) { 2175 DecodeStatus S = MCDisassembler::Success; 2176 2177 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2178 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2179 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2180 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2181 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2182 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2183 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 2184 2185 align *= (1 << size); 2186 2187 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2188 return MCDisassembler::Fail; 2189 if (regs == 2) { 2190 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2191 return MCDisassembler::Fail; 2192 } 2193 if (Rm != 0xF) { 2194 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2195 return MCDisassembler::Fail; 2196 } 2197 2198 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2199 return MCDisassembler::Fail; 2200 Inst.addOperand(MCOperand::CreateImm(align)); 2201 2202 if (Rm == 0xD) 2203 Inst.addOperand(MCOperand::CreateReg(0)); 2204 else if (Rm != 0xF) { 2205 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2206 return MCDisassembler::Fail; 2207 } 2208 2209 return S; 2210 } 2211 2212 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2213 uint64_t Address, const void *Decoder) { 2214 DecodeStatus S = MCDisassembler::Success; 2215 2216 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2217 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2218 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2219 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2220 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2221 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2222 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2223 align *= 2*size; 2224 2225 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2226 return MCDisassembler::Fail; 2227 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2228 return MCDisassembler::Fail; 2229 if (Rm != 0xF) { 2230 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2231 return MCDisassembler::Fail; 2232 } 2233 2234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2235 return MCDisassembler::Fail; 2236 Inst.addOperand(MCOperand::CreateImm(align)); 2237 2238 if (Rm == 0xD) 2239 Inst.addOperand(MCOperand::CreateReg(0)); 2240 else if (Rm != 0xF) { 2241 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2242 return MCDisassembler::Fail; 2243 } 2244 2245 return S; 2246 } 2247 2248 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2249 uint64_t Address, const void *Decoder) { 2250 DecodeStatus S = MCDisassembler::Success; 2251 2252 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2253 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2254 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2255 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2256 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2257 2258 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2259 return MCDisassembler::Fail; 2260 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2261 return MCDisassembler::Fail; 2262 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2263 return MCDisassembler::Fail; 2264 if (Rm != 0xF) { 2265 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2266 return MCDisassembler::Fail; 2267 } 2268 2269 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2270 return MCDisassembler::Fail; 2271 Inst.addOperand(MCOperand::CreateImm(0)); 2272 2273 if (Rm == 0xD) 2274 Inst.addOperand(MCOperand::CreateReg(0)); 2275 else if (Rm != 0xF) { 2276 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2277 return MCDisassembler::Fail; 2278 } 2279 2280 return S; 2281 } 2282 2283 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2284 uint64_t Address, const void *Decoder) { 2285 DecodeStatus S = MCDisassembler::Success; 2286 2287 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2288 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2289 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2290 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2291 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2292 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2293 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2294 2295 if (size == 0x3) { 2296 size = 4; 2297 align = 16; 2298 } else { 2299 if (size == 2) { 2300 size = 1 << size; 2301 align *= 8; 2302 } else { 2303 size = 1 << size; 2304 align *= 4*size; 2305 } 2306 } 2307 2308 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2309 return MCDisassembler::Fail; 2310 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2311 return MCDisassembler::Fail; 2312 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2313 return MCDisassembler::Fail; 2314 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2315 return MCDisassembler::Fail; 2316 if (Rm != 0xF) { 2317 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2318 return MCDisassembler::Fail; 2319 } 2320 2321 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2322 return MCDisassembler::Fail; 2323 Inst.addOperand(MCOperand::CreateImm(align)); 2324 2325 if (Rm == 0xD) 2326 Inst.addOperand(MCOperand::CreateReg(0)); 2327 else if (Rm != 0xF) { 2328 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2329 return MCDisassembler::Fail; 2330 } 2331 2332 return S; 2333 } 2334 2335 static DecodeStatus 2336 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2337 uint64_t Address, const void *Decoder) { 2338 DecodeStatus S = MCDisassembler::Success; 2339 2340 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2341 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2342 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2343 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2344 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2345 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2346 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2347 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2348 2349 if (Q) { 2350 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2351 return MCDisassembler::Fail; 2352 } else { 2353 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2354 return MCDisassembler::Fail; 2355 } 2356 2357 Inst.addOperand(MCOperand::CreateImm(imm)); 2358 2359 switch (Inst.getOpcode()) { 2360 case ARM::VORRiv4i16: 2361 case ARM::VORRiv2i32: 2362 case ARM::VBICiv4i16: 2363 case ARM::VBICiv2i32: 2364 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2365 return MCDisassembler::Fail; 2366 break; 2367 case ARM::VORRiv8i16: 2368 case ARM::VORRiv4i32: 2369 case ARM::VBICiv8i16: 2370 case ARM::VBICiv4i32: 2371 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2372 return MCDisassembler::Fail; 2373 break; 2374 default: 2375 break; 2376 } 2377 2378 return S; 2379 } 2380 2381 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2382 uint64_t Address, const void *Decoder) { 2383 DecodeStatus S = MCDisassembler::Success; 2384 2385 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2386 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2387 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2388 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2389 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2390 2391 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2392 return MCDisassembler::Fail; 2393 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2394 return MCDisassembler::Fail; 2395 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2396 2397 return S; 2398 } 2399 2400 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2401 uint64_t Address, const void *Decoder) { 2402 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2403 return MCDisassembler::Success; 2404 } 2405 2406 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2407 uint64_t Address, const void *Decoder) { 2408 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2409 return MCDisassembler::Success; 2410 } 2411 2412 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2413 uint64_t Address, const void *Decoder) { 2414 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2415 return MCDisassembler::Success; 2416 } 2417 2418 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2419 uint64_t Address, const void *Decoder) { 2420 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2421 return MCDisassembler::Success; 2422 } 2423 2424 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2425 uint64_t Address, const void *Decoder) { 2426 DecodeStatus S = MCDisassembler::Success; 2427 2428 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2429 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2430 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2431 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2432 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2433 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2434 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2435 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2436 2437 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2438 return MCDisassembler::Fail; 2439 if (op) { 2440 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2441 return MCDisassembler::Fail; // Writeback 2442 } 2443 2444 for (unsigned i = 0; i < length; ++i) { 2445 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder))) 2446 return MCDisassembler::Fail; 2447 } 2448 2449 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2450 return MCDisassembler::Fail; 2451 2452 return S; 2453 } 2454 2455 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2456 uint64_t Address, const void *Decoder) { 2457 // The immediate needs to be a fully instantiated float. However, the 2458 // auto-generated decoder is only able to fill in some of the bits 2459 // necessary. For instance, the 'b' bit is replicated multiple times, 2460 // and is even present in inverted form in one bit. We do a little 2461 // binary parsing here to fill in those missing bits, and then 2462 // reinterpret it all as a float. 2463 union { 2464 uint32_t integer; 2465 float fp; 2466 } fp_conv; 2467 2468 fp_conv.integer = Val; 2469 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2470 fp_conv.integer |= b << 26; 2471 fp_conv.integer |= b << 27; 2472 fp_conv.integer |= b << 28; 2473 fp_conv.integer |= b << 29; 2474 fp_conv.integer |= (~b & 0x1) << 30; 2475 2476 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2477 return MCDisassembler::Success; 2478 } 2479 2480 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2481 uint64_t Address, const void *Decoder) { 2482 DecodeStatus S = MCDisassembler::Success; 2483 2484 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2485 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2486 2487 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2488 return MCDisassembler::Fail; 2489 2490 switch(Inst.getOpcode()) { 2491 default: 2492 return MCDisassembler::Fail; 2493 case ARM::tADR: 2494 break; // tADR does not explicitly represent the PC as an operand. 2495 case ARM::tADDrSPi: 2496 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2497 break; 2498 } 2499 2500 Inst.addOperand(MCOperand::CreateImm(imm)); 2501 return S; 2502 } 2503 2504 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2505 uint64_t Address, const void *Decoder) { 2506 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2507 return MCDisassembler::Success; 2508 } 2509 2510 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2511 uint64_t Address, const void *Decoder) { 2512 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2513 return MCDisassembler::Success; 2514 } 2515 2516 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2517 uint64_t Address, const void *Decoder) { 2518 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2519 return MCDisassembler::Success; 2520 } 2521 2522 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2523 uint64_t Address, const void *Decoder) { 2524 DecodeStatus S = MCDisassembler::Success; 2525 2526 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2527 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2528 2529 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2530 return MCDisassembler::Fail; 2531 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 2532 return MCDisassembler::Fail; 2533 2534 return S; 2535 } 2536 2537 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2538 uint64_t Address, const void *Decoder) { 2539 DecodeStatus S = MCDisassembler::Success; 2540 2541 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2542 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2543 2544 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2545 return MCDisassembler::Fail; 2546 Inst.addOperand(MCOperand::CreateImm(imm)); 2547 2548 return S; 2549 } 2550 2551 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2552 uint64_t Address, const void *Decoder) { 2553 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2554 2555 return MCDisassembler::Success; 2556 } 2557 2558 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2559 uint64_t Address, const void *Decoder) { 2560 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2561 Inst.addOperand(MCOperand::CreateImm(Val)); 2562 2563 return MCDisassembler::Success; 2564 } 2565 2566 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2567 uint64_t Address, const void *Decoder) { 2568 DecodeStatus S = MCDisassembler::Success; 2569 2570 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2571 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2572 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2573 2574 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2575 return MCDisassembler::Fail; 2576 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 2577 return MCDisassembler::Fail; 2578 Inst.addOperand(MCOperand::CreateImm(imm)); 2579 2580 return S; 2581 } 2582 2583 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2584 uint64_t Address, const void *Decoder) { 2585 DecodeStatus S = MCDisassembler::Success; 2586 2587 switch (Inst.getOpcode()) { 2588 case ARM::t2PLDs: 2589 case ARM::t2PLDWs: 2590 case ARM::t2PLIs: 2591 break; 2592 default: { 2593 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2594 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2595 return MCDisassembler::Fail; 2596 } 2597 } 2598 2599 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2600 if (Rn == 0xF) { 2601 switch (Inst.getOpcode()) { 2602 case ARM::t2LDRBs: 2603 Inst.setOpcode(ARM::t2LDRBpci); 2604 break; 2605 case ARM::t2LDRHs: 2606 Inst.setOpcode(ARM::t2LDRHpci); 2607 break; 2608 case ARM::t2LDRSHs: 2609 Inst.setOpcode(ARM::t2LDRSHpci); 2610 break; 2611 case ARM::t2LDRSBs: 2612 Inst.setOpcode(ARM::t2LDRSBpci); 2613 break; 2614 case ARM::t2PLDs: 2615 Inst.setOpcode(ARM::t2PLDi12); 2616 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2617 break; 2618 default: 2619 return MCDisassembler::Fail; 2620 } 2621 2622 int imm = fieldFromInstruction32(Insn, 0, 12); 2623 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2624 Inst.addOperand(MCOperand::CreateImm(imm)); 2625 2626 return S; 2627 } 2628 2629 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2630 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2631 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2632 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 2633 return MCDisassembler::Fail; 2634 2635 return S; 2636 } 2637 2638 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2639 uint64_t Address, const void *Decoder) { 2640 int imm = Val & 0xFF; 2641 if (!(Val & 0x100)) imm *= -1; 2642 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2643 2644 return MCDisassembler::Success; 2645 } 2646 2647 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2648 uint64_t Address, const void *Decoder) { 2649 DecodeStatus S = MCDisassembler::Success; 2650 2651 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2652 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2653 2654 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2655 return MCDisassembler::Fail; 2656 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 2657 return MCDisassembler::Fail; 2658 2659 return S; 2660 } 2661 2662 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2663 uint64_t Address, const void *Decoder) { 2664 int imm = Val & 0xFF; 2665 if (!(Val & 0x100)) imm *= -1; 2666 Inst.addOperand(MCOperand::CreateImm(imm)); 2667 2668 return MCDisassembler::Success; 2669 } 2670 2671 2672 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2673 uint64_t Address, const void *Decoder) { 2674 DecodeStatus S = MCDisassembler::Success; 2675 2676 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2677 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2678 2679 // Some instructions always use an additive offset. 2680 switch (Inst.getOpcode()) { 2681 case ARM::t2LDRT: 2682 case ARM::t2LDRBT: 2683 case ARM::t2LDRHT: 2684 case ARM::t2LDRSBT: 2685 case ARM::t2LDRSHT: 2686 imm |= 0x100; 2687 break; 2688 default: 2689 break; 2690 } 2691 2692 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2693 return MCDisassembler::Fail; 2694 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 2695 return MCDisassembler::Fail; 2696 2697 return S; 2698 } 2699 2700 2701 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2702 uint64_t Address, const void *Decoder) { 2703 DecodeStatus S = MCDisassembler::Success; 2704 2705 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2706 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2707 2708 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2709 return MCDisassembler::Fail; 2710 Inst.addOperand(MCOperand::CreateImm(imm)); 2711 2712 return S; 2713 } 2714 2715 2716 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2717 uint64_t Address, const void *Decoder) { 2718 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2719 2720 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2721 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2722 Inst.addOperand(MCOperand::CreateImm(imm)); 2723 2724 return MCDisassembler::Success; 2725 } 2726 2727 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2728 uint64_t Address, const void *Decoder) { 2729 DecodeStatus S = MCDisassembler::Success; 2730 2731 if (Inst.getOpcode() == ARM::tADDrSP) { 2732 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2733 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2734 2735 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2736 return MCDisassembler::Fail; 2737 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2738 return MCDisassembler::Fail; 2739 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2740 } else if (Inst.getOpcode() == ARM::tADDspr) { 2741 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2742 2743 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2744 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2745 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2746 return MCDisassembler::Fail; 2747 } 2748 2749 return S; 2750 } 2751 2752 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2753 uint64_t Address, const void *Decoder) { 2754 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2755 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2756 2757 Inst.addOperand(MCOperand::CreateImm(imod)); 2758 Inst.addOperand(MCOperand::CreateImm(flags)); 2759 2760 return MCDisassembler::Success; 2761 } 2762 2763 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2764 uint64_t Address, const void *Decoder) { 2765 DecodeStatus S = MCDisassembler::Success; 2766 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2767 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2768 2769 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2770 return MCDisassembler::Fail; 2771 Inst.addOperand(MCOperand::CreateImm(add)); 2772 2773 return S; 2774 } 2775 2776 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2777 uint64_t Address, const void *Decoder) { 2778 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2779 return MCDisassembler::Success; 2780 } 2781 2782 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2783 uint64_t Address, const void *Decoder) { 2784 if (Val == 0xA || Val == 0xB) 2785 return MCDisassembler::Fail; 2786 2787 Inst.addOperand(MCOperand::CreateImm(Val)); 2788 return MCDisassembler::Success; 2789 } 2790 2791 static DecodeStatus 2792 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2793 uint64_t Address, const void *Decoder) { 2794 DecodeStatus S = MCDisassembler::Success; 2795 2796 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2797 if (pred == 0xE || pred == 0xF) { 2798 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 2799 switch (opc) { 2800 default: 2801 return MCDisassembler::Fail; 2802 case 0xf3bf8f4: 2803 Inst.setOpcode(ARM::t2DSB); 2804 break; 2805 case 0xf3bf8f5: 2806 Inst.setOpcode(ARM::t2DMB); 2807 break; 2808 case 0xf3bf8f6: 2809 Inst.setOpcode(ARM::t2ISB); 2810 break; 2811 } 2812 2813 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2814 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2815 } 2816 2817 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2818 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2819 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2820 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2821 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2822 2823 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 2824 return MCDisassembler::Fail; 2825 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2826 return MCDisassembler::Fail; 2827 2828 return S; 2829 } 2830 2831 // Decode a shifted immediate operand. These basically consist 2832 // of an 8-bit value, and a 4-bit directive that specifies either 2833 // a splat operation or a rotation. 2834 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2835 uint64_t Address, const void *Decoder) { 2836 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2837 if (ctrl == 0) { 2838 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2839 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2840 switch (byte) { 2841 case 0: 2842 Inst.addOperand(MCOperand::CreateImm(imm)); 2843 break; 2844 case 1: 2845 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2846 break; 2847 case 2: 2848 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2849 break; 2850 case 3: 2851 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2852 (imm << 8) | imm)); 2853 break; 2854 } 2855 } else { 2856 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2857 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2858 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2859 Inst.addOperand(MCOperand::CreateImm(imm)); 2860 } 2861 2862 return MCDisassembler::Success; 2863 } 2864 2865 static DecodeStatus 2866 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2867 uint64_t Address, const void *Decoder){ 2868 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2869 return MCDisassembler::Success; 2870 } 2871 2872 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2873 uint64_t Address, const void *Decoder){ 2874 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2875 return MCDisassembler::Success; 2876 } 2877 2878 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2879 uint64_t Address, const void *Decoder) { 2880 switch (Val) { 2881 default: 2882 return MCDisassembler::Fail; 2883 case 0xF: // SY 2884 case 0xE: // ST 2885 case 0xB: // ISH 2886 case 0xA: // ISHST 2887 case 0x7: // NSH 2888 case 0x6: // NSHST 2889 case 0x3: // OSH 2890 case 0x2: // OSHST 2891 break; 2892 } 2893 2894 Inst.addOperand(MCOperand::CreateImm(Val)); 2895 return MCDisassembler::Success; 2896 } 2897 2898 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 2899 uint64_t Address, const void *Decoder) { 2900 if (!Val) return MCDisassembler::Fail; 2901 Inst.addOperand(MCOperand::CreateImm(Val)); 2902 return MCDisassembler::Success; 2903 } 2904 2905 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 2906 uint64_t Address, const void *Decoder) { 2907 DecodeStatus S = MCDisassembler::Success; 2908 2909 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2910 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2911 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2912 2913 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 2914 2915 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2916 return MCDisassembler::Fail; 2917 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2918 return MCDisassembler::Fail; 2919 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2920 return MCDisassembler::Fail; 2921 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2922 return MCDisassembler::Fail; 2923 2924 return S; 2925 } 2926 2927 2928 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 2929 uint64_t Address, const void *Decoder){ 2930 DecodeStatus S = MCDisassembler::Success; 2931 2932 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2933 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 2934 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2935 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2936 2937 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2938 return MCDisassembler::Fail; 2939 2940 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 2941 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 2942 2943 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2944 return MCDisassembler::Fail; 2945 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2946 return MCDisassembler::Fail; 2947 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2948 return MCDisassembler::Fail; 2949 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2950 return MCDisassembler::Fail; 2951 2952 return S; 2953 } 2954 2955 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 2956 uint64_t Address, const void *Decoder) { 2957 DecodeStatus S = MCDisassembler::Success; 2958 2959 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2960 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2961 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2962 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2963 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2964 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2965 2966 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 2967 2968 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2969 return MCDisassembler::Fail; 2970 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2971 return MCDisassembler::Fail; 2972 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 2973 return MCDisassembler::Fail; 2974 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2975 return MCDisassembler::Fail; 2976 2977 return S; 2978 } 2979 2980 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 2981 uint64_t Address, const void *Decoder) { 2982 DecodeStatus S = MCDisassembler::Success; 2983 2984 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2985 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2986 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2987 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2988 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2989 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2990 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2991 2992 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 2993 if (Rm == 0xF) S = MCDisassembler::SoftFail; 2994 2995 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2996 return MCDisassembler::Fail; 2997 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2998 return MCDisassembler::Fail; 2999 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3000 return MCDisassembler::Fail; 3001 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3002 return MCDisassembler::Fail; 3003 3004 return S; 3005 } 3006 3007 3008 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 3009 uint64_t Address, const void *Decoder) { 3010 DecodeStatus S = MCDisassembler::Success; 3011 3012 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3013 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3014 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3015 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3016 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3017 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3018 3019 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3020 3021 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3022 return MCDisassembler::Fail; 3023 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3024 return MCDisassembler::Fail; 3025 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3026 return MCDisassembler::Fail; 3027 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3028 return MCDisassembler::Fail; 3029 3030 return S; 3031 } 3032 3033 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 3034 uint64_t Address, const void *Decoder) { 3035 DecodeStatus S = MCDisassembler::Success; 3036 3037 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3038 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3039 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3040 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3041 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3042 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3043 3044 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3045 3046 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3047 return MCDisassembler::Fail; 3048 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3049 return MCDisassembler::Fail; 3050 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3051 return MCDisassembler::Fail; 3052 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3053 return MCDisassembler::Fail; 3054 3055 return S; 3056 } 3057 3058 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 3059 uint64_t Address, const void *Decoder) { 3060 DecodeStatus S = MCDisassembler::Success; 3061 3062 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3063 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3064 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3065 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3066 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3067 3068 unsigned align = 0; 3069 unsigned index = 0; 3070 switch (size) { 3071 default: 3072 return MCDisassembler::Fail; 3073 case 0: 3074 if (fieldFromInstruction32(Insn, 4, 1)) 3075 return MCDisassembler::Fail; // UNDEFINED 3076 index = fieldFromInstruction32(Insn, 5, 3); 3077 break; 3078 case 1: 3079 if (fieldFromInstruction32(Insn, 5, 1)) 3080 return MCDisassembler::Fail; // UNDEFINED 3081 index = fieldFromInstruction32(Insn, 6, 2); 3082 if (fieldFromInstruction32(Insn, 4, 1)) 3083 align = 2; 3084 break; 3085 case 2: 3086 if (fieldFromInstruction32(Insn, 6, 1)) 3087 return MCDisassembler::Fail; // UNDEFINED 3088 index = fieldFromInstruction32(Insn, 7, 1); 3089 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3090 align = 4; 3091 } 3092 3093 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3094 return MCDisassembler::Fail; 3095 if (Rm != 0xF) { // Writeback 3096 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3097 return MCDisassembler::Fail; 3098 } 3099 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3100 return MCDisassembler::Fail; 3101 Inst.addOperand(MCOperand::CreateImm(align)); 3102 if (Rm != 0xF) { 3103 if (Rm != 0xD) { 3104 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3105 return MCDisassembler::Fail; 3106 } else 3107 Inst.addOperand(MCOperand::CreateReg(0)); 3108 } 3109 3110 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3111 return MCDisassembler::Fail; 3112 Inst.addOperand(MCOperand::CreateImm(index)); 3113 3114 return S; 3115 } 3116 3117 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 3118 uint64_t Address, const void *Decoder) { 3119 DecodeStatus S = MCDisassembler::Success; 3120 3121 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3122 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3123 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3124 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3125 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3126 3127 unsigned align = 0; 3128 unsigned index = 0; 3129 switch (size) { 3130 default: 3131 return MCDisassembler::Fail; 3132 case 0: 3133 if (fieldFromInstruction32(Insn, 4, 1)) 3134 return MCDisassembler::Fail; // UNDEFINED 3135 index = fieldFromInstruction32(Insn, 5, 3); 3136 break; 3137 case 1: 3138 if (fieldFromInstruction32(Insn, 5, 1)) 3139 return MCDisassembler::Fail; // UNDEFINED 3140 index = fieldFromInstruction32(Insn, 6, 2); 3141 if (fieldFromInstruction32(Insn, 4, 1)) 3142 align = 2; 3143 break; 3144 case 2: 3145 if (fieldFromInstruction32(Insn, 6, 1)) 3146 return MCDisassembler::Fail; // UNDEFINED 3147 index = fieldFromInstruction32(Insn, 7, 1); 3148 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3149 align = 4; 3150 } 3151 3152 if (Rm != 0xF) { // Writeback 3153 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3154 return MCDisassembler::Fail; 3155 } 3156 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3157 return MCDisassembler::Fail; 3158 Inst.addOperand(MCOperand::CreateImm(align)); 3159 if (Rm != 0xF) { 3160 if (Rm != 0xD) { 3161 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3162 return MCDisassembler::Fail; 3163 } else 3164 Inst.addOperand(MCOperand::CreateReg(0)); 3165 } 3166 3167 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3168 return MCDisassembler::Fail; 3169 Inst.addOperand(MCOperand::CreateImm(index)); 3170 3171 return S; 3172 } 3173 3174 3175 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 3176 uint64_t Address, const void *Decoder) { 3177 DecodeStatus S = MCDisassembler::Success; 3178 3179 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3180 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3181 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3182 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3183 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3184 3185 unsigned align = 0; 3186 unsigned index = 0; 3187 unsigned inc = 1; 3188 switch (size) { 3189 default: 3190 return MCDisassembler::Fail; 3191 case 0: 3192 index = fieldFromInstruction32(Insn, 5, 3); 3193 if (fieldFromInstruction32(Insn, 4, 1)) 3194 align = 2; 3195 break; 3196 case 1: 3197 index = fieldFromInstruction32(Insn, 6, 2); 3198 if (fieldFromInstruction32(Insn, 4, 1)) 3199 align = 4; 3200 if (fieldFromInstruction32(Insn, 5, 1)) 3201 inc = 2; 3202 break; 3203 case 2: 3204 if (fieldFromInstruction32(Insn, 5, 1)) 3205 return MCDisassembler::Fail; // UNDEFINED 3206 index = fieldFromInstruction32(Insn, 7, 1); 3207 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3208 align = 8; 3209 if (fieldFromInstruction32(Insn, 6, 1)) 3210 inc = 2; 3211 break; 3212 } 3213 3214 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3215 return MCDisassembler::Fail; 3216 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3217 return MCDisassembler::Fail; 3218 if (Rm != 0xF) { // Writeback 3219 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3220 return MCDisassembler::Fail; 3221 } 3222 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3223 return MCDisassembler::Fail; 3224 Inst.addOperand(MCOperand::CreateImm(align)); 3225 if (Rm != 0xF) { 3226 if (Rm != 0xD) { 3227 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3228 return MCDisassembler::Fail; 3229 } else 3230 Inst.addOperand(MCOperand::CreateReg(0)); 3231 } 3232 3233 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3234 return MCDisassembler::Fail; 3235 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3236 return MCDisassembler::Fail; 3237 Inst.addOperand(MCOperand::CreateImm(index)); 3238 3239 return S; 3240 } 3241 3242 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 3243 uint64_t Address, const void *Decoder) { 3244 DecodeStatus S = MCDisassembler::Success; 3245 3246 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3247 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3248 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3249 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3250 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3251 3252 unsigned align = 0; 3253 unsigned index = 0; 3254 unsigned inc = 1; 3255 switch (size) { 3256 default: 3257 return MCDisassembler::Fail; 3258 case 0: 3259 index = fieldFromInstruction32(Insn, 5, 3); 3260 if (fieldFromInstruction32(Insn, 4, 1)) 3261 align = 2; 3262 break; 3263 case 1: 3264 index = fieldFromInstruction32(Insn, 6, 2); 3265 if (fieldFromInstruction32(Insn, 4, 1)) 3266 align = 4; 3267 if (fieldFromInstruction32(Insn, 5, 1)) 3268 inc = 2; 3269 break; 3270 case 2: 3271 if (fieldFromInstruction32(Insn, 5, 1)) 3272 return MCDisassembler::Fail; // UNDEFINED 3273 index = fieldFromInstruction32(Insn, 7, 1); 3274 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3275 align = 8; 3276 if (fieldFromInstruction32(Insn, 6, 1)) 3277 inc = 2; 3278 break; 3279 } 3280 3281 if (Rm != 0xF) { // Writeback 3282 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3283 return MCDisassembler::Fail; 3284 } 3285 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3286 return MCDisassembler::Fail; 3287 Inst.addOperand(MCOperand::CreateImm(align)); 3288 if (Rm != 0xF) { 3289 if (Rm != 0xD) { 3290 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3291 return MCDisassembler::Fail; 3292 } else 3293 Inst.addOperand(MCOperand::CreateReg(0)); 3294 } 3295 3296 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3297 return MCDisassembler::Fail; 3298 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3299 return MCDisassembler::Fail; 3300 Inst.addOperand(MCOperand::CreateImm(index)); 3301 3302 return S; 3303 } 3304 3305 3306 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 3307 uint64_t Address, const void *Decoder) { 3308 DecodeStatus S = MCDisassembler::Success; 3309 3310 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3311 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3312 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3313 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3314 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3315 3316 unsigned align = 0; 3317 unsigned index = 0; 3318 unsigned inc = 1; 3319 switch (size) { 3320 default: 3321 return MCDisassembler::Fail; 3322 case 0: 3323 if (fieldFromInstruction32(Insn, 4, 1)) 3324 return MCDisassembler::Fail; // UNDEFINED 3325 index = fieldFromInstruction32(Insn, 5, 3); 3326 break; 3327 case 1: 3328 if (fieldFromInstruction32(Insn, 4, 1)) 3329 return MCDisassembler::Fail; // UNDEFINED 3330 index = fieldFromInstruction32(Insn, 6, 2); 3331 if (fieldFromInstruction32(Insn, 5, 1)) 3332 inc = 2; 3333 break; 3334 case 2: 3335 if (fieldFromInstruction32(Insn, 4, 2)) 3336 return MCDisassembler::Fail; // UNDEFINED 3337 index = fieldFromInstruction32(Insn, 7, 1); 3338 if (fieldFromInstruction32(Insn, 6, 1)) 3339 inc = 2; 3340 break; 3341 } 3342 3343 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3344 return MCDisassembler::Fail; 3345 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3346 return MCDisassembler::Fail; 3347 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3348 return MCDisassembler::Fail; 3349 3350 if (Rm != 0xF) { // Writeback 3351 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3352 return MCDisassembler::Fail; 3353 } 3354 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3355 return MCDisassembler::Fail; 3356 Inst.addOperand(MCOperand::CreateImm(align)); 3357 if (Rm != 0xF) { 3358 if (Rm != 0xD) { 3359 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3360 return MCDisassembler::Fail; 3361 } else 3362 Inst.addOperand(MCOperand::CreateReg(0)); 3363 } 3364 3365 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3366 return MCDisassembler::Fail; 3367 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3368 return MCDisassembler::Fail; 3369 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3370 return MCDisassembler::Fail; 3371 Inst.addOperand(MCOperand::CreateImm(index)); 3372 3373 return S; 3374 } 3375 3376 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3377 uint64_t Address, const void *Decoder) { 3378 DecodeStatus S = MCDisassembler::Success; 3379 3380 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3381 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3382 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3383 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3384 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3385 3386 unsigned align = 0; 3387 unsigned index = 0; 3388 unsigned inc = 1; 3389 switch (size) { 3390 default: 3391 return MCDisassembler::Fail; 3392 case 0: 3393 if (fieldFromInstruction32(Insn, 4, 1)) 3394 return MCDisassembler::Fail; // UNDEFINED 3395 index = fieldFromInstruction32(Insn, 5, 3); 3396 break; 3397 case 1: 3398 if (fieldFromInstruction32(Insn, 4, 1)) 3399 return MCDisassembler::Fail; // UNDEFINED 3400 index = fieldFromInstruction32(Insn, 6, 2); 3401 if (fieldFromInstruction32(Insn, 5, 1)) 3402 inc = 2; 3403 break; 3404 case 2: 3405 if (fieldFromInstruction32(Insn, 4, 2)) 3406 return MCDisassembler::Fail; // UNDEFINED 3407 index = fieldFromInstruction32(Insn, 7, 1); 3408 if (fieldFromInstruction32(Insn, 6, 1)) 3409 inc = 2; 3410 break; 3411 } 3412 3413 if (Rm != 0xF) { // Writeback 3414 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3415 return MCDisassembler::Fail; 3416 } 3417 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3418 return MCDisassembler::Fail; 3419 Inst.addOperand(MCOperand::CreateImm(align)); 3420 if (Rm != 0xF) { 3421 if (Rm != 0xD) { 3422 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3423 return MCDisassembler::Fail; 3424 } else 3425 Inst.addOperand(MCOperand::CreateReg(0)); 3426 } 3427 3428 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3429 return MCDisassembler::Fail; 3430 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3431 return MCDisassembler::Fail; 3432 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3433 return MCDisassembler::Fail; 3434 Inst.addOperand(MCOperand::CreateImm(index)); 3435 3436 return S; 3437 } 3438 3439 3440 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3441 uint64_t Address, const void *Decoder) { 3442 DecodeStatus S = MCDisassembler::Success; 3443 3444 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3445 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3446 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3447 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3448 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3449 3450 unsigned align = 0; 3451 unsigned index = 0; 3452 unsigned inc = 1; 3453 switch (size) { 3454 default: 3455 return MCDisassembler::Fail; 3456 case 0: 3457 if (fieldFromInstruction32(Insn, 4, 1)) 3458 align = 4; 3459 index = fieldFromInstruction32(Insn, 5, 3); 3460 break; 3461 case 1: 3462 if (fieldFromInstruction32(Insn, 4, 1)) 3463 align = 8; 3464 index = fieldFromInstruction32(Insn, 6, 2); 3465 if (fieldFromInstruction32(Insn, 5, 1)) 3466 inc = 2; 3467 break; 3468 case 2: 3469 if (fieldFromInstruction32(Insn, 4, 2)) 3470 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3471 index = fieldFromInstruction32(Insn, 7, 1); 3472 if (fieldFromInstruction32(Insn, 6, 1)) 3473 inc = 2; 3474 break; 3475 } 3476 3477 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3478 return MCDisassembler::Fail; 3479 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3480 return MCDisassembler::Fail; 3481 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3482 return MCDisassembler::Fail; 3483 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3484 return MCDisassembler::Fail; 3485 3486 if (Rm != 0xF) { // Writeback 3487 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3488 return MCDisassembler::Fail; 3489 } 3490 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3491 return MCDisassembler::Fail; 3492 Inst.addOperand(MCOperand::CreateImm(align)); 3493 if (Rm != 0xF) { 3494 if (Rm != 0xD) { 3495 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3496 return MCDisassembler::Fail; 3497 } else 3498 Inst.addOperand(MCOperand::CreateReg(0)); 3499 } 3500 3501 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3502 return MCDisassembler::Fail; 3503 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3504 return MCDisassembler::Fail; 3505 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3506 return MCDisassembler::Fail; 3507 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3508 return MCDisassembler::Fail; 3509 Inst.addOperand(MCOperand::CreateImm(index)); 3510 3511 return S; 3512 } 3513 3514 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3515 uint64_t Address, const void *Decoder) { 3516 DecodeStatus S = MCDisassembler::Success; 3517 3518 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3519 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3520 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3521 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3522 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3523 3524 unsigned align = 0; 3525 unsigned index = 0; 3526 unsigned inc = 1; 3527 switch (size) { 3528 default: 3529 return MCDisassembler::Fail; 3530 case 0: 3531 if (fieldFromInstruction32(Insn, 4, 1)) 3532 align = 4; 3533 index = fieldFromInstruction32(Insn, 5, 3); 3534 break; 3535 case 1: 3536 if (fieldFromInstruction32(Insn, 4, 1)) 3537 align = 8; 3538 index = fieldFromInstruction32(Insn, 6, 2); 3539 if (fieldFromInstruction32(Insn, 5, 1)) 3540 inc = 2; 3541 break; 3542 case 2: 3543 if (fieldFromInstruction32(Insn, 4, 2)) 3544 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3545 index = fieldFromInstruction32(Insn, 7, 1); 3546 if (fieldFromInstruction32(Insn, 6, 1)) 3547 inc = 2; 3548 break; 3549 } 3550 3551 if (Rm != 0xF) { // Writeback 3552 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3553 return MCDisassembler::Fail; 3554 } 3555 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3556 return MCDisassembler::Fail; 3557 Inst.addOperand(MCOperand::CreateImm(align)); 3558 if (Rm != 0xF) { 3559 if (Rm != 0xD) { 3560 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3561 return MCDisassembler::Fail; 3562 } else 3563 Inst.addOperand(MCOperand::CreateReg(0)); 3564 } 3565 3566 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3567 return MCDisassembler::Fail; 3568 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3569 return MCDisassembler::Fail; 3570 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3571 return MCDisassembler::Fail; 3572 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3573 return MCDisassembler::Fail; 3574 Inst.addOperand(MCOperand::CreateImm(index)); 3575 3576 return S; 3577 } 3578 3579 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 3580 uint64_t Address, const void *Decoder) { 3581 DecodeStatus S = MCDisassembler::Success; 3582 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3583 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3584 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3585 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3586 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3587 3588 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3589 S = MCDisassembler::SoftFail; 3590 3591 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3592 return MCDisassembler::Fail; 3593 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3594 return MCDisassembler::Fail; 3595 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3596 return MCDisassembler::Fail; 3597 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3598 return MCDisassembler::Fail; 3599 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3600 return MCDisassembler::Fail; 3601 3602 return S; 3603 } 3604 3605 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 3606 uint64_t Address, const void *Decoder) { 3607 DecodeStatus S = MCDisassembler::Success; 3608 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3609 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3610 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3611 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3612 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3613 3614 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3615 S = MCDisassembler::SoftFail; 3616 3617 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3618 return MCDisassembler::Fail; 3619 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3620 return MCDisassembler::Fail; 3621 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3622 return MCDisassembler::Fail; 3623 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3624 return MCDisassembler::Fail; 3625 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3626 return MCDisassembler::Fail; 3627 3628 return S; 3629 } 3630 3631 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn, 3632 uint64_t Address, const void *Decoder) { 3633 DecodeStatus S = MCDisassembler::Success; 3634 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 3635 // The InstPrinter needs to have the low bit of the predicate in 3636 // the mask operand to be able to print it properly. 3637 unsigned mask = fieldFromInstruction16(Insn, 0, 5); 3638 3639 if (pred == 0xF) { 3640 pred = 0xE; 3641 S = MCDisassembler::SoftFail; 3642 } 3643 3644 if ((mask & 0xF) == 0) { 3645 // Preserve the high bit of the mask, which is the low bit of 3646 // the predicate. 3647 mask &= 0x10; 3648 mask |= 0x8; 3649 S = MCDisassembler::SoftFail; 3650 } 3651 3652 Inst.addOperand(MCOperand::CreateImm(pred)); 3653 Inst.addOperand(MCOperand::CreateImm(mask)); 3654 return S; 3655 } 3656 3657 static DecodeStatus 3658 DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3659 uint64_t Address, const void *Decoder) { 3660 DecodeStatus S = MCDisassembler::Success; 3661 3662 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3663 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3664 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3665 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3666 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3667 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3668 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3669 bool writeback = (W == 1) | (P == 0); 3670 3671 addr |= (U << 8) | (Rn << 9); 3672 3673 if (writeback && (Rn == Rt || Rn == Rt2)) 3674 Check(S, MCDisassembler::SoftFail); 3675 if (Rt == Rt2) 3676 Check(S, MCDisassembler::SoftFail); 3677 3678 // Rt 3679 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3680 return MCDisassembler::Fail; 3681 // Rt2 3682 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 3683 return MCDisassembler::Fail; 3684 // Writeback operand 3685 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3686 return MCDisassembler::Fail; 3687 // addr 3688 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 3689 return MCDisassembler::Fail; 3690 3691 return S; 3692 } 3693 3694 static DecodeStatus 3695 DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3696 uint64_t Address, const void *Decoder) { 3697 DecodeStatus S = MCDisassembler::Success; 3698 3699 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3700 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3701 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3702 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3703 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3704 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3705 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3706 bool writeback = (W == 1) | (P == 0); 3707 3708 addr |= (U << 8) | (Rn << 9); 3709 3710 if (writeback && (Rn == Rt || Rn == Rt2)) 3711 Check(S, MCDisassembler::SoftFail); 3712 3713 // Writeback operand 3714 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3715 return MCDisassembler::Fail; 3716 // Rt 3717 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3718 return MCDisassembler::Fail; 3719 // Rt2 3720 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 3721 return MCDisassembler::Fail; 3722 // addr 3723 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 3724 return MCDisassembler::Fail; 3725 3726 return S; 3727 } 3728