1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARM.h" 13 #include "ARMRegisterInfo.h" 14 #include "ARMSubtarget.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCDisassembler.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 28 using namespace llvm; 29 30 typedef MCDisassembler::DecodeStatus DecodeStatus; 31 32 namespace { 33 /// ARMDisassembler - ARM disassembler for all ARM platforms. 34 class ARMDisassembler : public MCDisassembler { 35 public: 36 /// Constructor - Initializes the disassembler. 37 /// 38 ARMDisassembler(const MCSubtargetInfo &STI) : 39 MCDisassembler(STI) { 40 } 41 42 ~ARMDisassembler() { 43 } 44 45 /// getInstruction - See MCDisassembler. 46 DecodeStatus getInstruction(MCInst &instr, 47 uint64_t &size, 48 const MemoryObject ®ion, 49 uint64_t address, 50 raw_ostream &vStream) const; 51 52 /// getEDInfo - See MCDisassembler. 53 EDInstInfo *getEDInfo() const; 54 private: 55 }; 56 57 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 58 class ThumbDisassembler : public MCDisassembler { 59 public: 60 /// Constructor - Initializes the disassembler. 61 /// 62 ThumbDisassembler(const MCSubtargetInfo &STI) : 63 MCDisassembler(STI) { 64 } 65 66 ~ThumbDisassembler() { 67 } 68 69 /// getInstruction - See MCDisassembler. 70 DecodeStatus getInstruction(MCInst &instr, 71 uint64_t &size, 72 const MemoryObject ®ion, 73 uint64_t address, 74 raw_ostream &vStream) const; 75 76 /// getEDInfo - See MCDisassembler. 77 EDInstInfo *getEDInfo() const; 78 private: 79 mutable std::vector<unsigned> ITBlock; 80 void AddThumbPredicate(MCInst&) const; 81 void UpdateThumbVFPPredicate(MCInst&) const; 82 }; 83 } 84 85 static bool Check(DecodeStatus &Out, DecodeStatus In) { 86 switch (In) { 87 case MCDisassembler::Success: 88 // Out stays the same. 89 return true; 90 case MCDisassembler::SoftFail: 91 Out = In; 92 return true; 93 case MCDisassembler::Fail: 94 Out = In; 95 return false; 96 } 97 return false; 98 } 99 100 101 // Forward declare these because the autogenerated code will reference them. 102 // Definitions are further down. 103 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 104 uint64_t Address, const void *Decoder); 105 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 106 unsigned RegNo, uint64_t Address, 107 const void *Decoder); 108 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 109 uint64_t Address, const void *Decoder); 110 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 111 uint64_t Address, const void *Decoder); 112 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 113 uint64_t Address, const void *Decoder); 114 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 115 uint64_t Address, const void *Decoder); 116 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 117 uint64_t Address, const void *Decoder); 118 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 119 uint64_t Address, const void *Decoder); 120 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 121 unsigned RegNo, 122 uint64_t Address, 123 const void *Decoder); 124 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 125 uint64_t Address, const void *Decoder); 126 127 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 128 uint64_t Address, const void *Decoder); 129 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 130 uint64_t Address, const void *Decoder); 131 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 132 uint64_t Address, const void *Decoder); 133 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 134 uint64_t Address, const void *Decoder); 135 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 136 uint64_t Address, const void *Decoder); 137 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 138 uint64_t Address, const void *Decoder); 139 140 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 141 uint64_t Address, const void *Decoder); 142 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 143 uint64_t Address, const void *Decoder); 144 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 145 unsigned Insn, 146 uint64_t Address, 147 const void *Decoder); 148 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 149 uint64_t Address, const void *Decoder); 150 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 151 uint64_t Address, const void *Decoder); 152 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 153 uint64_t Address, const void *Decoder); 154 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 155 uint64_t Address, const void *Decoder); 156 157 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 158 unsigned Insn, 159 uint64_t Adddress, 160 const void *Decoder); 161 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 162 uint64_t Address, const void *Decoder); 163 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 164 uint64_t Address, const void *Decoder); 165 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 166 uint64_t Address, const void *Decoder); 167 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 168 uint64_t Address, const void *Decoder); 169 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 170 uint64_t Address, const void *Decoder); 171 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 172 uint64_t Address, const void *Decoder); 173 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 174 uint64_t Address, const void *Decoder); 175 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 176 uint64_t Address, const void *Decoder); 177 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 186 uint64_t Address, const void *Decoder); 187 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 188 uint64_t Address, const void *Decoder); 189 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 190 uint64_t Address, const void *Decoder); 191 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 192 uint64_t Address, const void *Decoder); 193 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 194 uint64_t Address, const void *Decoder); 195 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 196 uint64_t Address, const void *Decoder); 197 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 198 uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 242 uint64_t Address, const void *Decoder); 243 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 244 uint64_t Address, const void *Decoder); 245 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 246 uint64_t Address, const void *Decoder); 247 248 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val, 295 uint64_t Address, const void *Decoder); 296 297 #include "ARMGenDisassemblerTables.inc" 298 #include "ARMGenInstrInfo.inc" 299 #include "ARMGenEDInfo.inc" 300 301 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 302 return new ARMDisassembler(STI); 303 } 304 305 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 306 return new ThumbDisassembler(STI); 307 } 308 309 EDInstInfo *ARMDisassembler::getEDInfo() const { 310 return instInfoARM; 311 } 312 313 EDInstInfo *ThumbDisassembler::getEDInfo() const { 314 return instInfoARM; 315 } 316 317 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 318 const MemoryObject &Region, 319 uint64_t Address, 320 raw_ostream &os) const { 321 uint8_t bytes[4]; 322 323 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 324 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 325 326 // We want to read exactly 4 bytes of data. 327 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 328 Size = 0; 329 return MCDisassembler::Fail; 330 } 331 332 // Encoded as a small-endian 32-bit word in the stream. 333 uint32_t insn = (bytes[3] << 24) | 334 (bytes[2] << 16) | 335 (bytes[1] << 8) | 336 (bytes[0] << 0); 337 338 // Calling the auto-generated decoder function. 339 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 340 if (result != MCDisassembler::Fail) { 341 Size = 4; 342 return result; 343 } 344 345 // Instructions that are shared between ARM and Thumb modes. 346 // FIXME: This shouldn't really exist. It's an artifact of the 347 // fact that we fail to encode a few instructions properly for Thumb. 348 MI.clear(); 349 result = decodeCommonInstruction32(MI, insn, Address, this, STI); 350 if (result != MCDisassembler::Fail) { 351 Size = 4; 352 return result; 353 } 354 355 // VFP and NEON instructions, similarly, are shared between ARM 356 // and Thumb modes. 357 MI.clear(); 358 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 359 if (result != MCDisassembler::Fail) { 360 Size = 4; 361 return result; 362 } 363 364 MI.clear(); 365 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 366 if (result != MCDisassembler::Fail) { 367 Size = 4; 368 // Add a fake predicate operand, because we share these instruction 369 // definitions with Thumb2 where these instructions are predicable. 370 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 371 return MCDisassembler::Fail; 372 return result; 373 } 374 375 MI.clear(); 376 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 377 if (result != MCDisassembler::Fail) { 378 Size = 4; 379 // Add a fake predicate operand, because we share these instruction 380 // definitions with Thumb2 where these instructions are predicable. 381 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 382 return MCDisassembler::Fail; 383 return result; 384 } 385 386 MI.clear(); 387 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 388 if (result != MCDisassembler::Fail) { 389 Size = 4; 390 // Add a fake predicate operand, because we share these instruction 391 // definitions with Thumb2 where these instructions are predicable. 392 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 393 return MCDisassembler::Fail; 394 return result; 395 } 396 397 MI.clear(); 398 399 Size = 0; 400 return MCDisassembler::Fail; 401 } 402 403 namespace llvm { 404 extern MCInstrDesc ARMInsts[]; 405 } 406 407 // Thumb1 instructions don't have explicit S bits. Rather, they 408 // implicitly set CPSR. Since it's not represented in the encoding, the 409 // auto-generated decoder won't inject the CPSR operand. We need to fix 410 // that as a post-pass. 411 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 412 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 413 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 414 MCInst::iterator I = MI.begin(); 415 for (unsigned i = 0; i < NumOps; ++i, ++I) { 416 if (I == MI.end()) break; 417 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 418 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 419 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 420 return; 421 } 422 } 423 424 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 425 } 426 427 // Most Thumb instructions don't have explicit predicates in the 428 // encoding, but rather get their predicates from IT context. We need 429 // to fix up the predicate operands using this context information as a 430 // post-pass. 431 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 432 // A few instructions actually have predicates encoded in them. Don't 433 // try to overwrite it if we're seeing one of those. 434 switch (MI.getOpcode()) { 435 case ARM::tBcc: 436 case ARM::t2Bcc: 437 return; 438 default: 439 break; 440 } 441 442 // If we're in an IT block, base the predicate on that. Otherwise, 443 // assume a predicate of AL. 444 unsigned CC; 445 if (!ITBlock.empty()) { 446 CC = ITBlock.back(); 447 if (CC == 0xF) 448 CC = ARMCC::AL; 449 ITBlock.pop_back(); 450 } else 451 CC = ARMCC::AL; 452 453 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 454 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 455 MCInst::iterator I = MI.begin(); 456 for (unsigned i = 0; i < NumOps; ++i, ++I) { 457 if (I == MI.end()) break; 458 if (OpInfo[i].isPredicate()) { 459 I = MI.insert(I, MCOperand::CreateImm(CC)); 460 ++I; 461 if (CC == ARMCC::AL) 462 MI.insert(I, MCOperand::CreateReg(0)); 463 else 464 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 465 return; 466 } 467 } 468 469 I = MI.insert(I, MCOperand::CreateImm(CC)); 470 ++I; 471 if (CC == ARMCC::AL) 472 MI.insert(I, MCOperand::CreateReg(0)); 473 else 474 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 475 } 476 477 // Thumb VFP instructions are a special case. Because we share their 478 // encodings between ARM and Thumb modes, and they are predicable in ARM 479 // mode, the auto-generated decoder will give them an (incorrect) 480 // predicate operand. We need to rewrite these operands based on the IT 481 // context as a post-pass. 482 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 483 unsigned CC; 484 if (!ITBlock.empty()) { 485 CC = ITBlock.back(); 486 ITBlock.pop_back(); 487 } else 488 CC = ARMCC::AL; 489 490 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 491 MCInst::iterator I = MI.begin(); 492 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 493 for (unsigned i = 0; i < NumOps; ++i, ++I) { 494 if (OpInfo[i].isPredicate() ) { 495 I->setImm(CC); 496 ++I; 497 if (CC == ARMCC::AL) 498 I->setReg(0); 499 else 500 I->setReg(ARM::CPSR); 501 return; 502 } 503 } 504 } 505 506 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 507 const MemoryObject &Region, 508 uint64_t Address, 509 raw_ostream &os) const { 510 uint8_t bytes[4]; 511 512 assert((STI.getFeatureBits() & ARM::ModeThumb) && 513 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 514 515 // We want to read exactly 2 bytes of data. 516 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 517 Size = 0; 518 return MCDisassembler::Fail; 519 } 520 521 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 522 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 523 if (result != MCDisassembler::Fail) { 524 Size = 2; 525 AddThumbPredicate(MI); 526 return result; 527 } 528 529 MI.clear(); 530 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 531 if (result) { 532 Size = 2; 533 bool InITBlock = !ITBlock.empty(); 534 AddThumbPredicate(MI); 535 AddThumb1SBit(MI, InITBlock); 536 return result; 537 } 538 539 MI.clear(); 540 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 541 if (result != MCDisassembler::Fail) { 542 Size = 2; 543 AddThumbPredicate(MI); 544 545 // If we find an IT instruction, we need to parse its condition 546 // code and mask operands so that we can apply them correctly 547 // to the subsequent instructions. 548 if (MI.getOpcode() == ARM::t2IT) { 549 // (3 - the number of trailing zeros) is the number of then / else. 550 unsigned firstcond = MI.getOperand(0).getImm(); 551 unsigned Mask = MI.getOperand(1).getImm(); 552 unsigned CondBit0 = Mask >> 4 & 1; 553 unsigned NumTZ = CountTrailingZeros_32(Mask); 554 assert(NumTZ <= 3 && "Invalid IT mask!"); 555 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 556 bool T = ((Mask >> Pos) & 1) == CondBit0; 557 if (T) 558 ITBlock.insert(ITBlock.begin(), firstcond); 559 else 560 ITBlock.insert(ITBlock.begin(), firstcond ^ 1); 561 } 562 563 ITBlock.push_back(firstcond); 564 } 565 566 return result; 567 } 568 569 // We want to read exactly 4 bytes of data. 570 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 571 Size = 0; 572 return MCDisassembler::Fail; 573 } 574 575 uint32_t insn32 = (bytes[3] << 8) | 576 (bytes[2] << 0) | 577 (bytes[1] << 24) | 578 (bytes[0] << 16); 579 MI.clear(); 580 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 581 if (result != MCDisassembler::Fail) { 582 Size = 4; 583 bool InITBlock = ITBlock.size(); 584 AddThumbPredicate(MI); 585 AddThumb1SBit(MI, InITBlock); 586 return result; 587 } 588 589 MI.clear(); 590 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 591 if (result != MCDisassembler::Fail) { 592 Size = 4; 593 AddThumbPredicate(MI); 594 return result; 595 } 596 597 MI.clear(); 598 result = decodeCommonInstruction32(MI, insn32, Address, this, STI); 599 if (result != MCDisassembler::Fail) { 600 Size = 4; 601 AddThumbPredicate(MI); 602 return result; 603 } 604 605 MI.clear(); 606 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 607 if (result != MCDisassembler::Fail) { 608 Size = 4; 609 UpdateThumbVFPPredicate(MI); 610 return result; 611 } 612 613 MI.clear(); 614 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 615 if (result != MCDisassembler::Fail) { 616 Size = 4; 617 AddThumbPredicate(MI); 618 return result; 619 } 620 621 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 622 MI.clear(); 623 uint32_t NEONLdStInsn = insn32; 624 NEONLdStInsn &= 0xF0FFFFFF; 625 NEONLdStInsn |= 0x04000000; 626 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 627 if (result != MCDisassembler::Fail) { 628 Size = 4; 629 AddThumbPredicate(MI); 630 return result; 631 } 632 } 633 634 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 635 MI.clear(); 636 uint32_t NEONDataInsn = insn32; 637 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 638 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 639 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 640 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 641 if (result != MCDisassembler::Fail) { 642 Size = 4; 643 AddThumbPredicate(MI); 644 return result; 645 } 646 } 647 648 Size = 0; 649 return MCDisassembler::Fail; 650 } 651 652 653 extern "C" void LLVMInitializeARMDisassembler() { 654 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 655 createARMDisassembler); 656 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 657 createThumbDisassembler); 658 } 659 660 static const unsigned GPRDecoderTable[] = { 661 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 662 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 663 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 664 ARM::R12, ARM::SP, ARM::LR, ARM::PC 665 }; 666 667 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 668 uint64_t Address, const void *Decoder) { 669 if (RegNo > 15) 670 return MCDisassembler::Fail; 671 672 unsigned Register = GPRDecoderTable[RegNo]; 673 Inst.addOperand(MCOperand::CreateReg(Register)); 674 return MCDisassembler::Success; 675 } 676 677 static DecodeStatus 678 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 679 uint64_t Address, const void *Decoder) { 680 if (RegNo == 15) return MCDisassembler::Fail; 681 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 682 } 683 684 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 685 uint64_t Address, const void *Decoder) { 686 if (RegNo > 7) 687 return MCDisassembler::Fail; 688 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 689 } 690 691 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 692 uint64_t Address, const void *Decoder) { 693 unsigned Register = 0; 694 switch (RegNo) { 695 case 0: 696 Register = ARM::R0; 697 break; 698 case 1: 699 Register = ARM::R1; 700 break; 701 case 2: 702 Register = ARM::R2; 703 break; 704 case 3: 705 Register = ARM::R3; 706 break; 707 case 9: 708 Register = ARM::R9; 709 break; 710 case 12: 711 Register = ARM::R12; 712 break; 713 default: 714 return MCDisassembler::Fail; 715 } 716 717 Inst.addOperand(MCOperand::CreateReg(Register)); 718 return MCDisassembler::Success; 719 } 720 721 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 722 uint64_t Address, const void *Decoder) { 723 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 724 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 725 } 726 727 static const unsigned SPRDecoderTable[] = { 728 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 729 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 730 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 731 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 732 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 733 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 734 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 735 ARM::S28, ARM::S29, ARM::S30, ARM::S31 736 }; 737 738 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 739 uint64_t Address, const void *Decoder) { 740 if (RegNo > 31) 741 return MCDisassembler::Fail; 742 743 unsigned Register = SPRDecoderTable[RegNo]; 744 Inst.addOperand(MCOperand::CreateReg(Register)); 745 return MCDisassembler::Success; 746 } 747 748 static const unsigned DPRDecoderTable[] = { 749 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 750 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 751 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 752 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 753 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 754 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 755 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 756 ARM::D28, ARM::D29, ARM::D30, ARM::D31 757 }; 758 759 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 760 uint64_t Address, const void *Decoder) { 761 if (RegNo > 31) 762 return MCDisassembler::Fail; 763 764 unsigned Register = DPRDecoderTable[RegNo]; 765 Inst.addOperand(MCOperand::CreateReg(Register)); 766 return MCDisassembler::Success; 767 } 768 769 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 770 uint64_t Address, const void *Decoder) { 771 if (RegNo > 7) 772 return MCDisassembler::Fail; 773 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 774 } 775 776 static DecodeStatus 777 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 778 uint64_t Address, const void *Decoder) { 779 if (RegNo > 15) 780 return MCDisassembler::Fail; 781 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 782 } 783 784 static const unsigned QPRDecoderTable[] = { 785 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 786 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 787 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 788 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 789 }; 790 791 792 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 793 uint64_t Address, const void *Decoder) { 794 if (RegNo > 31) 795 return MCDisassembler::Fail; 796 RegNo >>= 1; 797 798 unsigned Register = QPRDecoderTable[RegNo]; 799 Inst.addOperand(MCOperand::CreateReg(Register)); 800 return MCDisassembler::Success; 801 } 802 803 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 804 uint64_t Address, const void *Decoder) { 805 if (Val == 0xF) return MCDisassembler::Fail; 806 // AL predicate is not allowed on Thumb1 branches. 807 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 808 return MCDisassembler::Fail; 809 Inst.addOperand(MCOperand::CreateImm(Val)); 810 if (Val == ARMCC::AL) { 811 Inst.addOperand(MCOperand::CreateReg(0)); 812 } else 813 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 814 return MCDisassembler::Success; 815 } 816 817 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 818 uint64_t Address, const void *Decoder) { 819 if (Val) 820 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 821 else 822 Inst.addOperand(MCOperand::CreateReg(0)); 823 return MCDisassembler::Success; 824 } 825 826 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 827 uint64_t Address, const void *Decoder) { 828 uint32_t imm = Val & 0xFF; 829 uint32_t rot = (Val & 0xF00) >> 7; 830 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 831 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 832 return MCDisassembler::Success; 833 } 834 835 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 836 uint64_t Address, const void *Decoder) { 837 DecodeStatus S = MCDisassembler::Success; 838 839 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 840 unsigned type = fieldFromInstruction32(Val, 5, 2); 841 unsigned imm = fieldFromInstruction32(Val, 7, 5); 842 843 // Register-immediate 844 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 845 return MCDisassembler::Fail; 846 847 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 848 switch (type) { 849 case 0: 850 Shift = ARM_AM::lsl; 851 break; 852 case 1: 853 Shift = ARM_AM::lsr; 854 break; 855 case 2: 856 Shift = ARM_AM::asr; 857 break; 858 case 3: 859 Shift = ARM_AM::ror; 860 break; 861 } 862 863 if (Shift == ARM_AM::ror && imm == 0) 864 Shift = ARM_AM::rrx; 865 866 unsigned Op = Shift | (imm << 3); 867 Inst.addOperand(MCOperand::CreateImm(Op)); 868 869 return S; 870 } 871 872 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 873 uint64_t Address, const void *Decoder) { 874 DecodeStatus S = MCDisassembler::Success; 875 876 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 877 unsigned type = fieldFromInstruction32(Val, 5, 2); 878 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 879 880 // Register-register 881 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 882 return MCDisassembler::Fail; 883 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 884 return MCDisassembler::Fail; 885 886 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 887 switch (type) { 888 case 0: 889 Shift = ARM_AM::lsl; 890 break; 891 case 1: 892 Shift = ARM_AM::lsr; 893 break; 894 case 2: 895 Shift = ARM_AM::asr; 896 break; 897 case 3: 898 Shift = ARM_AM::ror; 899 break; 900 } 901 902 Inst.addOperand(MCOperand::CreateImm(Shift)); 903 904 return S; 905 } 906 907 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 908 uint64_t Address, const void *Decoder) { 909 DecodeStatus S = MCDisassembler::Success; 910 911 // Empty register lists are not allowed. 912 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 913 for (unsigned i = 0; i < 16; ++i) { 914 if (Val & (1 << i)) { 915 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 916 return MCDisassembler::Fail; 917 } 918 } 919 920 return S; 921 } 922 923 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 924 uint64_t Address, const void *Decoder) { 925 DecodeStatus S = MCDisassembler::Success; 926 927 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 928 unsigned regs = Val & 0xFF; 929 930 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 931 return MCDisassembler::Fail; 932 for (unsigned i = 0; i < (regs - 1); ++i) { 933 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 934 return MCDisassembler::Fail; 935 } 936 937 return S; 938 } 939 940 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 941 uint64_t Address, const void *Decoder) { 942 DecodeStatus S = MCDisassembler::Success; 943 944 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 945 unsigned regs = (Val & 0xFF) / 2; 946 947 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 948 return MCDisassembler::Fail; 949 for (unsigned i = 0; i < (regs - 1); ++i) { 950 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 951 return MCDisassembler::Fail; 952 } 953 954 return S; 955 } 956 957 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 958 uint64_t Address, const void *Decoder) { 959 // This operand encodes a mask of contiguous zeros between a specified MSB 960 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 961 // the mask of all bits LSB-and-lower, and then xor them to create 962 // the mask of that's all ones on [msb, lsb]. Finally we not it to 963 // create the final mask. 964 unsigned msb = fieldFromInstruction32(Val, 5, 5); 965 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 966 uint32_t msb_mask = (1 << (msb+1)) - 1; 967 uint32_t lsb_mask = (1 << lsb) - 1; 968 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 969 return MCDisassembler::Success; 970 } 971 972 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 973 uint64_t Address, const void *Decoder) { 974 DecodeStatus S = MCDisassembler::Success; 975 976 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 977 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 978 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 979 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 980 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 981 unsigned U = fieldFromInstruction32(Insn, 23, 1); 982 983 switch (Inst.getOpcode()) { 984 case ARM::LDC_OFFSET: 985 case ARM::LDC_PRE: 986 case ARM::LDC_POST: 987 case ARM::LDC_OPTION: 988 case ARM::LDCL_OFFSET: 989 case ARM::LDCL_PRE: 990 case ARM::LDCL_POST: 991 case ARM::LDCL_OPTION: 992 case ARM::STC_OFFSET: 993 case ARM::STC_PRE: 994 case ARM::STC_POST: 995 case ARM::STC_OPTION: 996 case ARM::STCL_OFFSET: 997 case ARM::STCL_PRE: 998 case ARM::STCL_POST: 999 case ARM::STCL_OPTION: 1000 if (coproc == 0xA || coproc == 0xB) 1001 return MCDisassembler::Fail; 1002 break; 1003 default: 1004 break; 1005 } 1006 1007 Inst.addOperand(MCOperand::CreateImm(coproc)); 1008 Inst.addOperand(MCOperand::CreateImm(CRd)); 1009 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1010 return MCDisassembler::Fail; 1011 switch (Inst.getOpcode()) { 1012 case ARM::LDC_OPTION: 1013 case ARM::LDCL_OPTION: 1014 case ARM::LDC2_OPTION: 1015 case ARM::LDC2L_OPTION: 1016 case ARM::STC_OPTION: 1017 case ARM::STCL_OPTION: 1018 case ARM::STC2_OPTION: 1019 case ARM::STC2L_OPTION: 1020 case ARM::LDCL_POST: 1021 case ARM::STCL_POST: 1022 case ARM::LDC2L_POST: 1023 case ARM::STC2L_POST: 1024 break; 1025 default: 1026 Inst.addOperand(MCOperand::CreateReg(0)); 1027 break; 1028 } 1029 1030 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1031 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1032 1033 bool writeback = (P == 0) || (W == 1); 1034 unsigned idx_mode = 0; 1035 if (P && writeback) 1036 idx_mode = ARMII::IndexModePre; 1037 else if (!P && writeback) 1038 idx_mode = ARMII::IndexModePost; 1039 1040 switch (Inst.getOpcode()) { 1041 case ARM::LDCL_POST: 1042 case ARM::STCL_POST: 1043 case ARM::LDC2L_POST: 1044 case ARM::STC2L_POST: 1045 imm |= U << 8; 1046 case ARM::LDC_OPTION: 1047 case ARM::LDCL_OPTION: 1048 case ARM::LDC2_OPTION: 1049 case ARM::LDC2L_OPTION: 1050 case ARM::STC_OPTION: 1051 case ARM::STCL_OPTION: 1052 case ARM::STC2_OPTION: 1053 case ARM::STC2L_OPTION: 1054 Inst.addOperand(MCOperand::CreateImm(imm)); 1055 break; 1056 default: 1057 if (U) 1058 Inst.addOperand(MCOperand::CreateImm( 1059 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 1060 else 1061 Inst.addOperand(MCOperand::CreateImm( 1062 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 1063 break; 1064 } 1065 1066 switch (Inst.getOpcode()) { 1067 case ARM::LDC_OFFSET: 1068 case ARM::LDC_PRE: 1069 case ARM::LDC_POST: 1070 case ARM::LDC_OPTION: 1071 case ARM::LDCL_OFFSET: 1072 case ARM::LDCL_PRE: 1073 case ARM::LDCL_POST: 1074 case ARM::LDCL_OPTION: 1075 case ARM::STC_OFFSET: 1076 case ARM::STC_PRE: 1077 case ARM::STC_POST: 1078 case ARM::STC_OPTION: 1079 case ARM::STCL_OFFSET: 1080 case ARM::STCL_PRE: 1081 case ARM::STCL_POST: 1082 case ARM::STCL_OPTION: 1083 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1084 return MCDisassembler::Fail; 1085 break; 1086 default: 1087 break; 1088 } 1089 1090 return S; 1091 } 1092 1093 static DecodeStatus 1094 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 1095 uint64_t Address, const void *Decoder) { 1096 DecodeStatus S = MCDisassembler::Success; 1097 1098 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1099 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1100 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1101 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1102 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1103 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1104 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1105 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1106 1107 // On stores, the writeback operand precedes Rt. 1108 switch (Inst.getOpcode()) { 1109 case ARM::STR_POST_IMM: 1110 case ARM::STR_POST_REG: 1111 case ARM::STRB_POST_IMM: 1112 case ARM::STRB_POST_REG: 1113 case ARM::STRT_POST_REG: 1114 case ARM::STRT_POST_IMM: 1115 case ARM::STRBT_POST_REG: 1116 case ARM::STRBT_POST_IMM: 1117 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1118 return MCDisassembler::Fail; 1119 break; 1120 default: 1121 break; 1122 } 1123 1124 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1125 return MCDisassembler::Fail; 1126 1127 // On loads, the writeback operand comes after Rt. 1128 switch (Inst.getOpcode()) { 1129 case ARM::LDR_POST_IMM: 1130 case ARM::LDR_POST_REG: 1131 case ARM::LDRB_POST_IMM: 1132 case ARM::LDRB_POST_REG: 1133 case ARM::LDRBT_POST_REG: 1134 case ARM::LDRBT_POST_IMM: 1135 case ARM::LDRT_POST_REG: 1136 case ARM::LDRT_POST_IMM: 1137 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1138 return MCDisassembler::Fail; 1139 break; 1140 default: 1141 break; 1142 } 1143 1144 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1145 return MCDisassembler::Fail; 1146 1147 ARM_AM::AddrOpc Op = ARM_AM::add; 1148 if (!fieldFromInstruction32(Insn, 23, 1)) 1149 Op = ARM_AM::sub; 1150 1151 bool writeback = (P == 0) || (W == 1); 1152 unsigned idx_mode = 0; 1153 if (P && writeback) 1154 idx_mode = ARMII::IndexModePre; 1155 else if (!P && writeback) 1156 idx_mode = ARMII::IndexModePost; 1157 1158 if (writeback && (Rn == 15 || Rn == Rt)) 1159 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1160 1161 if (reg) { 1162 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1163 return MCDisassembler::Fail; 1164 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1165 switch( fieldFromInstruction32(Insn, 5, 2)) { 1166 case 0: 1167 Opc = ARM_AM::lsl; 1168 break; 1169 case 1: 1170 Opc = ARM_AM::lsr; 1171 break; 1172 case 2: 1173 Opc = ARM_AM::asr; 1174 break; 1175 case 3: 1176 Opc = ARM_AM::ror; 1177 break; 1178 default: 1179 return MCDisassembler::Fail; 1180 } 1181 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1182 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1183 1184 Inst.addOperand(MCOperand::CreateImm(imm)); 1185 } else { 1186 Inst.addOperand(MCOperand::CreateReg(0)); 1187 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1188 Inst.addOperand(MCOperand::CreateImm(tmp)); 1189 } 1190 1191 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1192 return MCDisassembler::Fail; 1193 1194 return S; 1195 } 1196 1197 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1198 uint64_t Address, const void *Decoder) { 1199 DecodeStatus S = MCDisassembler::Success; 1200 1201 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1202 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1203 unsigned type = fieldFromInstruction32(Val, 5, 2); 1204 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1205 unsigned U = fieldFromInstruction32(Val, 12, 1); 1206 1207 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1208 switch (type) { 1209 case 0: 1210 ShOp = ARM_AM::lsl; 1211 break; 1212 case 1: 1213 ShOp = ARM_AM::lsr; 1214 break; 1215 case 2: 1216 ShOp = ARM_AM::asr; 1217 break; 1218 case 3: 1219 ShOp = ARM_AM::ror; 1220 break; 1221 } 1222 1223 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1224 return MCDisassembler::Fail; 1225 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1226 return MCDisassembler::Fail; 1227 unsigned shift; 1228 if (U) 1229 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1230 else 1231 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1232 Inst.addOperand(MCOperand::CreateImm(shift)); 1233 1234 return S; 1235 } 1236 1237 static DecodeStatus 1238 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1239 uint64_t Address, const void *Decoder) { 1240 DecodeStatus S = MCDisassembler::Success; 1241 1242 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1243 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1244 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1245 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1246 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1247 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1248 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1249 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1250 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1251 1252 bool writeback = (W == 1) | (P == 0); 1253 1254 // For {LD,ST}RD, Rt must be even, else undefined. 1255 switch (Inst.getOpcode()) { 1256 case ARM::STRD: 1257 case ARM::STRD_PRE: 1258 case ARM::STRD_POST: 1259 case ARM::LDRD: 1260 case ARM::LDRD_PRE: 1261 case ARM::LDRD_POST: 1262 if (Rt & 0x1) return MCDisassembler::Fail; 1263 break; 1264 default: 1265 break; 1266 } 1267 1268 if (writeback) { // Writeback 1269 if (P) 1270 U |= ARMII::IndexModePre << 9; 1271 else 1272 U |= ARMII::IndexModePost << 9; 1273 1274 // On stores, the writeback operand precedes Rt. 1275 switch (Inst.getOpcode()) { 1276 case ARM::STRD: 1277 case ARM::STRD_PRE: 1278 case ARM::STRD_POST: 1279 case ARM::STRH: 1280 case ARM::STRH_PRE: 1281 case ARM::STRH_POST: 1282 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1283 return MCDisassembler::Fail; 1284 break; 1285 default: 1286 break; 1287 } 1288 } 1289 1290 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1291 return MCDisassembler::Fail; 1292 switch (Inst.getOpcode()) { 1293 case ARM::STRD: 1294 case ARM::STRD_PRE: 1295 case ARM::STRD_POST: 1296 case ARM::LDRD: 1297 case ARM::LDRD_PRE: 1298 case ARM::LDRD_POST: 1299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1300 return MCDisassembler::Fail; 1301 break; 1302 default: 1303 break; 1304 } 1305 1306 if (writeback) { 1307 // On loads, the writeback operand comes after Rt. 1308 switch (Inst.getOpcode()) { 1309 case ARM::LDRD: 1310 case ARM::LDRD_PRE: 1311 case ARM::LDRD_POST: 1312 case ARM::LDRH: 1313 case ARM::LDRH_PRE: 1314 case ARM::LDRH_POST: 1315 case ARM::LDRSH: 1316 case ARM::LDRSH_PRE: 1317 case ARM::LDRSH_POST: 1318 case ARM::LDRSB: 1319 case ARM::LDRSB_PRE: 1320 case ARM::LDRSB_POST: 1321 case ARM::LDRHTr: 1322 case ARM::LDRSBTr: 1323 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1324 return MCDisassembler::Fail; 1325 break; 1326 default: 1327 break; 1328 } 1329 } 1330 1331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1332 return MCDisassembler::Fail; 1333 1334 if (type) { 1335 Inst.addOperand(MCOperand::CreateReg(0)); 1336 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1337 } else { 1338 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1339 return MCDisassembler::Fail; 1340 Inst.addOperand(MCOperand::CreateImm(U)); 1341 } 1342 1343 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1344 return MCDisassembler::Fail; 1345 1346 return S; 1347 } 1348 1349 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1350 uint64_t Address, const void *Decoder) { 1351 DecodeStatus S = MCDisassembler::Success; 1352 1353 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1354 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1355 1356 switch (mode) { 1357 case 0: 1358 mode = ARM_AM::da; 1359 break; 1360 case 1: 1361 mode = ARM_AM::ia; 1362 break; 1363 case 2: 1364 mode = ARM_AM::db; 1365 break; 1366 case 3: 1367 mode = ARM_AM::ib; 1368 break; 1369 } 1370 1371 Inst.addOperand(MCOperand::CreateImm(mode)); 1372 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1373 return MCDisassembler::Fail; 1374 1375 return S; 1376 } 1377 1378 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1379 unsigned Insn, 1380 uint64_t Address, const void *Decoder) { 1381 DecodeStatus S = MCDisassembler::Success; 1382 1383 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1384 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1385 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1386 1387 if (pred == 0xF) { 1388 switch (Inst.getOpcode()) { 1389 case ARM::LDMDA: 1390 Inst.setOpcode(ARM::RFEDA); 1391 break; 1392 case ARM::LDMDA_UPD: 1393 Inst.setOpcode(ARM::RFEDA_UPD); 1394 break; 1395 case ARM::LDMDB: 1396 Inst.setOpcode(ARM::RFEDB); 1397 break; 1398 case ARM::LDMDB_UPD: 1399 Inst.setOpcode(ARM::RFEDB_UPD); 1400 break; 1401 case ARM::LDMIA: 1402 Inst.setOpcode(ARM::RFEIA); 1403 break; 1404 case ARM::LDMIA_UPD: 1405 Inst.setOpcode(ARM::RFEIA_UPD); 1406 break; 1407 case ARM::LDMIB: 1408 Inst.setOpcode(ARM::RFEIB); 1409 break; 1410 case ARM::LDMIB_UPD: 1411 Inst.setOpcode(ARM::RFEIB_UPD); 1412 break; 1413 case ARM::STMDA: 1414 Inst.setOpcode(ARM::SRSDA); 1415 break; 1416 case ARM::STMDA_UPD: 1417 Inst.setOpcode(ARM::SRSDA_UPD); 1418 break; 1419 case ARM::STMDB: 1420 Inst.setOpcode(ARM::SRSDB); 1421 break; 1422 case ARM::STMDB_UPD: 1423 Inst.setOpcode(ARM::SRSDB_UPD); 1424 break; 1425 case ARM::STMIA: 1426 Inst.setOpcode(ARM::SRSIA); 1427 break; 1428 case ARM::STMIA_UPD: 1429 Inst.setOpcode(ARM::SRSIA_UPD); 1430 break; 1431 case ARM::STMIB: 1432 Inst.setOpcode(ARM::SRSIB); 1433 break; 1434 case ARM::STMIB_UPD: 1435 Inst.setOpcode(ARM::SRSIB_UPD); 1436 break; 1437 default: 1438 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1439 } 1440 1441 // For stores (which become SRS's, the only operand is the mode. 1442 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1443 Inst.addOperand( 1444 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1445 return S; 1446 } 1447 1448 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1449 } 1450 1451 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1452 return MCDisassembler::Fail; 1453 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1454 return MCDisassembler::Fail; // Tied 1455 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1456 return MCDisassembler::Fail; 1457 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1458 return MCDisassembler::Fail; 1459 1460 return S; 1461 } 1462 1463 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1464 uint64_t Address, const void *Decoder) { 1465 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1466 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1467 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1468 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1469 1470 DecodeStatus S = MCDisassembler::Success; 1471 1472 // imod == '01' --> UNPREDICTABLE 1473 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1474 // return failure here. The '01' imod value is unprintable, so there's 1475 // nothing useful we could do even if we returned UNPREDICTABLE. 1476 1477 if (imod == 1) return MCDisassembler::Fail; 1478 1479 if (imod && M) { 1480 Inst.setOpcode(ARM::CPS3p); 1481 Inst.addOperand(MCOperand::CreateImm(imod)); 1482 Inst.addOperand(MCOperand::CreateImm(iflags)); 1483 Inst.addOperand(MCOperand::CreateImm(mode)); 1484 } else if (imod && !M) { 1485 Inst.setOpcode(ARM::CPS2p); 1486 Inst.addOperand(MCOperand::CreateImm(imod)); 1487 Inst.addOperand(MCOperand::CreateImm(iflags)); 1488 if (mode) S = MCDisassembler::SoftFail; 1489 } else if (!imod && M) { 1490 Inst.setOpcode(ARM::CPS1p); 1491 Inst.addOperand(MCOperand::CreateImm(mode)); 1492 if (iflags) S = MCDisassembler::SoftFail; 1493 } else { 1494 // imod == '00' && M == '0' --> UNPREDICTABLE 1495 Inst.setOpcode(ARM::CPS1p); 1496 Inst.addOperand(MCOperand::CreateImm(mode)); 1497 S = MCDisassembler::SoftFail; 1498 } 1499 1500 return S; 1501 } 1502 1503 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1504 uint64_t Address, const void *Decoder) { 1505 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1506 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1507 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1508 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1509 1510 DecodeStatus S = MCDisassembler::Success; 1511 1512 // imod == '01' --> UNPREDICTABLE 1513 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1514 // return failure here. The '01' imod value is unprintable, so there's 1515 // nothing useful we could do even if we returned UNPREDICTABLE. 1516 1517 if (imod == 1) return MCDisassembler::Fail; 1518 1519 if (imod && M) { 1520 Inst.setOpcode(ARM::t2CPS3p); 1521 Inst.addOperand(MCOperand::CreateImm(imod)); 1522 Inst.addOperand(MCOperand::CreateImm(iflags)); 1523 Inst.addOperand(MCOperand::CreateImm(mode)); 1524 } else if (imod && !M) { 1525 Inst.setOpcode(ARM::t2CPS2p); 1526 Inst.addOperand(MCOperand::CreateImm(imod)); 1527 Inst.addOperand(MCOperand::CreateImm(iflags)); 1528 if (mode) S = MCDisassembler::SoftFail; 1529 } else if (!imod && M) { 1530 Inst.setOpcode(ARM::t2CPS1p); 1531 Inst.addOperand(MCOperand::CreateImm(mode)); 1532 if (iflags) S = MCDisassembler::SoftFail; 1533 } else { 1534 // imod == '00' && M == '0' --> UNPREDICTABLE 1535 Inst.setOpcode(ARM::t2CPS1p); 1536 Inst.addOperand(MCOperand::CreateImm(mode)); 1537 S = MCDisassembler::SoftFail; 1538 } 1539 1540 return S; 1541 } 1542 1543 1544 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1545 uint64_t Address, const void *Decoder) { 1546 DecodeStatus S = MCDisassembler::Success; 1547 1548 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1549 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1550 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1551 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1552 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1553 1554 if (pred == 0xF) 1555 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1556 1557 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1558 return MCDisassembler::Fail; 1559 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1560 return MCDisassembler::Fail; 1561 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1562 return MCDisassembler::Fail; 1563 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1564 return MCDisassembler::Fail; 1565 1566 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1567 return MCDisassembler::Fail; 1568 1569 return S; 1570 } 1571 1572 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1573 uint64_t Address, const void *Decoder) { 1574 DecodeStatus S = MCDisassembler::Success; 1575 1576 unsigned add = fieldFromInstruction32(Val, 12, 1); 1577 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1578 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1579 1580 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1581 return MCDisassembler::Fail; 1582 1583 if (!add) imm *= -1; 1584 if (imm == 0 && !add) imm = INT32_MIN; 1585 Inst.addOperand(MCOperand::CreateImm(imm)); 1586 1587 return S; 1588 } 1589 1590 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1591 uint64_t Address, const void *Decoder) { 1592 DecodeStatus S = MCDisassembler::Success; 1593 1594 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1595 unsigned U = fieldFromInstruction32(Val, 8, 1); 1596 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1597 1598 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1599 return MCDisassembler::Fail; 1600 1601 if (U) 1602 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1603 else 1604 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1605 1606 return S; 1607 } 1608 1609 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1610 uint64_t Address, const void *Decoder) { 1611 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1612 } 1613 1614 static DecodeStatus 1615 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1616 uint64_t Address, const void *Decoder) { 1617 DecodeStatus S = MCDisassembler::Success; 1618 1619 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1620 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1621 1622 if (pred == 0xF) { 1623 Inst.setOpcode(ARM::BLXi); 1624 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1625 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1626 return S; 1627 } 1628 1629 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1630 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1631 return MCDisassembler::Fail; 1632 1633 return S; 1634 } 1635 1636 1637 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1638 uint64_t Address, const void *Decoder) { 1639 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1640 return MCDisassembler::Success; 1641 } 1642 1643 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1644 uint64_t Address, const void *Decoder) { 1645 DecodeStatus S = MCDisassembler::Success; 1646 1647 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1648 unsigned align = fieldFromInstruction32(Val, 4, 2); 1649 1650 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1651 return MCDisassembler::Fail; 1652 if (!align) 1653 Inst.addOperand(MCOperand::CreateImm(0)); 1654 else 1655 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1656 1657 return S; 1658 } 1659 1660 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1661 uint64_t Address, const void *Decoder) { 1662 DecodeStatus S = MCDisassembler::Success; 1663 1664 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1665 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1666 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1667 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1668 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1669 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1670 1671 // First output register 1672 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 1673 return MCDisassembler::Fail; 1674 1675 // Second output register 1676 switch (Inst.getOpcode()) { 1677 case ARM::VLD1q8: 1678 case ARM::VLD1q16: 1679 case ARM::VLD1q32: 1680 case ARM::VLD1q64: 1681 case ARM::VLD1q8_UPD: 1682 case ARM::VLD1q16_UPD: 1683 case ARM::VLD1q32_UPD: 1684 case ARM::VLD1q64_UPD: 1685 case ARM::VLD1d8T: 1686 case ARM::VLD1d16T: 1687 case ARM::VLD1d32T: 1688 case ARM::VLD1d64T: 1689 case ARM::VLD1d8T_UPD: 1690 case ARM::VLD1d16T_UPD: 1691 case ARM::VLD1d32T_UPD: 1692 case ARM::VLD1d64T_UPD: 1693 case ARM::VLD1d8Q: 1694 case ARM::VLD1d16Q: 1695 case ARM::VLD1d32Q: 1696 case ARM::VLD1d64Q: 1697 case ARM::VLD1d8Q_UPD: 1698 case ARM::VLD1d16Q_UPD: 1699 case ARM::VLD1d32Q_UPD: 1700 case ARM::VLD1d64Q_UPD: 1701 case ARM::VLD2d8: 1702 case ARM::VLD2d16: 1703 case ARM::VLD2d32: 1704 case ARM::VLD2d8_UPD: 1705 case ARM::VLD2d16_UPD: 1706 case ARM::VLD2d32_UPD: 1707 case ARM::VLD2q8: 1708 case ARM::VLD2q16: 1709 case ARM::VLD2q32: 1710 case ARM::VLD2q8_UPD: 1711 case ARM::VLD2q16_UPD: 1712 case ARM::VLD2q32_UPD: 1713 case ARM::VLD3d8: 1714 case ARM::VLD3d16: 1715 case ARM::VLD3d32: 1716 case ARM::VLD3d8_UPD: 1717 case ARM::VLD3d16_UPD: 1718 case ARM::VLD3d32_UPD: 1719 case ARM::VLD4d8: 1720 case ARM::VLD4d16: 1721 case ARM::VLD4d32: 1722 case ARM::VLD4d8_UPD: 1723 case ARM::VLD4d16_UPD: 1724 case ARM::VLD4d32_UPD: 1725 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 1726 return MCDisassembler::Fail; 1727 break; 1728 case ARM::VLD2b8: 1729 case ARM::VLD2b16: 1730 case ARM::VLD2b32: 1731 case ARM::VLD2b8_UPD: 1732 case ARM::VLD2b16_UPD: 1733 case ARM::VLD2b32_UPD: 1734 case ARM::VLD3q8: 1735 case ARM::VLD3q16: 1736 case ARM::VLD3q32: 1737 case ARM::VLD3q8_UPD: 1738 case ARM::VLD3q16_UPD: 1739 case ARM::VLD3q32_UPD: 1740 case ARM::VLD4q8: 1741 case ARM::VLD4q16: 1742 case ARM::VLD4q32: 1743 case ARM::VLD4q8_UPD: 1744 case ARM::VLD4q16_UPD: 1745 case ARM::VLD4q32_UPD: 1746 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1747 return MCDisassembler::Fail; 1748 default: 1749 break; 1750 } 1751 1752 // Third output register 1753 switch(Inst.getOpcode()) { 1754 case ARM::VLD1d8T: 1755 case ARM::VLD1d16T: 1756 case ARM::VLD1d32T: 1757 case ARM::VLD1d64T: 1758 case ARM::VLD1d8T_UPD: 1759 case ARM::VLD1d16T_UPD: 1760 case ARM::VLD1d32T_UPD: 1761 case ARM::VLD1d64T_UPD: 1762 case ARM::VLD1d8Q: 1763 case ARM::VLD1d16Q: 1764 case ARM::VLD1d32Q: 1765 case ARM::VLD1d64Q: 1766 case ARM::VLD1d8Q_UPD: 1767 case ARM::VLD1d16Q_UPD: 1768 case ARM::VLD1d32Q_UPD: 1769 case ARM::VLD1d64Q_UPD: 1770 case ARM::VLD2q8: 1771 case ARM::VLD2q16: 1772 case ARM::VLD2q32: 1773 case ARM::VLD2q8_UPD: 1774 case ARM::VLD2q16_UPD: 1775 case ARM::VLD2q32_UPD: 1776 case ARM::VLD3d8: 1777 case ARM::VLD3d16: 1778 case ARM::VLD3d32: 1779 case ARM::VLD3d8_UPD: 1780 case ARM::VLD3d16_UPD: 1781 case ARM::VLD3d32_UPD: 1782 case ARM::VLD4d8: 1783 case ARM::VLD4d16: 1784 case ARM::VLD4d32: 1785 case ARM::VLD4d8_UPD: 1786 case ARM::VLD4d16_UPD: 1787 case ARM::VLD4d32_UPD: 1788 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1789 return MCDisassembler::Fail; 1790 break; 1791 case ARM::VLD3q8: 1792 case ARM::VLD3q16: 1793 case ARM::VLD3q32: 1794 case ARM::VLD3q8_UPD: 1795 case ARM::VLD3q16_UPD: 1796 case ARM::VLD3q32_UPD: 1797 case ARM::VLD4q8: 1798 case ARM::VLD4q16: 1799 case ARM::VLD4q32: 1800 case ARM::VLD4q8_UPD: 1801 case ARM::VLD4q16_UPD: 1802 case ARM::VLD4q32_UPD: 1803 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 1804 return MCDisassembler::Fail; 1805 break; 1806 default: 1807 break; 1808 } 1809 1810 // Fourth output register 1811 switch (Inst.getOpcode()) { 1812 case ARM::VLD1d8Q: 1813 case ARM::VLD1d16Q: 1814 case ARM::VLD1d32Q: 1815 case ARM::VLD1d64Q: 1816 case ARM::VLD1d8Q_UPD: 1817 case ARM::VLD1d16Q_UPD: 1818 case ARM::VLD1d32Q_UPD: 1819 case ARM::VLD1d64Q_UPD: 1820 case ARM::VLD2q8: 1821 case ARM::VLD2q16: 1822 case ARM::VLD2q32: 1823 case ARM::VLD2q8_UPD: 1824 case ARM::VLD2q16_UPD: 1825 case ARM::VLD2q32_UPD: 1826 case ARM::VLD4d8: 1827 case ARM::VLD4d16: 1828 case ARM::VLD4d32: 1829 case ARM::VLD4d8_UPD: 1830 case ARM::VLD4d16_UPD: 1831 case ARM::VLD4d32_UPD: 1832 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 1833 return MCDisassembler::Fail; 1834 break; 1835 case ARM::VLD4q8: 1836 case ARM::VLD4q16: 1837 case ARM::VLD4q32: 1838 case ARM::VLD4q8_UPD: 1839 case ARM::VLD4q16_UPD: 1840 case ARM::VLD4q32_UPD: 1841 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 1842 return MCDisassembler::Fail; 1843 break; 1844 default: 1845 break; 1846 } 1847 1848 // Writeback operand 1849 switch (Inst.getOpcode()) { 1850 case ARM::VLD1d8_UPD: 1851 case ARM::VLD1d16_UPD: 1852 case ARM::VLD1d32_UPD: 1853 case ARM::VLD1d64_UPD: 1854 case ARM::VLD1q8_UPD: 1855 case ARM::VLD1q16_UPD: 1856 case ARM::VLD1q32_UPD: 1857 case ARM::VLD1q64_UPD: 1858 case ARM::VLD1d8T_UPD: 1859 case ARM::VLD1d16T_UPD: 1860 case ARM::VLD1d32T_UPD: 1861 case ARM::VLD1d64T_UPD: 1862 case ARM::VLD1d8Q_UPD: 1863 case ARM::VLD1d16Q_UPD: 1864 case ARM::VLD1d32Q_UPD: 1865 case ARM::VLD1d64Q_UPD: 1866 case ARM::VLD2d8_UPD: 1867 case ARM::VLD2d16_UPD: 1868 case ARM::VLD2d32_UPD: 1869 case ARM::VLD2q8_UPD: 1870 case ARM::VLD2q16_UPD: 1871 case ARM::VLD2q32_UPD: 1872 case ARM::VLD2b8_UPD: 1873 case ARM::VLD2b16_UPD: 1874 case ARM::VLD2b32_UPD: 1875 case ARM::VLD3d8_UPD: 1876 case ARM::VLD3d16_UPD: 1877 case ARM::VLD3d32_UPD: 1878 case ARM::VLD3q8_UPD: 1879 case ARM::VLD3q16_UPD: 1880 case ARM::VLD3q32_UPD: 1881 case ARM::VLD4d8_UPD: 1882 case ARM::VLD4d16_UPD: 1883 case ARM::VLD4d32_UPD: 1884 case ARM::VLD4q8_UPD: 1885 case ARM::VLD4q16_UPD: 1886 case ARM::VLD4q32_UPD: 1887 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 1888 return MCDisassembler::Fail; 1889 break; 1890 default: 1891 break; 1892 } 1893 1894 // AddrMode6 Base (register+alignment) 1895 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 1896 return MCDisassembler::Fail; 1897 1898 // AddrMode6 Offset (register) 1899 if (Rm == 0xD) 1900 Inst.addOperand(MCOperand::CreateReg(0)); 1901 else if (Rm != 0xF) { 1902 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1903 return MCDisassembler::Fail; 1904 } 1905 1906 return S; 1907 } 1908 1909 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1910 uint64_t Address, const void *Decoder) { 1911 DecodeStatus S = MCDisassembler::Success; 1912 1913 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1914 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1915 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1916 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1917 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1918 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1919 1920 // Writeback Operand 1921 switch (Inst.getOpcode()) { 1922 case ARM::VST1d8_UPD: 1923 case ARM::VST1d16_UPD: 1924 case ARM::VST1d32_UPD: 1925 case ARM::VST1d64_UPD: 1926 case ARM::VST1q8_UPD: 1927 case ARM::VST1q16_UPD: 1928 case ARM::VST1q32_UPD: 1929 case ARM::VST1q64_UPD: 1930 case ARM::VST1d8T_UPD: 1931 case ARM::VST1d16T_UPD: 1932 case ARM::VST1d32T_UPD: 1933 case ARM::VST1d64T_UPD: 1934 case ARM::VST1d8Q_UPD: 1935 case ARM::VST1d16Q_UPD: 1936 case ARM::VST1d32Q_UPD: 1937 case ARM::VST1d64Q_UPD: 1938 case ARM::VST2d8_UPD: 1939 case ARM::VST2d16_UPD: 1940 case ARM::VST2d32_UPD: 1941 case ARM::VST2q8_UPD: 1942 case ARM::VST2q16_UPD: 1943 case ARM::VST2q32_UPD: 1944 case ARM::VST2b8_UPD: 1945 case ARM::VST2b16_UPD: 1946 case ARM::VST2b32_UPD: 1947 case ARM::VST3d8_UPD: 1948 case ARM::VST3d16_UPD: 1949 case ARM::VST3d32_UPD: 1950 case ARM::VST3q8_UPD: 1951 case ARM::VST3q16_UPD: 1952 case ARM::VST3q32_UPD: 1953 case ARM::VST4d8_UPD: 1954 case ARM::VST4d16_UPD: 1955 case ARM::VST4d32_UPD: 1956 case ARM::VST4q8_UPD: 1957 case ARM::VST4q16_UPD: 1958 case ARM::VST4q32_UPD: 1959 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 1960 return MCDisassembler::Fail; 1961 break; 1962 default: 1963 break; 1964 } 1965 1966 // AddrMode6 Base (register+alignment) 1967 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 1968 return MCDisassembler::Fail; 1969 1970 // AddrMode6 Offset (register) 1971 if (Rm == 0xD) 1972 Inst.addOperand(MCOperand::CreateReg(0)); 1973 else if (Rm != 0xF) { 1974 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1975 return MCDisassembler::Fail; 1976 } 1977 1978 // First input register 1979 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 1980 return MCDisassembler::Fail; 1981 1982 // Second input register 1983 switch (Inst.getOpcode()) { 1984 case ARM::VST1q8: 1985 case ARM::VST1q16: 1986 case ARM::VST1q32: 1987 case ARM::VST1q64: 1988 case ARM::VST1q8_UPD: 1989 case ARM::VST1q16_UPD: 1990 case ARM::VST1q32_UPD: 1991 case ARM::VST1q64_UPD: 1992 case ARM::VST1d8T: 1993 case ARM::VST1d16T: 1994 case ARM::VST1d32T: 1995 case ARM::VST1d64T: 1996 case ARM::VST1d8T_UPD: 1997 case ARM::VST1d16T_UPD: 1998 case ARM::VST1d32T_UPD: 1999 case ARM::VST1d64T_UPD: 2000 case ARM::VST1d8Q: 2001 case ARM::VST1d16Q: 2002 case ARM::VST1d32Q: 2003 case ARM::VST1d64Q: 2004 case ARM::VST1d8Q_UPD: 2005 case ARM::VST1d16Q_UPD: 2006 case ARM::VST1d32Q_UPD: 2007 case ARM::VST1d64Q_UPD: 2008 case ARM::VST2d8: 2009 case ARM::VST2d16: 2010 case ARM::VST2d32: 2011 case ARM::VST2d8_UPD: 2012 case ARM::VST2d16_UPD: 2013 case ARM::VST2d32_UPD: 2014 case ARM::VST2q8: 2015 case ARM::VST2q16: 2016 case ARM::VST2q32: 2017 case ARM::VST2q8_UPD: 2018 case ARM::VST2q16_UPD: 2019 case ARM::VST2q32_UPD: 2020 case ARM::VST3d8: 2021 case ARM::VST3d16: 2022 case ARM::VST3d32: 2023 case ARM::VST3d8_UPD: 2024 case ARM::VST3d16_UPD: 2025 case ARM::VST3d32_UPD: 2026 case ARM::VST4d8: 2027 case ARM::VST4d16: 2028 case ARM::VST4d32: 2029 case ARM::VST4d8_UPD: 2030 case ARM::VST4d16_UPD: 2031 case ARM::VST4d32_UPD: 2032 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2033 return MCDisassembler::Fail; 2034 break; 2035 case ARM::VST2b8: 2036 case ARM::VST2b16: 2037 case ARM::VST2b32: 2038 case ARM::VST2b8_UPD: 2039 case ARM::VST2b16_UPD: 2040 case ARM::VST2b32_UPD: 2041 case ARM::VST3q8: 2042 case ARM::VST3q16: 2043 case ARM::VST3q32: 2044 case ARM::VST3q8_UPD: 2045 case ARM::VST3q16_UPD: 2046 case ARM::VST3q32_UPD: 2047 case ARM::VST4q8: 2048 case ARM::VST4q16: 2049 case ARM::VST4q32: 2050 case ARM::VST4q8_UPD: 2051 case ARM::VST4q16_UPD: 2052 case ARM::VST4q32_UPD: 2053 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2054 return MCDisassembler::Fail; 2055 break; 2056 default: 2057 break; 2058 } 2059 2060 // Third input register 2061 switch (Inst.getOpcode()) { 2062 case ARM::VST1d8T: 2063 case ARM::VST1d16T: 2064 case ARM::VST1d32T: 2065 case ARM::VST1d64T: 2066 case ARM::VST1d8T_UPD: 2067 case ARM::VST1d16T_UPD: 2068 case ARM::VST1d32T_UPD: 2069 case ARM::VST1d64T_UPD: 2070 case ARM::VST1d8Q: 2071 case ARM::VST1d16Q: 2072 case ARM::VST1d32Q: 2073 case ARM::VST1d64Q: 2074 case ARM::VST1d8Q_UPD: 2075 case ARM::VST1d16Q_UPD: 2076 case ARM::VST1d32Q_UPD: 2077 case ARM::VST1d64Q_UPD: 2078 case ARM::VST2q8: 2079 case ARM::VST2q16: 2080 case ARM::VST2q32: 2081 case ARM::VST2q8_UPD: 2082 case ARM::VST2q16_UPD: 2083 case ARM::VST2q32_UPD: 2084 case ARM::VST3d8: 2085 case ARM::VST3d16: 2086 case ARM::VST3d32: 2087 case ARM::VST3d8_UPD: 2088 case ARM::VST3d16_UPD: 2089 case ARM::VST3d32_UPD: 2090 case ARM::VST4d8: 2091 case ARM::VST4d16: 2092 case ARM::VST4d32: 2093 case ARM::VST4d8_UPD: 2094 case ARM::VST4d16_UPD: 2095 case ARM::VST4d32_UPD: 2096 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2097 return MCDisassembler::Fail; 2098 break; 2099 case ARM::VST3q8: 2100 case ARM::VST3q16: 2101 case ARM::VST3q32: 2102 case ARM::VST3q8_UPD: 2103 case ARM::VST3q16_UPD: 2104 case ARM::VST3q32_UPD: 2105 case ARM::VST4q8: 2106 case ARM::VST4q16: 2107 case ARM::VST4q32: 2108 case ARM::VST4q8_UPD: 2109 case ARM::VST4q16_UPD: 2110 case ARM::VST4q32_UPD: 2111 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2112 return MCDisassembler::Fail; 2113 break; 2114 default: 2115 break; 2116 } 2117 2118 // Fourth input register 2119 switch (Inst.getOpcode()) { 2120 case ARM::VST1d8Q: 2121 case ARM::VST1d16Q: 2122 case ARM::VST1d32Q: 2123 case ARM::VST1d64Q: 2124 case ARM::VST1d8Q_UPD: 2125 case ARM::VST1d16Q_UPD: 2126 case ARM::VST1d32Q_UPD: 2127 case ARM::VST1d64Q_UPD: 2128 case ARM::VST2q8: 2129 case ARM::VST2q16: 2130 case ARM::VST2q32: 2131 case ARM::VST2q8_UPD: 2132 case ARM::VST2q16_UPD: 2133 case ARM::VST2q32_UPD: 2134 case ARM::VST4d8: 2135 case ARM::VST4d16: 2136 case ARM::VST4d32: 2137 case ARM::VST4d8_UPD: 2138 case ARM::VST4d16_UPD: 2139 case ARM::VST4d32_UPD: 2140 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2141 return MCDisassembler::Fail; 2142 break; 2143 case ARM::VST4q8: 2144 case ARM::VST4q16: 2145 case ARM::VST4q32: 2146 case ARM::VST4q8_UPD: 2147 case ARM::VST4q16_UPD: 2148 case ARM::VST4q32_UPD: 2149 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2150 return MCDisassembler::Fail; 2151 break; 2152 default: 2153 break; 2154 } 2155 2156 return S; 2157 } 2158 2159 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2160 uint64_t Address, const void *Decoder) { 2161 DecodeStatus S = MCDisassembler::Success; 2162 2163 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2164 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2165 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2166 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2167 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2168 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2169 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 2170 2171 align *= (1 << size); 2172 2173 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2174 return MCDisassembler::Fail; 2175 if (regs == 2) { 2176 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2177 return MCDisassembler::Fail; 2178 } 2179 if (Rm != 0xF) { 2180 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2181 return MCDisassembler::Fail; 2182 } 2183 2184 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2185 return MCDisassembler::Fail; 2186 Inst.addOperand(MCOperand::CreateImm(align)); 2187 2188 if (Rm == 0xD) 2189 Inst.addOperand(MCOperand::CreateReg(0)); 2190 else if (Rm != 0xF) { 2191 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2192 return MCDisassembler::Fail; 2193 } 2194 2195 return S; 2196 } 2197 2198 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2199 uint64_t Address, const void *Decoder) { 2200 DecodeStatus S = MCDisassembler::Success; 2201 2202 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2203 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2204 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2205 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2206 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2207 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2208 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2209 align *= 2*size; 2210 2211 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2212 return MCDisassembler::Fail; 2213 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2214 return MCDisassembler::Fail; 2215 if (Rm != 0xF) { 2216 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2217 return MCDisassembler::Fail; 2218 } 2219 2220 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2221 return MCDisassembler::Fail; 2222 Inst.addOperand(MCOperand::CreateImm(align)); 2223 2224 if (Rm == 0xD) 2225 Inst.addOperand(MCOperand::CreateReg(0)); 2226 else if (Rm != 0xF) { 2227 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2228 return MCDisassembler::Fail; 2229 } 2230 2231 return S; 2232 } 2233 2234 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2235 uint64_t Address, const void *Decoder) { 2236 DecodeStatus S = MCDisassembler::Success; 2237 2238 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2239 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2240 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2241 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2242 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2243 2244 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2245 return MCDisassembler::Fail; 2246 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2247 return MCDisassembler::Fail; 2248 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2249 return MCDisassembler::Fail; 2250 if (Rm != 0xF) { 2251 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2252 return MCDisassembler::Fail; 2253 } 2254 2255 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2256 return MCDisassembler::Fail; 2257 Inst.addOperand(MCOperand::CreateImm(0)); 2258 2259 if (Rm == 0xD) 2260 Inst.addOperand(MCOperand::CreateReg(0)); 2261 else if (Rm != 0xF) { 2262 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2263 return MCDisassembler::Fail; 2264 } 2265 2266 return S; 2267 } 2268 2269 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2270 uint64_t Address, const void *Decoder) { 2271 DecodeStatus S = MCDisassembler::Success; 2272 2273 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2274 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2275 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2276 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2277 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2278 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2279 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2280 2281 if (size == 0x3) { 2282 size = 4; 2283 align = 16; 2284 } else { 2285 if (size == 2) { 2286 size = 1 << size; 2287 align *= 8; 2288 } else { 2289 size = 1 << size; 2290 align *= 4*size; 2291 } 2292 } 2293 2294 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2295 return MCDisassembler::Fail; 2296 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2297 return MCDisassembler::Fail; 2298 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2299 return MCDisassembler::Fail; 2300 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2301 return MCDisassembler::Fail; 2302 if (Rm != 0xF) { 2303 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2304 return MCDisassembler::Fail; 2305 } 2306 2307 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2308 return MCDisassembler::Fail; 2309 Inst.addOperand(MCOperand::CreateImm(align)); 2310 2311 if (Rm == 0xD) 2312 Inst.addOperand(MCOperand::CreateReg(0)); 2313 else if (Rm != 0xF) { 2314 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2315 return MCDisassembler::Fail; 2316 } 2317 2318 return S; 2319 } 2320 2321 static DecodeStatus 2322 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2323 uint64_t Address, const void *Decoder) { 2324 DecodeStatus S = MCDisassembler::Success; 2325 2326 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2327 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2328 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2329 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2330 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2331 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2332 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2333 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2334 2335 if (Q) { 2336 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2337 return MCDisassembler::Fail; 2338 } else { 2339 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2340 return MCDisassembler::Fail; 2341 } 2342 2343 Inst.addOperand(MCOperand::CreateImm(imm)); 2344 2345 switch (Inst.getOpcode()) { 2346 case ARM::VORRiv4i16: 2347 case ARM::VORRiv2i32: 2348 case ARM::VBICiv4i16: 2349 case ARM::VBICiv2i32: 2350 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2351 return MCDisassembler::Fail; 2352 break; 2353 case ARM::VORRiv8i16: 2354 case ARM::VORRiv4i32: 2355 case ARM::VBICiv8i16: 2356 case ARM::VBICiv4i32: 2357 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2358 return MCDisassembler::Fail; 2359 break; 2360 default: 2361 break; 2362 } 2363 2364 return S; 2365 } 2366 2367 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2368 uint64_t Address, const void *Decoder) { 2369 DecodeStatus S = MCDisassembler::Success; 2370 2371 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2372 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2373 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2374 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2375 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2376 2377 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2378 return MCDisassembler::Fail; 2379 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2380 return MCDisassembler::Fail; 2381 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2382 2383 return S; 2384 } 2385 2386 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2387 uint64_t Address, const void *Decoder) { 2388 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2389 return MCDisassembler::Success; 2390 } 2391 2392 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2393 uint64_t Address, const void *Decoder) { 2394 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2395 return MCDisassembler::Success; 2396 } 2397 2398 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2399 uint64_t Address, const void *Decoder) { 2400 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2401 return MCDisassembler::Success; 2402 } 2403 2404 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2405 uint64_t Address, const void *Decoder) { 2406 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2407 return MCDisassembler::Success; 2408 } 2409 2410 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2411 uint64_t Address, const void *Decoder) { 2412 DecodeStatus S = MCDisassembler::Success; 2413 2414 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2415 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2416 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2417 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2418 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2419 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2420 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2421 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2422 2423 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2424 return MCDisassembler::Fail; 2425 if (op) { 2426 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2427 return MCDisassembler::Fail; // Writeback 2428 } 2429 2430 for (unsigned i = 0; i < length; ++i) { 2431 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder))) 2432 return MCDisassembler::Fail; 2433 } 2434 2435 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2436 return MCDisassembler::Fail; 2437 2438 return S; 2439 } 2440 2441 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2442 uint64_t Address, const void *Decoder) { 2443 // The immediate needs to be a fully instantiated float. However, the 2444 // auto-generated decoder is only able to fill in some of the bits 2445 // necessary. For instance, the 'b' bit is replicated multiple times, 2446 // and is even present in inverted form in one bit. We do a little 2447 // binary parsing here to fill in those missing bits, and then 2448 // reinterpret it all as a float. 2449 union { 2450 uint32_t integer; 2451 float fp; 2452 } fp_conv; 2453 2454 fp_conv.integer = Val; 2455 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2456 fp_conv.integer |= b << 26; 2457 fp_conv.integer |= b << 27; 2458 fp_conv.integer |= b << 28; 2459 fp_conv.integer |= b << 29; 2460 fp_conv.integer |= (~b & 0x1) << 30; 2461 2462 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2463 return MCDisassembler::Success; 2464 } 2465 2466 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2467 uint64_t Address, const void *Decoder) { 2468 DecodeStatus S = MCDisassembler::Success; 2469 2470 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2471 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2472 2473 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2474 return MCDisassembler::Fail; 2475 2476 switch(Inst.getOpcode()) { 2477 default: 2478 return MCDisassembler::Fail; 2479 case ARM::tADR: 2480 break; // tADR does not explicitly represent the PC as an operand. 2481 case ARM::tADDrSPi: 2482 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2483 break; 2484 } 2485 2486 Inst.addOperand(MCOperand::CreateImm(imm)); 2487 return S; 2488 } 2489 2490 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2491 uint64_t Address, const void *Decoder) { 2492 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2493 return MCDisassembler::Success; 2494 } 2495 2496 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2497 uint64_t Address, const void *Decoder) { 2498 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2499 return MCDisassembler::Success; 2500 } 2501 2502 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2503 uint64_t Address, const void *Decoder) { 2504 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2505 return MCDisassembler::Success; 2506 } 2507 2508 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2509 uint64_t Address, const void *Decoder) { 2510 DecodeStatus S = MCDisassembler::Success; 2511 2512 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2513 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2514 2515 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2516 return MCDisassembler::Fail; 2517 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 2518 return MCDisassembler::Fail; 2519 2520 return S; 2521 } 2522 2523 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2524 uint64_t Address, const void *Decoder) { 2525 DecodeStatus S = MCDisassembler::Success; 2526 2527 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2528 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2529 2530 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2531 return MCDisassembler::Fail; 2532 Inst.addOperand(MCOperand::CreateImm(imm)); 2533 2534 return S; 2535 } 2536 2537 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2538 uint64_t Address, const void *Decoder) { 2539 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2540 2541 return MCDisassembler::Success; 2542 } 2543 2544 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2545 uint64_t Address, const void *Decoder) { 2546 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2547 Inst.addOperand(MCOperand::CreateImm(Val)); 2548 2549 return MCDisassembler::Success; 2550 } 2551 2552 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2553 uint64_t Address, const void *Decoder) { 2554 DecodeStatus S = MCDisassembler::Success; 2555 2556 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2557 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2558 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2559 2560 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2561 return MCDisassembler::Fail; 2562 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 2563 return MCDisassembler::Fail; 2564 Inst.addOperand(MCOperand::CreateImm(imm)); 2565 2566 return S; 2567 } 2568 2569 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2570 uint64_t Address, const void *Decoder) { 2571 DecodeStatus S = MCDisassembler::Success; 2572 2573 switch (Inst.getOpcode()) { 2574 case ARM::t2PLDs: 2575 case ARM::t2PLDWs: 2576 case ARM::t2PLIs: 2577 break; 2578 default: { 2579 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2580 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2581 return MCDisassembler::Fail; 2582 } 2583 } 2584 2585 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2586 if (Rn == 0xF) { 2587 switch (Inst.getOpcode()) { 2588 case ARM::t2LDRBs: 2589 Inst.setOpcode(ARM::t2LDRBpci); 2590 break; 2591 case ARM::t2LDRHs: 2592 Inst.setOpcode(ARM::t2LDRHpci); 2593 break; 2594 case ARM::t2LDRSHs: 2595 Inst.setOpcode(ARM::t2LDRSHpci); 2596 break; 2597 case ARM::t2LDRSBs: 2598 Inst.setOpcode(ARM::t2LDRSBpci); 2599 break; 2600 case ARM::t2PLDs: 2601 Inst.setOpcode(ARM::t2PLDi12); 2602 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2603 break; 2604 default: 2605 return MCDisassembler::Fail; 2606 } 2607 2608 int imm = fieldFromInstruction32(Insn, 0, 12); 2609 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2610 Inst.addOperand(MCOperand::CreateImm(imm)); 2611 2612 return S; 2613 } 2614 2615 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2616 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2617 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2618 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 2619 return MCDisassembler::Fail; 2620 2621 return S; 2622 } 2623 2624 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2625 uint64_t Address, const void *Decoder) { 2626 int imm = Val & 0xFF; 2627 if (!(Val & 0x100)) imm *= -1; 2628 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2629 2630 return MCDisassembler::Success; 2631 } 2632 2633 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2634 uint64_t Address, const void *Decoder) { 2635 DecodeStatus S = MCDisassembler::Success; 2636 2637 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2638 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2639 2640 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2641 return MCDisassembler::Fail; 2642 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 2643 return MCDisassembler::Fail; 2644 2645 return S; 2646 } 2647 2648 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2649 uint64_t Address, const void *Decoder) { 2650 int imm = Val & 0xFF; 2651 if (!(Val & 0x100)) imm *= -1; 2652 Inst.addOperand(MCOperand::CreateImm(imm)); 2653 2654 return MCDisassembler::Success; 2655 } 2656 2657 2658 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2659 uint64_t Address, const void *Decoder) { 2660 DecodeStatus S = MCDisassembler::Success; 2661 2662 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2663 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2664 2665 // Some instructions always use an additive offset. 2666 switch (Inst.getOpcode()) { 2667 case ARM::t2LDRT: 2668 case ARM::t2LDRBT: 2669 case ARM::t2LDRHT: 2670 case ARM::t2LDRSBT: 2671 case ARM::t2LDRSHT: 2672 imm |= 0x100; 2673 break; 2674 default: 2675 break; 2676 } 2677 2678 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2679 return MCDisassembler::Fail; 2680 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 2681 return MCDisassembler::Fail; 2682 2683 return S; 2684 } 2685 2686 2687 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2688 uint64_t Address, const void *Decoder) { 2689 DecodeStatus S = MCDisassembler::Success; 2690 2691 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2692 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2693 2694 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2695 return MCDisassembler::Fail; 2696 Inst.addOperand(MCOperand::CreateImm(imm)); 2697 2698 return S; 2699 } 2700 2701 2702 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2703 uint64_t Address, const void *Decoder) { 2704 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2705 2706 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2707 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2708 Inst.addOperand(MCOperand::CreateImm(imm)); 2709 2710 return MCDisassembler::Success; 2711 } 2712 2713 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2714 uint64_t Address, const void *Decoder) { 2715 DecodeStatus S = MCDisassembler::Success; 2716 2717 if (Inst.getOpcode() == ARM::tADDrSP) { 2718 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2719 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2720 2721 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2722 return MCDisassembler::Fail; 2723 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2724 return MCDisassembler::Fail; 2725 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2726 } else if (Inst.getOpcode() == ARM::tADDspr) { 2727 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2728 2729 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2730 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2731 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2732 return MCDisassembler::Fail; 2733 } 2734 2735 return S; 2736 } 2737 2738 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2739 uint64_t Address, const void *Decoder) { 2740 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2741 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2742 2743 Inst.addOperand(MCOperand::CreateImm(imod)); 2744 Inst.addOperand(MCOperand::CreateImm(flags)); 2745 2746 return MCDisassembler::Success; 2747 } 2748 2749 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2750 uint64_t Address, const void *Decoder) { 2751 DecodeStatus S = MCDisassembler::Success; 2752 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2753 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2754 2755 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2756 return MCDisassembler::Fail; 2757 Inst.addOperand(MCOperand::CreateImm(add)); 2758 2759 return S; 2760 } 2761 2762 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2763 uint64_t Address, const void *Decoder) { 2764 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2765 return MCDisassembler::Success; 2766 } 2767 2768 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2769 uint64_t Address, const void *Decoder) { 2770 if (Val == 0xA || Val == 0xB) 2771 return MCDisassembler::Fail; 2772 2773 Inst.addOperand(MCOperand::CreateImm(Val)); 2774 return MCDisassembler::Success; 2775 } 2776 2777 static DecodeStatus 2778 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2779 uint64_t Address, const void *Decoder) { 2780 DecodeStatus S = MCDisassembler::Success; 2781 2782 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2783 if (pred == 0xE || pred == 0xF) { 2784 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 2785 switch (opc) { 2786 default: 2787 return MCDisassembler::Fail; 2788 case 0xf3bf8f4: 2789 Inst.setOpcode(ARM::t2DSB); 2790 break; 2791 case 0xf3bf8f5: 2792 Inst.setOpcode(ARM::t2DMB); 2793 break; 2794 case 0xf3bf8f6: 2795 Inst.setOpcode(ARM::t2ISB); 2796 break; 2797 } 2798 2799 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2800 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2801 } 2802 2803 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2804 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2805 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2806 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2807 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2808 2809 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 2810 return MCDisassembler::Fail; 2811 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2812 return MCDisassembler::Fail; 2813 2814 return S; 2815 } 2816 2817 // Decode a shifted immediate operand. These basically consist 2818 // of an 8-bit value, and a 4-bit directive that specifies either 2819 // a splat operation or a rotation. 2820 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2821 uint64_t Address, const void *Decoder) { 2822 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2823 if (ctrl == 0) { 2824 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2825 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2826 switch (byte) { 2827 case 0: 2828 Inst.addOperand(MCOperand::CreateImm(imm)); 2829 break; 2830 case 1: 2831 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2832 break; 2833 case 2: 2834 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2835 break; 2836 case 3: 2837 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2838 (imm << 8) | imm)); 2839 break; 2840 } 2841 } else { 2842 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2843 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2844 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2845 Inst.addOperand(MCOperand::CreateImm(imm)); 2846 } 2847 2848 return MCDisassembler::Success; 2849 } 2850 2851 static DecodeStatus 2852 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2853 uint64_t Address, const void *Decoder){ 2854 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2855 return MCDisassembler::Success; 2856 } 2857 2858 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2859 uint64_t Address, const void *Decoder){ 2860 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2861 return MCDisassembler::Success; 2862 } 2863 2864 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2865 uint64_t Address, const void *Decoder) { 2866 switch (Val) { 2867 default: 2868 return MCDisassembler::Fail; 2869 case 0xF: // SY 2870 case 0xE: // ST 2871 case 0xB: // ISH 2872 case 0xA: // ISHST 2873 case 0x7: // NSH 2874 case 0x6: // NSHST 2875 case 0x3: // OSH 2876 case 0x2: // OSHST 2877 break; 2878 } 2879 2880 Inst.addOperand(MCOperand::CreateImm(Val)); 2881 return MCDisassembler::Success; 2882 } 2883 2884 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 2885 uint64_t Address, const void *Decoder) { 2886 if (!Val) return MCDisassembler::Fail; 2887 Inst.addOperand(MCOperand::CreateImm(Val)); 2888 return MCDisassembler::Success; 2889 } 2890 2891 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 2892 uint64_t Address, const void *Decoder) { 2893 DecodeStatus S = MCDisassembler::Success; 2894 2895 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2896 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2897 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2898 2899 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 2900 2901 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2902 return MCDisassembler::Fail; 2903 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2904 return MCDisassembler::Fail; 2905 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2906 return MCDisassembler::Fail; 2907 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2908 return MCDisassembler::Fail; 2909 2910 return S; 2911 } 2912 2913 2914 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 2915 uint64_t Address, const void *Decoder){ 2916 DecodeStatus S = MCDisassembler::Success; 2917 2918 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2919 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 2920 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2921 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2922 2923 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2924 return MCDisassembler::Fail; 2925 2926 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 2927 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 2928 2929 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2930 return MCDisassembler::Fail; 2931 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2932 return MCDisassembler::Fail; 2933 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2934 return MCDisassembler::Fail; 2935 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2936 return MCDisassembler::Fail; 2937 2938 return S; 2939 } 2940 2941 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 2942 uint64_t Address, const void *Decoder) { 2943 DecodeStatus S = MCDisassembler::Success; 2944 2945 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2946 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2947 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2948 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2949 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2950 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2951 2952 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 2953 2954 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2955 return MCDisassembler::Fail; 2956 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2957 return MCDisassembler::Fail; 2958 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 2959 return MCDisassembler::Fail; 2960 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2961 return MCDisassembler::Fail; 2962 2963 return S; 2964 } 2965 2966 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 2967 uint64_t Address, const void *Decoder) { 2968 DecodeStatus S = MCDisassembler::Success; 2969 2970 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2971 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2972 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2973 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2974 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2975 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2976 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2977 2978 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 2979 if (Rm == 0xF) S = MCDisassembler::SoftFail; 2980 2981 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2982 return MCDisassembler::Fail; 2983 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2984 return MCDisassembler::Fail; 2985 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 2986 return MCDisassembler::Fail; 2987 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2988 return MCDisassembler::Fail; 2989 2990 return S; 2991 } 2992 2993 2994 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 2995 uint64_t Address, const void *Decoder) { 2996 DecodeStatus S = MCDisassembler::Success; 2997 2998 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2999 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3000 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3001 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3002 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3003 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3004 3005 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3006 3007 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3008 return MCDisassembler::Fail; 3009 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3010 return MCDisassembler::Fail; 3011 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3012 return MCDisassembler::Fail; 3013 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3014 return MCDisassembler::Fail; 3015 3016 return S; 3017 } 3018 3019 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 3020 uint64_t Address, const void *Decoder) { 3021 DecodeStatus S = MCDisassembler::Success; 3022 3023 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3024 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3025 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3026 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3027 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3028 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3029 3030 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3031 3032 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3033 return MCDisassembler::Fail; 3034 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3035 return MCDisassembler::Fail; 3036 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3037 return MCDisassembler::Fail; 3038 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3039 return MCDisassembler::Fail; 3040 3041 return S; 3042 } 3043 3044 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 3045 uint64_t Address, const void *Decoder) { 3046 DecodeStatus S = MCDisassembler::Success; 3047 3048 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3049 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3050 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3051 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3052 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3053 3054 unsigned align = 0; 3055 unsigned index = 0; 3056 switch (size) { 3057 default: 3058 return MCDisassembler::Fail; 3059 case 0: 3060 if (fieldFromInstruction32(Insn, 4, 1)) 3061 return MCDisassembler::Fail; // UNDEFINED 3062 index = fieldFromInstruction32(Insn, 5, 3); 3063 break; 3064 case 1: 3065 if (fieldFromInstruction32(Insn, 5, 1)) 3066 return MCDisassembler::Fail; // UNDEFINED 3067 index = fieldFromInstruction32(Insn, 6, 2); 3068 if (fieldFromInstruction32(Insn, 4, 1)) 3069 align = 2; 3070 break; 3071 case 2: 3072 if (fieldFromInstruction32(Insn, 6, 1)) 3073 return MCDisassembler::Fail; // UNDEFINED 3074 index = fieldFromInstruction32(Insn, 7, 1); 3075 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3076 align = 4; 3077 } 3078 3079 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3080 return MCDisassembler::Fail; 3081 if (Rm != 0xF) { // Writeback 3082 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3083 return MCDisassembler::Fail; 3084 } 3085 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3086 return MCDisassembler::Fail; 3087 Inst.addOperand(MCOperand::CreateImm(align)); 3088 if (Rm != 0xF) { 3089 if (Rm != 0xD) { 3090 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3091 return MCDisassembler::Fail; 3092 } else 3093 Inst.addOperand(MCOperand::CreateReg(0)); 3094 } 3095 3096 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3097 return MCDisassembler::Fail; 3098 Inst.addOperand(MCOperand::CreateImm(index)); 3099 3100 return S; 3101 } 3102 3103 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 3104 uint64_t Address, const void *Decoder) { 3105 DecodeStatus S = MCDisassembler::Success; 3106 3107 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3108 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3109 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3110 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3111 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3112 3113 unsigned align = 0; 3114 unsigned index = 0; 3115 switch (size) { 3116 default: 3117 return MCDisassembler::Fail; 3118 case 0: 3119 if (fieldFromInstruction32(Insn, 4, 1)) 3120 return MCDisassembler::Fail; // UNDEFINED 3121 index = fieldFromInstruction32(Insn, 5, 3); 3122 break; 3123 case 1: 3124 if (fieldFromInstruction32(Insn, 5, 1)) 3125 return MCDisassembler::Fail; // UNDEFINED 3126 index = fieldFromInstruction32(Insn, 6, 2); 3127 if (fieldFromInstruction32(Insn, 4, 1)) 3128 align = 2; 3129 break; 3130 case 2: 3131 if (fieldFromInstruction32(Insn, 6, 1)) 3132 return MCDisassembler::Fail; // UNDEFINED 3133 index = fieldFromInstruction32(Insn, 7, 1); 3134 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3135 align = 4; 3136 } 3137 3138 if (Rm != 0xF) { // Writeback 3139 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3140 return MCDisassembler::Fail; 3141 } 3142 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3143 return MCDisassembler::Fail; 3144 Inst.addOperand(MCOperand::CreateImm(align)); 3145 if (Rm != 0xF) { 3146 if (Rm != 0xD) { 3147 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3148 return MCDisassembler::Fail; 3149 } else 3150 Inst.addOperand(MCOperand::CreateReg(0)); 3151 } 3152 3153 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3154 return MCDisassembler::Fail; 3155 Inst.addOperand(MCOperand::CreateImm(index)); 3156 3157 return S; 3158 } 3159 3160 3161 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 3162 uint64_t Address, const void *Decoder) { 3163 DecodeStatus S = MCDisassembler::Success; 3164 3165 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3166 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3167 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3168 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3169 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3170 3171 unsigned align = 0; 3172 unsigned index = 0; 3173 unsigned inc = 1; 3174 switch (size) { 3175 default: 3176 return MCDisassembler::Fail; 3177 case 0: 3178 index = fieldFromInstruction32(Insn, 5, 3); 3179 if (fieldFromInstruction32(Insn, 4, 1)) 3180 align = 2; 3181 break; 3182 case 1: 3183 index = fieldFromInstruction32(Insn, 6, 2); 3184 if (fieldFromInstruction32(Insn, 4, 1)) 3185 align = 4; 3186 if (fieldFromInstruction32(Insn, 5, 1)) 3187 inc = 2; 3188 break; 3189 case 2: 3190 if (fieldFromInstruction32(Insn, 5, 1)) 3191 return MCDisassembler::Fail; // UNDEFINED 3192 index = fieldFromInstruction32(Insn, 7, 1); 3193 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3194 align = 8; 3195 if (fieldFromInstruction32(Insn, 6, 1)) 3196 inc = 2; 3197 break; 3198 } 3199 3200 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3201 return MCDisassembler::Fail; 3202 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3203 return MCDisassembler::Fail; 3204 if (Rm != 0xF) { // Writeback 3205 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3206 return MCDisassembler::Fail; 3207 } 3208 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3209 return MCDisassembler::Fail; 3210 Inst.addOperand(MCOperand::CreateImm(align)); 3211 if (Rm != 0xF) { 3212 if (Rm != 0xD) { 3213 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3214 return MCDisassembler::Fail; 3215 } else 3216 Inst.addOperand(MCOperand::CreateReg(0)); 3217 } 3218 3219 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3220 return MCDisassembler::Fail; 3221 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3222 return MCDisassembler::Fail; 3223 Inst.addOperand(MCOperand::CreateImm(index)); 3224 3225 return S; 3226 } 3227 3228 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 3229 uint64_t Address, const void *Decoder) { 3230 DecodeStatus S = MCDisassembler::Success; 3231 3232 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3233 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3234 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3235 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3236 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3237 3238 unsigned align = 0; 3239 unsigned index = 0; 3240 unsigned inc = 1; 3241 switch (size) { 3242 default: 3243 return MCDisassembler::Fail; 3244 case 0: 3245 index = fieldFromInstruction32(Insn, 5, 3); 3246 if (fieldFromInstruction32(Insn, 4, 1)) 3247 align = 2; 3248 break; 3249 case 1: 3250 index = fieldFromInstruction32(Insn, 6, 2); 3251 if (fieldFromInstruction32(Insn, 4, 1)) 3252 align = 4; 3253 if (fieldFromInstruction32(Insn, 5, 1)) 3254 inc = 2; 3255 break; 3256 case 2: 3257 if (fieldFromInstruction32(Insn, 5, 1)) 3258 return MCDisassembler::Fail; // UNDEFINED 3259 index = fieldFromInstruction32(Insn, 7, 1); 3260 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3261 align = 8; 3262 if (fieldFromInstruction32(Insn, 6, 1)) 3263 inc = 2; 3264 break; 3265 } 3266 3267 if (Rm != 0xF) { // Writeback 3268 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3269 return MCDisassembler::Fail; 3270 } 3271 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3272 return MCDisassembler::Fail; 3273 Inst.addOperand(MCOperand::CreateImm(align)); 3274 if (Rm != 0xF) { 3275 if (Rm != 0xD) { 3276 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3277 return MCDisassembler::Fail; 3278 } else 3279 Inst.addOperand(MCOperand::CreateReg(0)); 3280 } 3281 3282 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3283 return MCDisassembler::Fail; 3284 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3285 return MCDisassembler::Fail; 3286 Inst.addOperand(MCOperand::CreateImm(index)); 3287 3288 return S; 3289 } 3290 3291 3292 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 3293 uint64_t Address, const void *Decoder) { 3294 DecodeStatus S = MCDisassembler::Success; 3295 3296 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3297 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3298 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3299 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3300 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3301 3302 unsigned align = 0; 3303 unsigned index = 0; 3304 unsigned inc = 1; 3305 switch (size) { 3306 default: 3307 return MCDisassembler::Fail; 3308 case 0: 3309 if (fieldFromInstruction32(Insn, 4, 1)) 3310 return MCDisassembler::Fail; // UNDEFINED 3311 index = fieldFromInstruction32(Insn, 5, 3); 3312 break; 3313 case 1: 3314 if (fieldFromInstruction32(Insn, 4, 1)) 3315 return MCDisassembler::Fail; // UNDEFINED 3316 index = fieldFromInstruction32(Insn, 6, 2); 3317 if (fieldFromInstruction32(Insn, 5, 1)) 3318 inc = 2; 3319 break; 3320 case 2: 3321 if (fieldFromInstruction32(Insn, 4, 2)) 3322 return MCDisassembler::Fail; // UNDEFINED 3323 index = fieldFromInstruction32(Insn, 7, 1); 3324 if (fieldFromInstruction32(Insn, 6, 1)) 3325 inc = 2; 3326 break; 3327 } 3328 3329 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3330 return MCDisassembler::Fail; 3331 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3332 return MCDisassembler::Fail; 3333 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3334 return MCDisassembler::Fail; 3335 3336 if (Rm != 0xF) { // Writeback 3337 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3338 return MCDisassembler::Fail; 3339 } 3340 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3341 return MCDisassembler::Fail; 3342 Inst.addOperand(MCOperand::CreateImm(align)); 3343 if (Rm != 0xF) { 3344 if (Rm != 0xD) { 3345 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3346 return MCDisassembler::Fail; 3347 } else 3348 Inst.addOperand(MCOperand::CreateReg(0)); 3349 } 3350 3351 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3352 return MCDisassembler::Fail; 3353 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3354 return MCDisassembler::Fail; 3355 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3356 return MCDisassembler::Fail; 3357 Inst.addOperand(MCOperand::CreateImm(index)); 3358 3359 return S; 3360 } 3361 3362 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3363 uint64_t Address, const void *Decoder) { 3364 DecodeStatus S = MCDisassembler::Success; 3365 3366 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3367 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3368 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3369 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3370 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3371 3372 unsigned align = 0; 3373 unsigned index = 0; 3374 unsigned inc = 1; 3375 switch (size) { 3376 default: 3377 return MCDisassembler::Fail; 3378 case 0: 3379 if (fieldFromInstruction32(Insn, 4, 1)) 3380 return MCDisassembler::Fail; // UNDEFINED 3381 index = fieldFromInstruction32(Insn, 5, 3); 3382 break; 3383 case 1: 3384 if (fieldFromInstruction32(Insn, 4, 1)) 3385 return MCDisassembler::Fail; // UNDEFINED 3386 index = fieldFromInstruction32(Insn, 6, 2); 3387 if (fieldFromInstruction32(Insn, 5, 1)) 3388 inc = 2; 3389 break; 3390 case 2: 3391 if (fieldFromInstruction32(Insn, 4, 2)) 3392 return MCDisassembler::Fail; // UNDEFINED 3393 index = fieldFromInstruction32(Insn, 7, 1); 3394 if (fieldFromInstruction32(Insn, 6, 1)) 3395 inc = 2; 3396 break; 3397 } 3398 3399 if (Rm != 0xF) { // Writeback 3400 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3401 return MCDisassembler::Fail; 3402 } 3403 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3404 return MCDisassembler::Fail; 3405 Inst.addOperand(MCOperand::CreateImm(align)); 3406 if (Rm != 0xF) { 3407 if (Rm != 0xD) { 3408 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3409 return MCDisassembler::Fail; 3410 } else 3411 Inst.addOperand(MCOperand::CreateReg(0)); 3412 } 3413 3414 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3415 return MCDisassembler::Fail; 3416 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3417 return MCDisassembler::Fail; 3418 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3419 return MCDisassembler::Fail; 3420 Inst.addOperand(MCOperand::CreateImm(index)); 3421 3422 return S; 3423 } 3424 3425 3426 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3427 uint64_t Address, const void *Decoder) { 3428 DecodeStatus S = MCDisassembler::Success; 3429 3430 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3431 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3432 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3433 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3434 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3435 3436 unsigned align = 0; 3437 unsigned index = 0; 3438 unsigned inc = 1; 3439 switch (size) { 3440 default: 3441 return MCDisassembler::Fail; 3442 case 0: 3443 if (fieldFromInstruction32(Insn, 4, 1)) 3444 align = 4; 3445 index = fieldFromInstruction32(Insn, 5, 3); 3446 break; 3447 case 1: 3448 if (fieldFromInstruction32(Insn, 4, 1)) 3449 align = 8; 3450 index = fieldFromInstruction32(Insn, 6, 2); 3451 if (fieldFromInstruction32(Insn, 5, 1)) 3452 inc = 2; 3453 break; 3454 case 2: 3455 if (fieldFromInstruction32(Insn, 4, 2)) 3456 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3457 index = fieldFromInstruction32(Insn, 7, 1); 3458 if (fieldFromInstruction32(Insn, 6, 1)) 3459 inc = 2; 3460 break; 3461 } 3462 3463 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3464 return MCDisassembler::Fail; 3465 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3466 return MCDisassembler::Fail; 3467 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3468 return MCDisassembler::Fail; 3469 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3470 return MCDisassembler::Fail; 3471 3472 if (Rm != 0xF) { // Writeback 3473 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3474 return MCDisassembler::Fail; 3475 } 3476 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3477 return MCDisassembler::Fail; 3478 Inst.addOperand(MCOperand::CreateImm(align)); 3479 if (Rm != 0xF) { 3480 if (Rm != 0xD) { 3481 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3482 return MCDisassembler::Fail; 3483 } else 3484 Inst.addOperand(MCOperand::CreateReg(0)); 3485 } 3486 3487 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3488 return MCDisassembler::Fail; 3489 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3490 return MCDisassembler::Fail; 3491 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3492 return MCDisassembler::Fail; 3493 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3494 return MCDisassembler::Fail; 3495 Inst.addOperand(MCOperand::CreateImm(index)); 3496 3497 return S; 3498 } 3499 3500 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3501 uint64_t Address, const void *Decoder) { 3502 DecodeStatus S = MCDisassembler::Success; 3503 3504 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3505 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3506 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3507 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3508 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3509 3510 unsigned align = 0; 3511 unsigned index = 0; 3512 unsigned inc = 1; 3513 switch (size) { 3514 default: 3515 return MCDisassembler::Fail; 3516 case 0: 3517 if (fieldFromInstruction32(Insn, 4, 1)) 3518 align = 4; 3519 index = fieldFromInstruction32(Insn, 5, 3); 3520 break; 3521 case 1: 3522 if (fieldFromInstruction32(Insn, 4, 1)) 3523 align = 8; 3524 index = fieldFromInstruction32(Insn, 6, 2); 3525 if (fieldFromInstruction32(Insn, 5, 1)) 3526 inc = 2; 3527 break; 3528 case 2: 3529 if (fieldFromInstruction32(Insn, 4, 2)) 3530 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3531 index = fieldFromInstruction32(Insn, 7, 1); 3532 if (fieldFromInstruction32(Insn, 6, 1)) 3533 inc = 2; 3534 break; 3535 } 3536 3537 if (Rm != 0xF) { // Writeback 3538 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3539 return MCDisassembler::Fail; 3540 } 3541 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3542 return MCDisassembler::Fail; 3543 Inst.addOperand(MCOperand::CreateImm(align)); 3544 if (Rm != 0xF) { 3545 if (Rm != 0xD) { 3546 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3547 return MCDisassembler::Fail; 3548 } else 3549 Inst.addOperand(MCOperand::CreateReg(0)); 3550 } 3551 3552 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3553 return MCDisassembler::Fail; 3554 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3555 return MCDisassembler::Fail; 3556 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3557 return MCDisassembler::Fail; 3558 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3559 return MCDisassembler::Fail; 3560 Inst.addOperand(MCOperand::CreateImm(index)); 3561 3562 return S; 3563 } 3564 3565 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 3566 uint64_t Address, const void *Decoder) { 3567 DecodeStatus S = MCDisassembler::Success; 3568 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3569 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3570 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3571 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3572 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3573 3574 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3575 S = MCDisassembler::SoftFail; 3576 3577 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3578 return MCDisassembler::Fail; 3579 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3580 return MCDisassembler::Fail; 3581 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3582 return MCDisassembler::Fail; 3583 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3584 return MCDisassembler::Fail; 3585 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3586 return MCDisassembler::Fail; 3587 3588 return S; 3589 } 3590 3591 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 3592 uint64_t Address, const void *Decoder) { 3593 DecodeStatus S = MCDisassembler::Success; 3594 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3595 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3596 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3597 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3598 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3599 3600 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3601 S = MCDisassembler::SoftFail; 3602 3603 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3604 return MCDisassembler::Fail; 3605 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3606 return MCDisassembler::Fail; 3607 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3608 return MCDisassembler::Fail; 3609 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3610 return MCDisassembler::Fail; 3611 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3612 return MCDisassembler::Fail; 3613 3614 return S; 3615 } 3616 3617 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn, 3618 uint64_t Address, const void *Decoder) { 3619 DecodeStatus S = MCDisassembler::Success; 3620 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 3621 // The InstPrinter needs to have the low bit of the predicate in 3622 // the mask operand to be able to print it properly. 3623 unsigned mask = fieldFromInstruction16(Insn, 0, 5); 3624 3625 if (pred == 0xF) { 3626 pred = 0xE; 3627 S = MCDisassembler::SoftFail; 3628 } 3629 3630 if ((mask & 0xF) == 0) { 3631 // Preserve the high bit of the mask, which is the low bit of 3632 // the predicate. 3633 mask &= 0x10; 3634 mask |= 0x8; 3635 S = MCDisassembler::SoftFail; 3636 } 3637 3638 Inst.addOperand(MCOperand::CreateImm(pred)); 3639 Inst.addOperand(MCOperand::CreateImm(mask)); 3640 return S; 3641 } 3642