History log of /dpdk/drivers/net/qede/base/ecore_dev.c (Results 1 – 25 of 132)
Revision Date Author Comments
# 92c6786e 25-Sep-2020 Manish Chopra <manishc@marvell.com>

net/qede: define PCI config space specific osals

This patch defines various PCI config space access APIs
in order to read and find IOV specific PCI capabilities.

With these definitions implemented,

net/qede: define PCI config space specific osals

This patch defines various PCI config space access APIs
in order to read and find IOV specific PCI capabilities.

With these definitions implemented, it enables the base
driver to do SR-IOV specific initialization and HW specific
configuration required from PF-PMD driver instance.

Signed-off-by: Manish Chopra <manishc@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: Rasesh Mody <rmody@marvell.com>

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# 2352f348 08-Jul-2020 Rasesh Mody <rmody@marvell.com>

net/qede/base: add changes for debug data collection

This patch adds base driver APIs required for debug data collection.
It adds support for dumping internal lookup tables(ilt), reading nvram
image

net/qede/base: add changes for debug data collection

This patch adds base driver APIs required for debug data collection.
It adds support for dumping internal lookup tables(ilt), reading nvram
image, register definitions.

Signed-off-by: Rasesh Mody <rmody@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>

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# 519438f7 08-Jul-2020 Rasesh Mody <rmody@marvell.com>

net/qede/base: re-arrange few structures for DDC

This patch rearranges some of the base driver structures which will be
also used by debug data collection (DDC) implementation. It adds a new
file ec

net/qede/base: re-arrange few structures for DDC

This patch rearranges some of the base driver structures which will be
also used by debug data collection (DDC) implementation. It adds a new
file ecore_hsi_func_common.h with Physical, Virtual memory descriptors.

Signed-off-by: Rasesh Mody <rmody@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>

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# 5018f1fc 27-Apr-2020 Joyce Kong <joyce.kong@arm.com>

net/qede: use common bit operations API

Remove its own bit operation APIs and use the common one,
this can reduce the code duplication largely.

Signed-off-by: Joyce Kong <joyce.kong@arm.com>
Review

net/qede: use common bit operations API

Remove its own bit operation APIs and use the common one,
this can reduce the code duplication largely.

Signed-off-by: Joyce Kong <joyce.kong@arm.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>

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# f44ca48c 06-Feb-2020 Manish Chopra <manishc@marvell.com>

net/qede: fix VF reload

On ungraceful termination of DPDK application, PMD VF driver
fails to re-load due to PF seeing the VF in unexpected state
during VF acquisition handshake.

This patch fixes i

net/qede: fix VF reload

On ungraceful termination of DPDK application, PMD VF driver
fails to re-load due to PF seeing the VF in unexpected state
during VF acquisition handshake.

This patch fixes it by allowing VF to request the PF for soft
FLR during the load in such cases so that it can get cleanly
re-loaded.

Fixes: 2ea6f76aff40 ("qede: add core driver")
Cc: stable@dpdk.org

Signed-off-by: Manish Chopra <manishc@marvell.com>
Signed-off-by: Shahed Shaikh <shshaikh@marvell.com>
Signed-off-by: Rasesh Mody <rmody@marvell.com>
Acked-by: Rasesh Mody <rmody@marvell.com>

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# 117e4a77 21-Dec-2019 Rasesh Mody <rmody@marvell.com>

net/qede/base: fix number of ports per engine

Fix the way in which the number of ports per engine of an adapter is
determined by reading port mode register. Set default value to 1.

Fixes: 3b307c55f

net/qede/base: fix number of ports per engine

Fix the way in which the number of ports per engine of an adapter is
determined by reading port mode register. Set default value to 1.

Fixes: 3b307c55f2ac ("net/qede/base: update FW to 8.40.25.0")
Cc: stable@dpdk.org

Signed-off-by: Rasesh Mody <rmody@marvell.com>

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# 58bb1ee4 20-Oct-2019 Rasesh Mody <rmody@marvell.com>

net/qede/base: update FW to 8.40.33.0

In our testing we have identified a critical FW bug. Performance
is degraded significantly for certain packet sizes with 8.40.25.0 FW.

This patch updates the F

net/qede/base: update FW to 8.40.33.0

In our testing we have identified a critical FW bug. Performance
is degraded significantly for certain packet sizes with 8.40.25.0 FW.

This patch updates the FW to version 8.40.33.0. The updated FW has a
fix to performance issue.

The patch also adds initialization for FW overlay RAM as part of
hardware initialization which is required by the new FW.

Fixes: 3b307c55f2ac ("net/qede/base: update FW to 8.40.25.0")
Cc: stable@dpdk.org

Signed-off-by: Rasesh Mody <rmody@marvell.com>

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# 3b307c55 06-Oct-2019 Rasesh Mody <rmody@marvell.com>

net/qede/base: update FW to 8.40.25.0

This patch updates the FW to 8.40.25.0 and corresponding base driver
changes. It also updates the PMD version to 2.11.0.1. The FW updates
consists of enhancemen

net/qede/base: update FW to 8.40.25.0

This patch updates the FW to 8.40.25.0 and corresponding base driver
changes. It also updates the PMD version to 2.11.0.1. The FW updates
consists of enhancements and fixes as described below.

- VF RX queue start ramrod can get stuck due to completion error.
Return EQ completion with error, when fail to load VF data. Use VF
FID in RX queue start ramrod
- Fix big receive buffer initialization for 100G to address failure
leading to BRB hardware assertion
- GRE tunnel traffic doesn't run when non-L2 ethernet protocol is
enabled, fix FW to not forward tunneled SYN packets to LL2.
- Fix the FW assert that is caused during vport_update when
tx-switching is enabled
- Add initial FW support for VF Representors
- Add ecore_get_hsi_def_val() API to get default HSI values
- Move following from .c to .h files:
TSTORM_QZONE_START and MSTORM_QZONE_START
enum ilt_clients
renamed struct ecore_dma_mem to phys_mem_desc and moved
- Add ecore_cxt_set_cli() and ecore_cxt_set_blk() APIs to set client
config and block details
- Use SET_FIELD() macro where appropriate
- Address spell check and code alignment issues

Signed-off-by: Rasesh Mody <rmody@marvell.com>

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# 7ed1cd53 06-Oct-2019 Rasesh Mody <rmody@marvell.com>

net/qede/base: update HSI

Update hardware software common base driver code in preparation to
update the firmware to version 8.40.25.0.

Signed-off-by: Rasesh Mody <rmody@marvell.com>


# ea85629f 06-Oct-2019 Rasesh Mody <rmody@marvell.com>

net/qede/base: move DMAE to HSI

Move DMA engine (DMAE) structures from base driver to HSI module.
Use DMAE_PARAMS_* in place of ECORE_DMAE_FLAG_*.
Enforce SET_FIELD() macro where appropriate.

Signe

net/qede/base: move DMAE to HSI

Move DMA engine (DMAE) structures from base driver to HSI module.
Use DMAE_PARAMS_* in place of ECORE_DMAE_FLAG_*.
Enforce SET_FIELD() macro where appropriate.

Signed-off-by: Rasesh Mody <rmody@marvell.com>

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# 52fa735c 06-Oct-2019 Rasesh Mody <rmody@marvell.com>

net/qede/base: rename HSI datatypes and functions

This patch changes code with E4/E5/e4/e5/BB_K2 prefixes and suffixes.
- HSI datatypes renaming - removed all e5 datatypes and renamed
all e4 dat

net/qede/base: rename HSI datatypes and functions

This patch changes code with E4/E5/e4/e5/BB_K2 prefixes and suffixes.
- HSI datatypes renaming - removed all e5 datatypes and renamed
all e4 datatypes to be prefix less/suffix less.
(s/_E4//; s/_e4//; s/E4_//).
- HSI functions - removed e4/e5 prefixes/suffixes.

Signed-off-by: Rasesh Mody <rmody@marvell.com>

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# 8e950a86 06-Oct-2019 Rasesh Mody <rmody@marvell.com>

net/qede/base: lock entire QM reconfiguration flow

Multiple flows can issue QM reconfiguration, hence hold the lock longer
to account for entire duration of reconfiguration flow.

Signed-off-by: Ras

net/qede/base: lock entire QM reconfiguration flow

Multiple flows can issue QM reconfiguration, hence hold the lock longer
to account for entire duration of reconfiguration flow.

Signed-off-by: Rasesh Mody <rmody@marvell.com>

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# 66c4904f 31-Oct-2018 Rasesh Mody <rasesh.mody@cavium.com>

net/qede/base: fix to initialize HW for LLH filters

During initialization of leading PF, we need to initialize HW for LLH
filters. Set HW init parameter to set the engine affinity for
multiple engin

net/qede/base: fix to initialize HW for LLH filters

During initialization of leading PF, we need to initialize HW for LLH
filters. Set HW init parameter to set the engine affinity for
multiple engine adapters.

Fixes: 3eed444a9621 ("net/qede/base: changes for 100G")

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>

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# 3eed444a 29-Sep-2018 Rasesh Mody <rasesh.mody@cavium.com>

net/qede/base: changes for 100G

Change details:

- Get engine affinity from the management FW and configure accordingly
- Add an LLH filter with the primary MAC address in QPAR/NPAR
- Move some o

net/qede/base: changes for 100G

Change details:

- Get engine affinity from the management FW and configure accordingly
- Add an LLH filter with the primary MAC address in QPAR/NPAR
- Move some of the LLH APIs around
- Add PPFID APIs
- Update all allocated ppfids with the same value for the
following PORT_PF registers:
NIG_REG_DSCP_TO_TC_MAP_ENABLE
- Add port_id, src_pfid and dst_pfid to DMA engine params

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>

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# 54f74d6a 29-Sep-2018 Rasesh Mody <rasesh.mody@cavium.com>

net/qede/base: get pre-negotiated OEM values

Request management FW for OEM values, which are negotiated prior to
the driver load by sending the GET_OEM_UPDATES command after both
engines are initial

net/qede/base: get pre-negotiated OEM values

Request management FW for OEM values, which are negotiated prior to
the driver load by sending the GET_OEM_UPDATES command after both
engines are initialized.

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>

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# 7b49adea 29-Sep-2018 Rasesh Mody <rasesh.mody@cavium.com>

net/qede/base: adjust queue manager idx greater than max

Modified queue manager getter APIs to cycle through their range if
index is higher than max. This prevents accessing index out of bounds.

Si

net/qede/base: adjust queue manager idx greater than max

Modified queue manager getter APIs to cycle through their range if
index is higher than max. This prevents accessing index out of bounds.

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>

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# bf03492a 29-Sep-2018 Rasesh Mody <rasesh.mody@cavium.com>

net/qede/base: add mf-bit/API for FIP special mode

Add mf-bit/API for FIP special mode.

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>


# cbc23596 29-Sep-2018 Rasesh Mody <rasesh.mody@cavium.com>

net/qede/base: add DPC sync after PF stop

Add DPC sync after stopping the physical funciton to allow clean up of
asyncronous events. Post this the driver don't expect the FW to send
async events.

S

net/qede/base: add DPC sync after PF stop

Add DPC sync after stopping the physical funciton to allow clean up of
asyncronous events. Post this the driver don't expect the FW to send
async events.

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>

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# f32557f9 29-Sep-2018 Rasesh Mody <rasesh.mody@cavium.com>

net/qede/base: check for EDPM enabled in DB recovery

Add a check for EDPM enabled before flushing doorbell recovery queue.

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>


# 3c361686 29-Sep-2018 Rasesh Mody <rasesh.mody@cavium.com>

net/qede/base: upgrade to FW 8.37.7.0

This patch adds changes to base driver for upgrading to 8.37.3.0 FW.

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>


# 797ce8ee 08-Sep-2018 Shahed Shaikh <shahed.shaikh@cavium.com>

net/qede/base: fix MFW FLR flow

Management firmware does not properly clean IGU block in PF FLR flow
which may result in undelivered attentions for link events from
default status block.
Add a worka

net/qede/base: fix MFW FLR flow

Management firmware does not properly clean IGU block in PF FLR flow
which may result in undelivered attentions for link events from
default status block.
Add a workaround in PMD to execute extra IGU cleanup right after PF FLR
is done.

Fixes: 9e2f08a4ad5f ("net/qede/base: add request for PF FLR before load request")
Cc: stable@dpdk.org

Signed-off-by: Shahed Shaikh <shahed.shaikh@cavium.com>

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# 3f11cf06 08-Sep-2018 Rasesh Mody <rasesh.mody@cavium.com>

net/qede/base: limit number of non ethernet queues to 64

Limit the number of non ethernet queues to 64, allowing a max queues to
status block ratio of 2:1 in case of storage target. Theoretically a

net/qede/base: limit number of non ethernet queues to 64

Limit the number of non ethernet queues to 64, allowing a max queues to
status block ratio of 2:1 in case of storage target. Theoretically a
non-target storage PF can have 128 queues and SBs.

This change is to support 64 entries for a target iSCSI/FCoE PF and 128
for a non-target.

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>

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# d5df6159 08-Sep-2018 Rasesh Mody <rasesh.mody@cavium.com>

net/qede: fix ethernet type in HW registers

Fix to program the HW registers with proper ether type.

Fixes: 36f45bce2537 ("net/qede/base: fix to support OVLAN mode")
Cc: stable@dpdk.org

Signed-off-

net/qede: fix ethernet type in HW registers

Fix to program the HW registers with proper ether type.

Fixes: 36f45bce2537 ("net/qede/base: fix to support OVLAN mode")
Cc: stable@dpdk.org

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>

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# 4fe58a3e 08-Sep-2018 Rasesh Mody <rasesh.mody@cavium.com>

net/qede/base: get pre-negotiated values for stag and bw

Request management FW for STAG and bandwidth values negotiated prior to
the driver load.

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>


# ebbc55b8 08-Sep-2018 Rasesh Mody <rasesh.mody@cavium.com>

net/qede/base: add OneView APIs

Add support for the following OneView APIs:
- ecore_mcp_ov_update_mtu() - Send MTU value to the management FW.
- ecore_mcp_ov_update_mac() - Send MAC address to the

net/qede/base: add OneView APIs

Add support for the following OneView APIs:
- ecore_mcp_ov_update_mtu() - Send MTU value to the management FW.
- ecore_mcp_ov_update_mac() - Send MAC address to the management FW.
- ecore_mcp_ov_update_eswitch() - Send eswitch_mode to management FW
after the firmware load.

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>

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