1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2016 - 2018 Cavium Inc. 3 * All rights reserved. 4 * www.cavium.com 5 */ 6 7 #include "bcm_osal.h" 8 #include "reg_addr.h" 9 #include "ecore_gtt_reg_addr.h" 10 #include "ecore.h" 11 #include "ecore_chain.h" 12 #include "ecore_status.h" 13 #include "ecore_hw.h" 14 #include "ecore_rt_defs.h" 15 #include "ecore_init_ops.h" 16 #include "ecore_int.h" 17 #include "ecore_cxt.h" 18 #include "ecore_spq.h" 19 #include "ecore_init_fw_funcs.h" 20 #include "ecore_sp_commands.h" 21 #include "ecore_dev_api.h" 22 #include "ecore_sriov.h" 23 #include "ecore_vf.h" 24 #include "ecore_mcp.h" 25 #include "ecore_hw_defs.h" 26 #include "mcp_public.h" 27 #include "ecore_iro.h" 28 #include "nvm_cfg.h" 29 #include "ecore_dcbx.h" 30 #include "ecore_l2.h" 31 32 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM 33 * registers involved are not split and thus configuration is a race where 34 * some of the PFs configuration might be lost. 35 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration 36 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where 37 * there's more than a single compiled ecore component in system]. 38 */ 39 static osal_spinlock_t qm_lock; 40 static u32 qm_lock_ref_cnt; 41 42 /******************** Doorbell Recovery *******************/ 43 /* The doorbell recovery mechanism consists of a list of entries which represent 44 * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each 45 * entity needs to register with the mechanism and provide the parameters 46 * describing it's doorbell, including a location where last used doorbell data 47 * can be found. The doorbell execute function will traverse the list and 48 * doorbell all of the registered entries. 49 */ 50 struct ecore_db_recovery_entry { 51 osal_list_entry_t list_entry; 52 void OSAL_IOMEM *db_addr; 53 void *db_data; 54 enum ecore_db_rec_width db_width; 55 enum ecore_db_rec_space db_space; 56 u8 hwfn_idx; 57 }; 58 59 /* display a single doorbell recovery entry */ 60 void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn, 61 struct ecore_db_recovery_entry *db_entry, 62 const char *action) 63 { 64 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n", 65 action, db_entry, db_entry->db_addr, db_entry->db_data, 66 db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b", 67 db_entry->db_space == DB_REC_USER ? "user" : "kernel", 68 db_entry->hwfn_idx); 69 } 70 71 /* doorbell address sanity (address within doorbell bar range) */ 72 bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr, 73 void *db_data) 74 { 75 /* make sure doorbell address is within the doorbell bar */ 76 if (db_addr < p_dev->doorbells || (u8 *)db_addr > 77 (u8 *)p_dev->doorbells + p_dev->db_size) { 78 OSAL_WARN(true, 79 "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n", 80 db_addr, p_dev->doorbells, 81 (u8 *)p_dev->doorbells + p_dev->db_size); 82 return false; 83 } 84 85 /* make sure doorbell data pointer is not null */ 86 if (!db_data) { 87 OSAL_WARN(true, "Illegal doorbell data pointer: %p", db_data); 88 return false; 89 } 90 91 return true; 92 } 93 94 /* find hwfn according to the doorbell address */ 95 struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev, 96 void OSAL_IOMEM *db_addr) 97 { 98 struct ecore_hwfn *p_hwfn; 99 100 /* In CMT doorbell bar is split down the middle between engine 0 and 101 * enigne 1 102 */ 103 if (ECORE_IS_CMT(p_dev)) 104 p_hwfn = db_addr < p_dev->hwfns[1].doorbells ? 105 &p_dev->hwfns[0] : &p_dev->hwfns[1]; 106 else 107 p_hwfn = ECORE_LEADING_HWFN(p_dev); 108 109 return p_hwfn; 110 } 111 112 /* add a new entry to the doorbell recovery mechanism */ 113 enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev, 114 void OSAL_IOMEM *db_addr, 115 void *db_data, 116 enum ecore_db_rec_width db_width, 117 enum ecore_db_rec_space db_space) 118 { 119 struct ecore_db_recovery_entry *db_entry; 120 struct ecore_hwfn *p_hwfn; 121 122 /* shortcircuit VFs, for now */ 123 if (IS_VF(p_dev)) { 124 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n"); 125 return ECORE_SUCCESS; 126 } 127 128 /* sanitize doorbell address */ 129 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data)) 130 return ECORE_INVAL; 131 132 /* obtain hwfn from doorbell address */ 133 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr); 134 135 /* create entry */ 136 db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry)); 137 if (!db_entry) { 138 DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n"); 139 return ECORE_NOMEM; 140 } 141 142 /* populate entry */ 143 db_entry->db_addr = db_addr; 144 db_entry->db_data = db_data; 145 db_entry->db_width = db_width; 146 db_entry->db_space = db_space; 147 db_entry->hwfn_idx = p_hwfn->my_id; 148 149 /* display */ 150 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding"); 151 152 /* protect the list */ 153 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock); 154 OSAL_LIST_PUSH_TAIL(&db_entry->list_entry, 155 &p_hwfn->db_recovery_info.list); 156 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock); 157 158 return ECORE_SUCCESS; 159 } 160 161 /* remove an entry from the doorbell recovery mechanism */ 162 enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev, 163 void OSAL_IOMEM *db_addr, 164 void *db_data) 165 { 166 struct ecore_db_recovery_entry *db_entry = OSAL_NULL; 167 enum _ecore_status_t rc = ECORE_INVAL; 168 struct ecore_hwfn *p_hwfn; 169 170 /* shortcircuit VFs, for now */ 171 if (IS_VF(p_dev)) { 172 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n"); 173 return ECORE_SUCCESS; 174 } 175 176 /* sanitize doorbell address */ 177 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data)) 178 return ECORE_INVAL; 179 180 /* obtain hwfn from doorbell address */ 181 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr); 182 183 /* protect the list */ 184 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock); 185 OSAL_LIST_FOR_EACH_ENTRY(db_entry, 186 &p_hwfn->db_recovery_info.list, 187 list_entry, 188 struct ecore_db_recovery_entry) { 189 /* search according to db_data addr since db_addr is not unique 190 * (roce) 191 */ 192 if (db_entry->db_data == db_data) { 193 ecore_db_recovery_dp_entry(p_hwfn, db_entry, 194 "Deleting"); 195 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry, 196 &p_hwfn->db_recovery_info.list); 197 rc = ECORE_SUCCESS; 198 break; 199 } 200 } 201 202 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock); 203 204 if (rc == ECORE_INVAL) 205 /*OSAL_WARN(true,*/ 206 DP_NOTICE(p_hwfn, false, 207 "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n", 208 db_data, db_addr); 209 else 210 OSAL_FREE(p_dev, db_entry); 211 212 return rc; 213 } 214 215 /* initialize the doorbell recovery mechanism */ 216 enum _ecore_status_t ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn) 217 { 218 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n"); 219 220 /* make sure db_size was set in p_dev */ 221 if (!p_hwfn->p_dev->db_size) { 222 DP_ERR(p_hwfn->p_dev, "db_size not set\n"); 223 return ECORE_INVAL; 224 } 225 226 OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list); 227 #ifdef CONFIG_ECORE_LOCK_ALLOC 228 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock)) 229 return ECORE_NOMEM; 230 #endif 231 OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock); 232 p_hwfn->db_recovery_info.db_recovery_counter = 0; 233 234 return ECORE_SUCCESS; 235 } 236 237 /* destroy the doorbell recovery mechanism */ 238 void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn) 239 { 240 struct ecore_db_recovery_entry *db_entry = OSAL_NULL; 241 242 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n"); 243 if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) { 244 DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n"); 245 while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) { 246 db_entry = OSAL_LIST_FIRST_ENTRY( 247 &p_hwfn->db_recovery_info.list, 248 struct ecore_db_recovery_entry, 249 list_entry); 250 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging"); 251 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry, 252 &p_hwfn->db_recovery_info.list); 253 OSAL_FREE(p_hwfn->p_dev, db_entry); 254 } 255 } 256 #ifdef CONFIG_ECORE_LOCK_ALLOC 257 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock); 258 #endif 259 p_hwfn->db_recovery_info.db_recovery_counter = 0; 260 } 261 262 /* print the content of the doorbell recovery mechanism */ 263 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn) 264 { 265 struct ecore_db_recovery_entry *db_entry = OSAL_NULL; 266 267 DP_NOTICE(p_hwfn, false, 268 "Dispalying doorbell recovery database. Counter was %d\n", 269 p_hwfn->db_recovery_info.db_recovery_counter); 270 271 /* protect the list */ 272 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock); 273 OSAL_LIST_FOR_EACH_ENTRY(db_entry, 274 &p_hwfn->db_recovery_info.list, 275 list_entry, 276 struct ecore_db_recovery_entry) { 277 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing"); 278 } 279 280 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock); 281 } 282 283 /* ring the doorbell of a single doorbell recovery entry */ 284 void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn, 285 struct ecore_db_recovery_entry *db_entry, 286 enum ecore_db_rec_exec db_exec) 287 { 288 /* Print according to width */ 289 if (db_entry->db_width == DB_REC_WIDTH_32B) 290 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %x\n", 291 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing", 292 db_entry->db_addr, *(u32 *)db_entry->db_data); 293 else 294 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %lx\n", 295 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing", 296 db_entry->db_addr, 297 *(unsigned long *)(db_entry->db_data)); 298 299 /* Sanity */ 300 if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr, 301 db_entry->db_data)) 302 return; 303 304 /* Flush the write combined buffer. Since there are multiple doorbelling 305 * entities using the same address, if we don't flush, a transaction 306 * could be lost. 307 */ 308 OSAL_WMB(p_hwfn->p_dev); 309 310 /* Ring the doorbell */ 311 if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) { 312 if (db_entry->db_width == DB_REC_WIDTH_32B) 313 DIRECT_REG_WR(p_hwfn, db_entry->db_addr, 314 *(u32 *)(db_entry->db_data)); 315 else 316 DIRECT_REG_WR64(p_hwfn, db_entry->db_addr, 317 *(u64 *)(db_entry->db_data)); 318 } 319 320 /* Flush the write combined buffer. Next doorbell may come from a 321 * different entity to the same address... 322 */ 323 OSAL_WMB(p_hwfn->p_dev); 324 } 325 326 /* traverse the doorbell recovery entry list and ring all the doorbells */ 327 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn, 328 enum ecore_db_rec_exec db_exec) 329 { 330 struct ecore_db_recovery_entry *db_entry = OSAL_NULL; 331 332 if (db_exec != DB_REC_ONCE) { 333 DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n", 334 p_hwfn->db_recovery_info.db_recovery_counter); 335 336 /* track amount of times recovery was executed */ 337 p_hwfn->db_recovery_info.db_recovery_counter++; 338 } 339 340 /* protect the list */ 341 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock); 342 OSAL_LIST_FOR_EACH_ENTRY(db_entry, 343 &p_hwfn->db_recovery_info.list, 344 list_entry, 345 struct ecore_db_recovery_entry) { 346 ecore_db_recovery_ring(p_hwfn, db_entry, db_exec); 347 if (db_exec == DB_REC_ONCE) 348 break; 349 } 350 351 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock); 352 } 353 /******************** Doorbell Recovery end ****************/ 354 355 /********************************** NIG LLH ***********************************/ 356 357 enum ecore_llh_filter_type { 358 ECORE_LLH_FILTER_TYPE_MAC, 359 ECORE_LLH_FILTER_TYPE_PROTOCOL, 360 }; 361 362 struct ecore_llh_mac_filter { 363 u8 addr[ETH_ALEN]; 364 }; 365 366 struct ecore_llh_protocol_filter { 367 enum ecore_llh_prot_filter_type_t type; 368 u16 source_port_or_eth_type; 369 u16 dest_port; 370 }; 371 372 union ecore_llh_filter { 373 struct ecore_llh_mac_filter mac; 374 struct ecore_llh_protocol_filter protocol; 375 }; 376 377 struct ecore_llh_filter_info { 378 bool b_enabled; 379 u32 ref_cnt; 380 enum ecore_llh_filter_type type; 381 union ecore_llh_filter filter; 382 }; 383 384 struct ecore_llh_info { 385 /* Number of LLH filters banks */ 386 u8 num_ppfid; 387 388 #define MAX_NUM_PPFID 8 389 u8 ppfid_array[MAX_NUM_PPFID]; 390 391 /* Array of filters arrays: 392 * "num_ppfid" elements of filters banks, where each is an array of 393 * "NIG_REG_LLH_FUNC_FILTER_EN_SIZE" filters. 394 */ 395 struct ecore_llh_filter_info **pp_filters; 396 }; 397 398 static void ecore_llh_free(struct ecore_dev *p_dev) 399 { 400 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info; 401 u32 i; 402 403 if (p_llh_info != OSAL_NULL) { 404 if (p_llh_info->pp_filters != OSAL_NULL) { 405 for (i = 0; i < p_llh_info->num_ppfid; i++) 406 OSAL_FREE(p_dev, p_llh_info->pp_filters[i]); 407 } 408 409 OSAL_FREE(p_dev, p_llh_info->pp_filters); 410 } 411 412 OSAL_FREE(p_dev, p_llh_info); 413 p_dev->p_llh_info = OSAL_NULL; 414 } 415 416 static enum _ecore_status_t ecore_llh_alloc(struct ecore_dev *p_dev) 417 { 418 struct ecore_llh_info *p_llh_info; 419 u32 size; 420 u8 i; 421 422 p_llh_info = OSAL_ZALLOC(p_dev, GFP_KERNEL, sizeof(*p_llh_info)); 423 if (!p_llh_info) 424 return ECORE_NOMEM; 425 p_dev->p_llh_info = p_llh_info; 426 427 for (i = 0; i < MAX_NUM_PPFID; i++) { 428 if (!(p_dev->ppfid_bitmap & (0x1 << i))) 429 continue; 430 431 p_llh_info->ppfid_array[p_llh_info->num_ppfid] = i; 432 DP_VERBOSE(p_dev, ECORE_MSG_SP, "ppfid_array[%d] = %hhd\n", 433 p_llh_info->num_ppfid, i); 434 p_llh_info->num_ppfid++; 435 } 436 437 size = p_llh_info->num_ppfid * sizeof(*p_llh_info->pp_filters); 438 p_llh_info->pp_filters = OSAL_ZALLOC(p_dev, GFP_KERNEL, size); 439 if (!p_llh_info->pp_filters) 440 return ECORE_NOMEM; 441 442 size = NIG_REG_LLH_FUNC_FILTER_EN_SIZE * 443 sizeof(**p_llh_info->pp_filters); 444 for (i = 0; i < p_llh_info->num_ppfid; i++) { 445 p_llh_info->pp_filters[i] = OSAL_ZALLOC(p_dev, GFP_KERNEL, 446 size); 447 if (!p_llh_info->pp_filters[i]) 448 return ECORE_NOMEM; 449 } 450 451 return ECORE_SUCCESS; 452 } 453 454 static enum _ecore_status_t ecore_llh_shadow_sanity(struct ecore_dev *p_dev, 455 u8 ppfid, u8 filter_idx, 456 const char *action) 457 { 458 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info; 459 460 if (ppfid >= p_llh_info->num_ppfid) { 461 DP_NOTICE(p_dev, false, 462 "LLH shadow [%s]: using ppfid %d while only %d ppfids are available\n", 463 action, ppfid, p_llh_info->num_ppfid); 464 return ECORE_INVAL; 465 } 466 467 if (filter_idx >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) { 468 DP_NOTICE(p_dev, false, 469 "LLH shadow [%s]: using filter_idx %d while only %d filters are available\n", 470 action, filter_idx, NIG_REG_LLH_FUNC_FILTER_EN_SIZE); 471 return ECORE_INVAL; 472 } 473 474 return ECORE_SUCCESS; 475 } 476 477 #define ECORE_LLH_INVALID_FILTER_IDX 0xff 478 479 static enum _ecore_status_t 480 ecore_llh_shadow_search_filter(struct ecore_dev *p_dev, u8 ppfid, 481 union ecore_llh_filter *p_filter, 482 u8 *p_filter_idx) 483 { 484 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info; 485 struct ecore_llh_filter_info *p_filters; 486 enum _ecore_status_t rc; 487 u8 i; 488 489 rc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, "search"); 490 if (rc != ECORE_SUCCESS) 491 return rc; 492 493 *p_filter_idx = ECORE_LLH_INVALID_FILTER_IDX; 494 495 p_filters = p_llh_info->pp_filters[ppfid]; 496 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 497 if (!OSAL_MEMCMP(p_filter, &p_filters[i].filter, 498 sizeof(*p_filter))) { 499 *p_filter_idx = i; 500 break; 501 } 502 } 503 504 return ECORE_SUCCESS; 505 } 506 507 static enum _ecore_status_t 508 ecore_llh_shadow_get_free_idx(struct ecore_dev *p_dev, u8 ppfid, 509 u8 *p_filter_idx) 510 { 511 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info; 512 struct ecore_llh_filter_info *p_filters; 513 enum _ecore_status_t rc; 514 u8 i; 515 516 rc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, "get_free_idx"); 517 if (rc != ECORE_SUCCESS) 518 return rc; 519 520 *p_filter_idx = ECORE_LLH_INVALID_FILTER_IDX; 521 522 p_filters = p_llh_info->pp_filters[ppfid]; 523 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 524 if (!p_filters[i].b_enabled) { 525 *p_filter_idx = i; 526 break; 527 } 528 } 529 530 return ECORE_SUCCESS; 531 } 532 533 static enum _ecore_status_t 534 __ecore_llh_shadow_add_filter(struct ecore_dev *p_dev, u8 ppfid, u8 filter_idx, 535 enum ecore_llh_filter_type type, 536 union ecore_llh_filter *p_filter, u32 *p_ref_cnt) 537 { 538 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info; 539 struct ecore_llh_filter_info *p_filters; 540 enum _ecore_status_t rc; 541 542 rc = ecore_llh_shadow_sanity(p_dev, ppfid, filter_idx, "add"); 543 if (rc != ECORE_SUCCESS) 544 return rc; 545 546 p_filters = p_llh_info->pp_filters[ppfid]; 547 if (!p_filters[filter_idx].ref_cnt) { 548 p_filters[filter_idx].b_enabled = true; 549 p_filters[filter_idx].type = type; 550 OSAL_MEMCPY(&p_filters[filter_idx].filter, p_filter, 551 sizeof(p_filters[filter_idx].filter)); 552 } 553 554 *p_ref_cnt = ++p_filters[filter_idx].ref_cnt; 555 556 return ECORE_SUCCESS; 557 } 558 559 static enum _ecore_status_t 560 ecore_llh_shadow_add_filter(struct ecore_dev *p_dev, u8 ppfid, 561 enum ecore_llh_filter_type type, 562 union ecore_llh_filter *p_filter, 563 u8 *p_filter_idx, u32 *p_ref_cnt) 564 { 565 enum _ecore_status_t rc; 566 567 /* Check if the same filter already exist */ 568 rc = ecore_llh_shadow_search_filter(p_dev, ppfid, p_filter, 569 p_filter_idx); 570 if (rc != ECORE_SUCCESS) 571 return rc; 572 573 /* Find a new entry in case of a new filter */ 574 if (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) { 575 rc = ecore_llh_shadow_get_free_idx(p_dev, ppfid, p_filter_idx); 576 if (rc != ECORE_SUCCESS) 577 return rc; 578 } 579 580 /* No free entry was found */ 581 if (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) { 582 DP_NOTICE(p_dev, false, 583 "Failed to find an empty LLH filter to utilize [ppfid %d]\n", 584 ppfid); 585 return ECORE_NORESOURCES; 586 } 587 588 return __ecore_llh_shadow_add_filter(p_dev, ppfid, *p_filter_idx, type, 589 p_filter, p_ref_cnt); 590 } 591 592 static enum _ecore_status_t 593 __ecore_llh_shadow_remove_filter(struct ecore_dev *p_dev, u8 ppfid, 594 u8 filter_idx, u32 *p_ref_cnt) 595 { 596 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info; 597 struct ecore_llh_filter_info *p_filters; 598 enum _ecore_status_t rc; 599 600 rc = ecore_llh_shadow_sanity(p_dev, ppfid, filter_idx, "remove"); 601 if (rc != ECORE_SUCCESS) 602 return rc; 603 604 p_filters = p_llh_info->pp_filters[ppfid]; 605 if (!p_filters[filter_idx].ref_cnt) { 606 DP_NOTICE(p_dev, false, 607 "LLH shadow: trying to remove a filter with ref_cnt=0\n"); 608 return ECORE_INVAL; 609 } 610 611 *p_ref_cnt = --p_filters[filter_idx].ref_cnt; 612 if (!p_filters[filter_idx].ref_cnt) 613 OSAL_MEM_ZERO(&p_filters[filter_idx], 614 sizeof(p_filters[filter_idx])); 615 616 return ECORE_SUCCESS; 617 } 618 619 static enum _ecore_status_t 620 ecore_llh_shadow_remove_filter(struct ecore_dev *p_dev, u8 ppfid, 621 union ecore_llh_filter *p_filter, 622 u8 *p_filter_idx, u32 *p_ref_cnt) 623 { 624 enum _ecore_status_t rc; 625 626 rc = ecore_llh_shadow_search_filter(p_dev, ppfid, p_filter, 627 p_filter_idx); 628 if (rc != ECORE_SUCCESS) 629 return rc; 630 631 /* No matching filter was found */ 632 if (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) { 633 DP_NOTICE(p_dev, false, 634 "Failed to find a filter in the LLH shadow\n"); 635 return ECORE_INVAL; 636 } 637 638 return __ecore_llh_shadow_remove_filter(p_dev, ppfid, *p_filter_idx, 639 p_ref_cnt); 640 } 641 642 static enum _ecore_status_t 643 ecore_llh_shadow_remove_all_filters(struct ecore_dev *p_dev, u8 ppfid) 644 { 645 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info; 646 struct ecore_llh_filter_info *p_filters; 647 enum _ecore_status_t rc; 648 649 rc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, "remove_all"); 650 if (rc != ECORE_SUCCESS) 651 return rc; 652 653 p_filters = p_llh_info->pp_filters[ppfid]; 654 OSAL_MEM_ZERO(p_filters, 655 NIG_REG_LLH_FUNC_FILTER_EN_SIZE * sizeof(*p_filters)); 656 657 return ECORE_SUCCESS; 658 } 659 660 static enum _ecore_status_t ecore_abs_ppfid(struct ecore_dev *p_dev, 661 u8 rel_ppfid, u8 *p_abs_ppfid) 662 { 663 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info; 664 u8 ppfids = p_llh_info->num_ppfid - 1; 665 666 if (rel_ppfid >= p_llh_info->num_ppfid) { 667 DP_NOTICE(p_dev, false, 668 "rel_ppfid %d is not valid, available indices are 0..%hhd\n", 669 rel_ppfid, ppfids); 670 return ECORE_INVAL; 671 } 672 673 *p_abs_ppfid = p_llh_info->ppfid_array[rel_ppfid]; 674 675 return ECORE_SUCCESS; 676 } 677 678 static enum _ecore_status_t 679 __ecore_llh_set_engine_affin(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) 680 { 681 struct ecore_dev *p_dev = p_hwfn->p_dev; 682 enum ecore_eng eng; 683 u8 ppfid; 684 enum _ecore_status_t rc; 685 686 rc = ecore_mcp_get_engine_config(p_hwfn, p_ptt); 687 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) { 688 DP_NOTICE(p_hwfn, false, 689 "Failed to get the engine affinity configuration\n"); 690 return rc; 691 } 692 693 /* RoCE PF is bound to a single engine */ 694 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) { 695 eng = p_dev->fir_affin ? ECORE_ENG1 : ECORE_ENG0; 696 rc = ecore_llh_set_roce_affinity(p_dev, eng); 697 if (rc != ECORE_SUCCESS) { 698 DP_NOTICE(p_dev, false, 699 "Failed to set the RoCE engine affinity\n"); 700 return rc; 701 } 702 703 DP_VERBOSE(p_dev, ECORE_MSG_SP, 704 "LLH: Set the engine affinity of RoCE packets as %d\n", 705 eng); 706 } 707 708 /* Storage PF is bound to a single engine while L2 PF uses both */ 709 if (ECORE_IS_FCOE_PERSONALITY(p_hwfn) || 710 ECORE_IS_ISCSI_PERSONALITY(p_hwfn)) 711 eng = p_dev->fir_affin ? ECORE_ENG1 : ECORE_ENG0; 712 else /* L2_PERSONALITY */ 713 eng = ECORE_BOTH_ENG; 714 715 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) { 716 rc = ecore_llh_set_ppfid_affinity(p_dev, ppfid, eng); 717 if (rc != ECORE_SUCCESS) { 718 DP_NOTICE(p_dev, false, 719 "Failed to set the engine affinity of ppfid %d\n", 720 ppfid); 721 return rc; 722 } 723 } 724 725 DP_VERBOSE(p_dev, ECORE_MSG_SP, 726 "LLH: Set the engine affinity of non-RoCE packets as %d\n", 727 eng); 728 729 return ECORE_SUCCESS; 730 } 731 732 static enum _ecore_status_t 733 ecore_llh_set_engine_affin(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 734 bool avoid_eng_affin) 735 { 736 struct ecore_dev *p_dev = p_hwfn->p_dev; 737 enum _ecore_status_t rc; 738 739 /* Backwards compatible mode: 740 * - RoCE packets - Use engine 0. 741 * - Non-RoCE packets - Use connection based classification for L2 PFs, 742 * and engine 0 otherwise. 743 */ 744 if (avoid_eng_affin) { 745 enum ecore_eng eng; 746 u8 ppfid; 747 748 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) { 749 eng = ECORE_ENG0; 750 rc = ecore_llh_set_roce_affinity(p_dev, eng); 751 if (rc != ECORE_SUCCESS) { 752 DP_NOTICE(p_dev, false, 753 "Failed to set the RoCE engine affinity\n"); 754 return rc; 755 } 756 757 DP_VERBOSE(p_dev, ECORE_MSG_SP, 758 "LLH [backwards compatible mode]: Set the engine affinity of RoCE packets as %d\n", 759 eng); 760 } 761 762 eng = (ECORE_IS_FCOE_PERSONALITY(p_hwfn) || 763 ECORE_IS_ISCSI_PERSONALITY(p_hwfn)) ? ECORE_ENG0 764 : ECORE_BOTH_ENG; 765 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) { 766 rc = ecore_llh_set_ppfid_affinity(p_dev, ppfid, eng); 767 if (rc != ECORE_SUCCESS) { 768 DP_NOTICE(p_dev, false, 769 "Failed to set the engine affinity of ppfid %d\n", 770 ppfid); 771 return rc; 772 } 773 } 774 775 DP_VERBOSE(p_dev, ECORE_MSG_SP, 776 "LLH [backwards compatible mode]: Set the engine affinity of non-RoCE packets as %d\n", 777 eng); 778 779 return ECORE_SUCCESS; 780 } 781 782 return __ecore_llh_set_engine_affin(p_hwfn, p_ptt); 783 } 784 785 static enum _ecore_status_t ecore_llh_hw_init_pf(struct ecore_hwfn *p_hwfn, 786 struct ecore_ptt *p_ptt, 787 bool avoid_eng_affin) 788 { 789 struct ecore_dev *p_dev = p_hwfn->p_dev; 790 u8 ppfid, abs_ppfid; 791 enum _ecore_status_t rc; 792 793 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) { 794 u32 addr; 795 796 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid); 797 if (rc != ECORE_SUCCESS) 798 return rc; 799 800 addr = NIG_REG_LLH_PPFID2PFID_TBL_0 + abs_ppfid * 0x4; 801 ecore_wr(p_hwfn, p_ptt, addr, p_hwfn->rel_pf_id); 802 } 803 804 if (OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) && 805 !ECORE_IS_FCOE_PERSONALITY(p_hwfn)) { 806 rc = ecore_llh_add_mac_filter(p_dev, 0, 807 p_hwfn->hw_info.hw_mac_addr); 808 if (rc != ECORE_SUCCESS) 809 DP_NOTICE(p_dev, false, 810 "Failed to add an LLH filter with the primary MAC\n"); 811 } 812 813 if (ECORE_IS_CMT(p_dev)) { 814 rc = ecore_llh_set_engine_affin(p_hwfn, p_ptt, avoid_eng_affin); 815 if (rc != ECORE_SUCCESS) 816 return rc; 817 } 818 819 return ECORE_SUCCESS; 820 } 821 822 u8 ecore_llh_get_num_ppfid(struct ecore_dev *p_dev) 823 { 824 return p_dev->p_llh_info->num_ppfid; 825 } 826 827 enum ecore_eng ecore_llh_get_l2_affinity_hint(struct ecore_dev *p_dev) 828 { 829 return p_dev->l2_affin_hint ? ECORE_ENG1 : ECORE_ENG0; 830 } 831 832 /* TBD - should be removed when these definitions are available in reg_addr.h */ 833 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_MASK 0x3 834 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_SHIFT 0 835 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_MASK 0x3 836 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_SHIFT 2 837 838 enum _ecore_status_t ecore_llh_set_ppfid_affinity(struct ecore_dev *p_dev, 839 u8 ppfid, enum ecore_eng eng) 840 { 841 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev); 842 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn); 843 u32 addr, val, eng_sel; 844 enum _ecore_status_t rc = ECORE_SUCCESS; 845 u8 abs_ppfid; 846 847 if (p_ptt == OSAL_NULL) 848 return ECORE_AGAIN; 849 850 if (!ECORE_IS_CMT(p_dev)) 851 goto out; 852 853 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid); 854 if (rc != ECORE_SUCCESS) 855 goto out; 856 857 switch (eng) { 858 case ECORE_ENG0: 859 eng_sel = 0; 860 break; 861 case ECORE_ENG1: 862 eng_sel = 1; 863 break; 864 case ECORE_BOTH_ENG: 865 eng_sel = 2; 866 break; 867 default: 868 DP_NOTICE(p_dev, false, 869 "Invalid affinity value for ppfid [%d]\n", eng); 870 rc = ECORE_INVAL; 871 goto out; 872 } 873 874 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4; 875 val = ecore_rd(p_hwfn, p_ptt, addr); 876 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE, eng_sel); 877 ecore_wr(p_hwfn, p_ptt, addr, val); 878 879 /* The iWARP affinity is set as the affinity of ppfid 0 */ 880 if (!ppfid && ECORE_IS_IWARP_PERSONALITY(p_hwfn)) 881 p_dev->iwarp_affin = (eng == ECORE_ENG1) ? 1 : 0; 882 out: 883 ecore_ptt_release(p_hwfn, p_ptt); 884 885 return rc; 886 } 887 888 enum _ecore_status_t ecore_llh_set_roce_affinity(struct ecore_dev *p_dev, 889 enum ecore_eng eng) 890 { 891 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev); 892 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn); 893 u32 addr, val, eng_sel; 894 enum _ecore_status_t rc = ECORE_SUCCESS; 895 u8 ppfid, abs_ppfid; 896 897 if (p_ptt == OSAL_NULL) 898 return ECORE_AGAIN; 899 900 if (!ECORE_IS_CMT(p_dev)) 901 goto out; 902 903 switch (eng) { 904 case ECORE_ENG0: 905 eng_sel = 0; 906 break; 907 case ECORE_ENG1: 908 eng_sel = 1; 909 break; 910 case ECORE_BOTH_ENG: 911 eng_sel = 2; 912 ecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL, 913 0xf /* QP bit 15 */); 914 break; 915 default: 916 DP_NOTICE(p_dev, false, 917 "Invalid affinity value for RoCE [%d]\n", eng); 918 rc = ECORE_INVAL; 919 goto out; 920 } 921 922 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) { 923 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid); 924 if (rc != ECORE_SUCCESS) 925 goto out; 926 927 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4; 928 val = ecore_rd(p_hwfn, p_ptt, addr); 929 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_ROCE, eng_sel); 930 ecore_wr(p_hwfn, p_ptt, addr, val); 931 } 932 out: 933 ecore_ptt_release(p_hwfn, p_ptt); 934 935 return rc; 936 } 937 938 struct ecore_llh_filter_details { 939 u64 value; 940 u32 mode; 941 u32 protocol_type; 942 u32 hdr_sel; 943 u32 enable; 944 }; 945 946 static enum _ecore_status_t 947 ecore_llh_access_filter(struct ecore_hwfn *p_hwfn, 948 struct ecore_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx, 949 struct ecore_llh_filter_details *p_details, 950 bool b_write_access) 951 { 952 u8 pfid = ECORE_PFID_BY_PPFID(p_hwfn, abs_ppfid); 953 struct dmae_params params; 954 enum _ecore_status_t rc; 955 u32 addr; 956 957 /* The NIG/LLH registers that are accessed in this function have only 16 958 * rows which are exposed to a PF. I.e. only the 16 filters of its 959 * default ppfid 960 * Accessing filters of other ppfids requires pretending to other PFs, 961 * and thus the usage of the ecore_ppfid_rd/wr() functions. 962 */ 963 964 /* Filter enable - should be done first when removing a filter */ 965 if (b_write_access && !p_details->enable) { 966 addr = NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + filter_idx * 0x4; 967 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr, 968 p_details->enable); 969 } 970 971 /* Filter value */ 972 addr = NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + 2 * filter_idx * 0x4; 973 OSAL_MEMSET(¶ms, 0, sizeof(params)); 974 975 if (b_write_access) { 976 SET_FIELD(params.flags, DMAE_PARAMS_DST_PF_VALID, 0x1); 977 params.dst_pf_id = pfid; 978 rc = ecore_dmae_host2grc(p_hwfn, p_ptt, 979 (u64)(osal_uintptr_t)&p_details->value, 980 addr, 2 /* size_in_dwords */, ¶ms); 981 } else { 982 SET_FIELD(params.flags, DMAE_PARAMS_SRC_PF_VALID, 0x1); 983 SET_FIELD(params.flags, DMAE_PARAMS_COMPLETION_DST, 0x1); 984 params.src_pf_id = pfid; 985 rc = ecore_dmae_grc2host(p_hwfn, p_ptt, addr, 986 (u64)(osal_uintptr_t)&p_details->value, 987 2 /* size_in_dwords */, ¶ms); 988 } 989 990 if (rc != ECORE_SUCCESS) 991 return rc; 992 993 /* Filter mode */ 994 addr = NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 + filter_idx * 0x4; 995 if (b_write_access) 996 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr, p_details->mode); 997 else 998 p_details->mode = ecore_ppfid_rd(p_hwfn, p_ptt, abs_ppfid, 999 addr); 1000 1001 /* Filter protocol type */ 1002 addr = NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 + filter_idx * 0x4; 1003 if (b_write_access) 1004 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr, 1005 p_details->protocol_type); 1006 else 1007 p_details->protocol_type = ecore_ppfid_rd(p_hwfn, p_ptt, 1008 abs_ppfid, addr); 1009 1010 /* Filter header select */ 1011 addr = NIG_REG_LLH_FUNC_FILTER_HDR_SEL + filter_idx * 0x4; 1012 if (b_write_access) 1013 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr, 1014 p_details->hdr_sel); 1015 else 1016 p_details->hdr_sel = ecore_ppfid_rd(p_hwfn, p_ptt, abs_ppfid, 1017 addr); 1018 1019 /* Filter enable - should be done last when adding a filter */ 1020 if (!b_write_access || p_details->enable) { 1021 addr = NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + filter_idx * 0x4; 1022 if (b_write_access) 1023 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr, 1024 p_details->enable); 1025 else 1026 p_details->enable = ecore_ppfid_rd(p_hwfn, p_ptt, 1027 abs_ppfid, addr); 1028 } 1029 1030 return ECORE_SUCCESS; 1031 } 1032 1033 static enum _ecore_status_t 1034 ecore_llh_add_filter_e4(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 1035 u8 abs_ppfid, u8 filter_idx, u8 filter_prot_type, 1036 u32 high, u32 low) 1037 { 1038 struct ecore_llh_filter_details filter_details; 1039 1040 filter_details.enable = 1; 1041 filter_details.value = ((u64)high << 32) | low; 1042 filter_details.hdr_sel = 1043 OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits) ? 1044 1 : /* inner/encapsulated header */ 1045 0; /* outer/tunnel header */ 1046 filter_details.protocol_type = filter_prot_type; 1047 filter_details.mode = filter_prot_type ? 1048 1 : /* protocol-based classification */ 1049 0; /* MAC-address based classification */ 1050 1051 return ecore_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx, 1052 &filter_details, 1053 true /* write access */); 1054 } 1055 1056 static enum _ecore_status_t 1057 ecore_llh_remove_filter_e4(struct ecore_hwfn *p_hwfn, 1058 struct ecore_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx) 1059 { 1060 struct ecore_llh_filter_details filter_details; 1061 1062 OSAL_MEMSET(&filter_details, 0, sizeof(filter_details)); 1063 1064 return ecore_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx, 1065 &filter_details, 1066 true /* write access */); 1067 } 1068 1069 static enum _ecore_status_t 1070 ecore_llh_add_filter(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 1071 u8 abs_ppfid, u8 filter_idx, u8 filter_prot_type, u32 high, 1072 u32 low) 1073 { 1074 return ecore_llh_add_filter_e4(p_hwfn, p_ptt, abs_ppfid, 1075 filter_idx, filter_prot_type, 1076 high, low); 1077 } 1078 1079 static enum _ecore_status_t 1080 ecore_llh_remove_filter(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 1081 u8 abs_ppfid, u8 filter_idx) 1082 { 1083 return ecore_llh_remove_filter_e4(p_hwfn, p_ptt, abs_ppfid, 1084 filter_idx); 1085 } 1086 1087 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_dev *p_dev, u8 ppfid, 1088 u8 mac_addr[ETH_ALEN]) 1089 { 1090 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev); 1091 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn); 1092 union ecore_llh_filter filter; 1093 u8 filter_idx, abs_ppfid; 1094 u32 high, low, ref_cnt; 1095 enum _ecore_status_t rc = ECORE_SUCCESS; 1096 1097 if (p_ptt == OSAL_NULL) 1098 return ECORE_AGAIN; 1099 1100 if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits)) 1101 goto out; 1102 1103 OSAL_MEM_ZERO(&filter, sizeof(filter)); 1104 OSAL_MEMCPY(filter.mac.addr, mac_addr, ETH_ALEN); 1105 rc = ecore_llh_shadow_add_filter(p_dev, ppfid, 1106 ECORE_LLH_FILTER_TYPE_MAC, 1107 &filter, &filter_idx, &ref_cnt); 1108 if (rc != ECORE_SUCCESS) 1109 goto err; 1110 1111 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid); 1112 if (rc != ECORE_SUCCESS) 1113 goto err; 1114 1115 /* Configure the LLH only in case of a new the filter */ 1116 if (ref_cnt == 1) { 1117 high = mac_addr[1] | (mac_addr[0] << 8); 1118 low = mac_addr[5] | (mac_addr[4] << 8) | (mac_addr[3] << 16) | 1119 (mac_addr[2] << 24); 1120 rc = ecore_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx, 1121 0, high, low); 1122 if (rc != ECORE_SUCCESS) 1123 goto err; 1124 } 1125 1126 DP_VERBOSE(p_dev, ECORE_MSG_SP, 1127 "LLH: Added MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n", 1128 mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3], 1129 mac_addr[4], mac_addr[5], ppfid, abs_ppfid, filter_idx, 1130 ref_cnt); 1131 1132 goto out; 1133 1134 err: 1135 DP_NOTICE(p_dev, false, 1136 "LLH: Failed to add MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] to ppfid %hhd\n", 1137 mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3], 1138 mac_addr[4], mac_addr[5], ppfid); 1139 out: 1140 ecore_ptt_release(p_hwfn, p_ptt); 1141 1142 return rc; 1143 } 1144 1145 static enum _ecore_status_t 1146 ecore_llh_protocol_filter_stringify(struct ecore_dev *p_dev, 1147 enum ecore_llh_prot_filter_type_t type, 1148 u16 source_port_or_eth_type, u16 dest_port, 1149 char *str, osal_size_t str_len) 1150 { 1151 switch (type) { 1152 case ECORE_LLH_FILTER_ETHERTYPE: 1153 OSAL_SNPRINTF(str, str_len, "Ethertype 0x%04x", 1154 source_port_or_eth_type); 1155 break; 1156 case ECORE_LLH_FILTER_TCP_SRC_PORT: 1157 OSAL_SNPRINTF(str, str_len, "TCP src port 0x%04x", 1158 source_port_or_eth_type); 1159 break; 1160 case ECORE_LLH_FILTER_UDP_SRC_PORT: 1161 OSAL_SNPRINTF(str, str_len, "UDP src port 0x%04x", 1162 source_port_or_eth_type); 1163 break; 1164 case ECORE_LLH_FILTER_TCP_DEST_PORT: 1165 OSAL_SNPRINTF(str, str_len, "TCP dst port 0x%04x", dest_port); 1166 break; 1167 case ECORE_LLH_FILTER_UDP_DEST_PORT: 1168 OSAL_SNPRINTF(str, str_len, "UDP dst port 0x%04x", dest_port); 1169 break; 1170 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 1171 OSAL_SNPRINTF(str, str_len, "TCP src/dst ports 0x%04x/0x%04x", 1172 source_port_or_eth_type, dest_port); 1173 break; 1174 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 1175 OSAL_SNPRINTF(str, str_len, "UDP src/dst ports 0x%04x/0x%04x", 1176 source_port_or_eth_type, dest_port); 1177 break; 1178 default: 1179 DP_NOTICE(p_dev, true, 1180 "Non valid LLH protocol filter type %d\n", type); 1181 return ECORE_INVAL; 1182 } 1183 1184 return ECORE_SUCCESS; 1185 } 1186 1187 static enum _ecore_status_t 1188 ecore_llh_protocol_filter_to_hilo(struct ecore_dev *p_dev, 1189 enum ecore_llh_prot_filter_type_t type, 1190 u16 source_port_or_eth_type, u16 dest_port, 1191 u32 *p_high, u32 *p_low) 1192 { 1193 *p_high = 0; 1194 *p_low = 0; 1195 1196 switch (type) { 1197 case ECORE_LLH_FILTER_ETHERTYPE: 1198 *p_high = source_port_or_eth_type; 1199 break; 1200 case ECORE_LLH_FILTER_TCP_SRC_PORT: 1201 case ECORE_LLH_FILTER_UDP_SRC_PORT: 1202 *p_low = source_port_or_eth_type << 16; 1203 break; 1204 case ECORE_LLH_FILTER_TCP_DEST_PORT: 1205 case ECORE_LLH_FILTER_UDP_DEST_PORT: 1206 *p_low = dest_port; 1207 break; 1208 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 1209 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 1210 *p_low = (source_port_or_eth_type << 16) | dest_port; 1211 break; 1212 default: 1213 DP_NOTICE(p_dev, true, 1214 "Non valid LLH protocol filter type %d\n", type); 1215 return ECORE_INVAL; 1216 } 1217 1218 return ECORE_SUCCESS; 1219 } 1220 1221 enum _ecore_status_t 1222 ecore_llh_add_protocol_filter(struct ecore_dev *p_dev, u8 ppfid, 1223 enum ecore_llh_prot_filter_type_t type, 1224 u16 source_port_or_eth_type, u16 dest_port) 1225 { 1226 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev); 1227 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn); 1228 u8 filter_idx, abs_ppfid, type_bitmap; 1229 char str[32]; 1230 union ecore_llh_filter filter; 1231 u32 high, low, ref_cnt; 1232 enum _ecore_status_t rc = ECORE_SUCCESS; 1233 1234 if (p_ptt == OSAL_NULL) 1235 return ECORE_AGAIN; 1236 1237 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits)) 1238 goto out; 1239 1240 rc = ecore_llh_protocol_filter_stringify(p_dev, type, 1241 source_port_or_eth_type, 1242 dest_port, str, sizeof(str)); 1243 if (rc != ECORE_SUCCESS) 1244 goto err; 1245 1246 OSAL_MEM_ZERO(&filter, sizeof(filter)); 1247 filter.protocol.type = type; 1248 filter.protocol.source_port_or_eth_type = source_port_or_eth_type; 1249 filter.protocol.dest_port = dest_port; 1250 rc = ecore_llh_shadow_add_filter(p_dev, ppfid, 1251 ECORE_LLH_FILTER_TYPE_PROTOCOL, 1252 &filter, &filter_idx, &ref_cnt); 1253 if (rc != ECORE_SUCCESS) 1254 goto err; 1255 1256 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid); 1257 if (rc != ECORE_SUCCESS) 1258 goto err; 1259 1260 /* Configure the LLH only in case of a new the filter */ 1261 if (ref_cnt == 1) { 1262 rc = ecore_llh_protocol_filter_to_hilo(p_dev, type, 1263 source_port_or_eth_type, 1264 dest_port, &high, &low); 1265 if (rc != ECORE_SUCCESS) 1266 goto err; 1267 1268 type_bitmap = 0x1 << type; 1269 rc = ecore_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx, 1270 type_bitmap, high, low); 1271 if (rc != ECORE_SUCCESS) 1272 goto err; 1273 } 1274 1275 DP_VERBOSE(p_dev, ECORE_MSG_SP, 1276 "LLH: Added protocol filter [%s] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n", 1277 str, ppfid, abs_ppfid, filter_idx, ref_cnt); 1278 1279 goto out; 1280 1281 err: 1282 DP_NOTICE(p_hwfn, false, 1283 "LLH: Failed to add protocol filter [%s] to ppfid %hhd\n", 1284 str, ppfid); 1285 out: 1286 ecore_ptt_release(p_hwfn, p_ptt); 1287 1288 return rc; 1289 } 1290 1291 void ecore_llh_remove_mac_filter(struct ecore_dev *p_dev, u8 ppfid, 1292 u8 mac_addr[ETH_ALEN]) 1293 { 1294 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev); 1295 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn); 1296 union ecore_llh_filter filter; 1297 u8 filter_idx, abs_ppfid; 1298 enum _ecore_status_t rc = ECORE_SUCCESS; 1299 u32 ref_cnt; 1300 1301 if (p_ptt == OSAL_NULL) 1302 return; 1303 1304 if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits)) 1305 goto out; 1306 1307 OSAL_MEM_ZERO(&filter, sizeof(filter)); 1308 OSAL_MEMCPY(filter.mac.addr, mac_addr, ETH_ALEN); 1309 rc = ecore_llh_shadow_remove_filter(p_dev, ppfid, &filter, &filter_idx, 1310 &ref_cnt); 1311 if (rc != ECORE_SUCCESS) 1312 goto err; 1313 1314 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid); 1315 if (rc != ECORE_SUCCESS) 1316 goto err; 1317 1318 /* Remove from the LLH in case the filter is not in use */ 1319 if (!ref_cnt) { 1320 rc = ecore_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid, 1321 filter_idx); 1322 if (rc != ECORE_SUCCESS) 1323 goto err; 1324 } 1325 1326 DP_VERBOSE(p_dev, ECORE_MSG_SP, 1327 "LLH: Removed MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n", 1328 mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3], 1329 mac_addr[4], mac_addr[5], ppfid, abs_ppfid, filter_idx, 1330 ref_cnt); 1331 1332 goto out; 1333 1334 err: 1335 DP_NOTICE(p_dev, false, 1336 "LLH: Failed to remove MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] from ppfid %hhd\n", 1337 mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3], 1338 mac_addr[4], mac_addr[5], ppfid); 1339 out: 1340 ecore_ptt_release(p_hwfn, p_ptt); 1341 } 1342 1343 void ecore_llh_remove_protocol_filter(struct ecore_dev *p_dev, u8 ppfid, 1344 enum ecore_llh_prot_filter_type_t type, 1345 u16 source_port_or_eth_type, 1346 u16 dest_port) 1347 { 1348 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev); 1349 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn); 1350 u8 filter_idx, abs_ppfid; 1351 char str[32]; 1352 union ecore_llh_filter filter; 1353 enum _ecore_status_t rc = ECORE_SUCCESS; 1354 u32 ref_cnt; 1355 1356 if (p_ptt == OSAL_NULL) 1357 return; 1358 1359 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits)) 1360 goto out; 1361 1362 rc = ecore_llh_protocol_filter_stringify(p_dev, type, 1363 source_port_or_eth_type, 1364 dest_port, str, sizeof(str)); 1365 if (rc != ECORE_SUCCESS) 1366 goto err; 1367 1368 OSAL_MEM_ZERO(&filter, sizeof(filter)); 1369 filter.protocol.type = type; 1370 filter.protocol.source_port_or_eth_type = source_port_or_eth_type; 1371 filter.protocol.dest_port = dest_port; 1372 rc = ecore_llh_shadow_remove_filter(p_dev, ppfid, &filter, &filter_idx, 1373 &ref_cnt); 1374 if (rc != ECORE_SUCCESS) 1375 goto err; 1376 1377 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid); 1378 if (rc != ECORE_SUCCESS) 1379 goto err; 1380 1381 /* Remove from the LLH in case the filter is not in use */ 1382 if (!ref_cnt) { 1383 rc = ecore_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid, 1384 filter_idx); 1385 if (rc != ECORE_SUCCESS) 1386 goto err; 1387 } 1388 1389 DP_VERBOSE(p_dev, ECORE_MSG_SP, 1390 "LLH: Removed protocol filter [%s] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n", 1391 str, ppfid, abs_ppfid, filter_idx, ref_cnt); 1392 1393 goto out; 1394 1395 err: 1396 DP_NOTICE(p_dev, false, 1397 "LLH: Failed to remove protocol filter [%s] from ppfid %hhd\n", 1398 str, ppfid); 1399 out: 1400 ecore_ptt_release(p_hwfn, p_ptt); 1401 } 1402 1403 void ecore_llh_clear_ppfid_filters(struct ecore_dev *p_dev, u8 ppfid) 1404 { 1405 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev); 1406 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn); 1407 u8 filter_idx, abs_ppfid; 1408 enum _ecore_status_t rc = ECORE_SUCCESS; 1409 1410 if (p_ptt == OSAL_NULL) 1411 return; 1412 1413 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) && 1414 !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits)) 1415 goto out; 1416 1417 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid); 1418 if (rc != ECORE_SUCCESS) 1419 goto out; 1420 1421 rc = ecore_llh_shadow_remove_all_filters(p_dev, ppfid); 1422 if (rc != ECORE_SUCCESS) 1423 goto out; 1424 1425 for (filter_idx = 0; filter_idx < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; 1426 filter_idx++) { 1427 rc = ecore_llh_remove_filter_e4(p_hwfn, p_ptt, 1428 abs_ppfid, filter_idx); 1429 if (rc != ECORE_SUCCESS) 1430 goto out; 1431 } 1432 out: 1433 ecore_ptt_release(p_hwfn, p_ptt); 1434 } 1435 1436 void ecore_llh_clear_all_filters(struct ecore_dev *p_dev) 1437 { 1438 u8 ppfid; 1439 1440 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) && 1441 !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits)) 1442 return; 1443 1444 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) 1445 ecore_llh_clear_ppfid_filters(p_dev, ppfid); 1446 } 1447 1448 enum _ecore_status_t ecore_all_ppfids_wr(struct ecore_hwfn *p_hwfn, 1449 struct ecore_ptt *p_ptt, u32 addr, 1450 u32 val) 1451 { 1452 struct ecore_dev *p_dev = p_hwfn->p_dev; 1453 u8 ppfid, abs_ppfid; 1454 enum _ecore_status_t rc; 1455 1456 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) { 1457 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid); 1458 if (rc != ECORE_SUCCESS) 1459 return rc; 1460 1461 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr, val); 1462 } 1463 1464 return ECORE_SUCCESS; 1465 } 1466 1467 static enum _ecore_status_t 1468 ecore_llh_dump_ppfid_e4(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 1469 u8 ppfid) 1470 { 1471 struct ecore_llh_filter_details filter_details; 1472 u8 abs_ppfid, filter_idx; 1473 u32 addr; 1474 enum _ecore_status_t rc; 1475 1476 rc = ecore_abs_ppfid(p_hwfn->p_dev, ppfid, &abs_ppfid); 1477 if (rc != ECORE_SUCCESS) 1478 return rc; 1479 1480 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4; 1481 DP_NOTICE(p_hwfn, false, 1482 "[rel_pf_id %hhd, ppfid={rel %hhd, abs %hhd}, engine_sel 0x%x]\n", 1483 p_hwfn->rel_pf_id, ppfid, abs_ppfid, 1484 ecore_rd(p_hwfn, p_ptt, addr)); 1485 1486 for (filter_idx = 0; filter_idx < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; 1487 filter_idx++) { 1488 OSAL_MEMSET(&filter_details, 0, sizeof(filter_details)); 1489 rc = ecore_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, 1490 filter_idx, &filter_details, 1491 false /* read access */); 1492 if (rc != ECORE_SUCCESS) 1493 return rc; 1494 1495 DP_NOTICE(p_hwfn, false, 1496 "filter %2hhd: enable %d, value 0x%016lx, mode %d, protocol_type 0x%x, hdr_sel 0x%x\n", 1497 filter_idx, filter_details.enable, 1498 (unsigned long)filter_details.value, 1499 filter_details.mode, 1500 filter_details.protocol_type, filter_details.hdr_sel); 1501 } 1502 1503 return ECORE_SUCCESS; 1504 } 1505 1506 enum _ecore_status_t ecore_llh_dump_ppfid(struct ecore_dev *p_dev, u8 ppfid) 1507 { 1508 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev); 1509 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn); 1510 enum _ecore_status_t rc; 1511 1512 if (p_ptt == OSAL_NULL) 1513 return ECORE_AGAIN; 1514 1515 rc = ecore_llh_dump_ppfid_e4(p_hwfn, p_ptt, ppfid); 1516 1517 ecore_ptt_release(p_hwfn, p_ptt); 1518 1519 return rc; 1520 } 1521 1522 enum _ecore_status_t ecore_llh_dump_all(struct ecore_dev *p_dev) 1523 { 1524 u8 ppfid; 1525 enum _ecore_status_t rc; 1526 1527 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) { 1528 rc = ecore_llh_dump_ppfid(p_dev, ppfid); 1529 if (rc != ECORE_SUCCESS) 1530 return rc; 1531 } 1532 1533 return ECORE_SUCCESS; 1534 } 1535 1536 /******************************* NIG LLH - End ********************************/ 1537 1538 /* Configurable */ 1539 #define ECORE_MIN_DPIS (4) /* The minimal num of DPIs required to 1540 * load the driver. The number was 1541 * arbitrarily set. 1542 */ 1543 1544 /* Derived */ 1545 #define ECORE_MIN_PWM_REGION (ECORE_WID_SIZE * ECORE_MIN_DPIS) 1546 1547 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, 1548 struct ecore_ptt *p_ptt, 1549 enum BAR_ID bar_id) 1550 { 1551 u32 bar_reg = (bar_id == BAR_ID_0 ? 1552 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE); 1553 u32 val; 1554 1555 if (IS_VF(p_hwfn->p_dev)) 1556 return ecore_vf_hw_bar_size(p_hwfn, bar_id); 1557 1558 val = ecore_rd(p_hwfn, p_ptt, bar_reg); 1559 if (val) 1560 return 1 << (val + 15); 1561 1562 /* The above registers were updated in the past only in CMT mode. Since 1563 * they were found to be useful MFW started updating them from 8.7.7.0. 1564 * In older MFW versions they are set to 0 which means disabled. 1565 */ 1566 if (ECORE_IS_CMT(p_hwfn->p_dev)) { 1567 DP_INFO(p_hwfn, 1568 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n"); 1569 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024; 1570 } else { 1571 DP_INFO(p_hwfn, 1572 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n"); 1573 val = 512 * 1024; 1574 } 1575 1576 return val; 1577 } 1578 1579 void ecore_init_dp(struct ecore_dev *p_dev, 1580 u32 dp_module, u8 dp_level, void *dp_ctx) 1581 { 1582 u32 i; 1583 1584 p_dev->dp_level = dp_level; 1585 p_dev->dp_module = dp_module; 1586 p_dev->dp_ctx = dp_ctx; 1587 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 1588 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 1589 1590 p_hwfn->dp_level = dp_level; 1591 p_hwfn->dp_module = dp_module; 1592 p_hwfn->dp_ctx = dp_ctx; 1593 } 1594 } 1595 1596 enum _ecore_status_t ecore_init_struct(struct ecore_dev *p_dev) 1597 { 1598 u8 i; 1599 1600 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 1601 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 1602 1603 p_hwfn->p_dev = p_dev; 1604 p_hwfn->my_id = i; 1605 p_hwfn->b_active = false; 1606 1607 #ifdef CONFIG_ECORE_LOCK_ALLOC 1608 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->dmae_info.lock)) 1609 goto handle_err; 1610 #endif 1611 OSAL_SPIN_LOCK_INIT(&p_hwfn->dmae_info.lock); 1612 } 1613 1614 /* hwfn 0 is always active */ 1615 p_dev->hwfns[0].b_active = true; 1616 1617 /* set the default cache alignment to 128 (may be overridden later) */ 1618 p_dev->cache_shift = 7; 1619 return ECORE_SUCCESS; 1620 #ifdef CONFIG_ECORE_LOCK_ALLOC 1621 handle_err: 1622 while (--i) { 1623 struct ecore_hwfn *p_hwfn = OSAL_NULL; 1624 1625 p_hwfn = &p_dev->hwfns[i]; 1626 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock); 1627 } 1628 return ECORE_NOMEM; 1629 #endif 1630 } 1631 1632 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn) 1633 { 1634 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 1635 1636 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params); 1637 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params); 1638 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params); 1639 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data); 1640 } 1641 1642 static void ecore_dbg_user_data_free(struct ecore_hwfn *p_hwfn) 1643 { 1644 OSAL_FREE(p_hwfn->p_dev, p_hwfn->dbg_user_info); 1645 p_hwfn->dbg_user_info = OSAL_NULL; 1646 } 1647 1648 void ecore_resc_free(struct ecore_dev *p_dev) 1649 { 1650 int i; 1651 1652 if (IS_VF(p_dev)) { 1653 for_each_hwfn(p_dev, i) 1654 ecore_l2_free(&p_dev->hwfns[i]); 1655 return; 1656 } 1657 1658 OSAL_FREE(p_dev, p_dev->fw_data); 1659 1660 OSAL_FREE(p_dev, p_dev->reset_stats); 1661 1662 ecore_llh_free(p_dev); 1663 1664 for_each_hwfn(p_dev, i) { 1665 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 1666 1667 ecore_cxt_mngr_free(p_hwfn); 1668 ecore_qm_info_free(p_hwfn); 1669 ecore_spq_free(p_hwfn); 1670 ecore_eq_free(p_hwfn); 1671 ecore_consq_free(p_hwfn); 1672 ecore_int_free(p_hwfn); 1673 ecore_iov_free(p_hwfn); 1674 ecore_l2_free(p_hwfn); 1675 ecore_dmae_info_free(p_hwfn); 1676 ecore_dcbx_info_free(p_hwfn); 1677 ecore_dbg_user_data_free(p_hwfn); 1678 /* @@@TBD Flush work-queue ? */ 1679 1680 /* destroy doorbell recovery mechanism */ 1681 ecore_db_recovery_teardown(p_hwfn); 1682 } 1683 } 1684 1685 /******************** QM initialization *******************/ 1686 1687 /* bitmaps for indicating active traffic classes. 1688 * Special case for Arrowhead 4 port 1689 */ 1690 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */ 1691 #define ACTIVE_TCS_BMAP 0x9f 1692 /* 0..3 actually used, OOO and high priority stuff all use 3 */ 1693 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf 1694 1695 /* determines the physical queue flags for a given PF. */ 1696 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn) 1697 { 1698 u32 flags; 1699 1700 /* common flags */ 1701 flags = PQ_FLAGS_LB; 1702 1703 /* feature flags */ 1704 if (IS_ECORE_SRIOV(p_hwfn->p_dev)) 1705 flags |= PQ_FLAGS_VFS; 1706 if (IS_ECORE_PACING(p_hwfn)) 1707 flags |= PQ_FLAGS_RLS; 1708 1709 /* protocol flags */ 1710 switch (p_hwfn->hw_info.personality) { 1711 case ECORE_PCI_ETH: 1712 if (!IS_ECORE_PACING(p_hwfn)) 1713 flags |= PQ_FLAGS_MCOS; 1714 break; 1715 case ECORE_PCI_FCOE: 1716 flags |= PQ_FLAGS_OFLD; 1717 break; 1718 case ECORE_PCI_ISCSI: 1719 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD; 1720 break; 1721 case ECORE_PCI_ETH_ROCE: 1722 flags |= PQ_FLAGS_OFLD | PQ_FLAGS_LLT; 1723 if (!IS_ECORE_PACING(p_hwfn)) 1724 flags |= PQ_FLAGS_MCOS; 1725 break; 1726 case ECORE_PCI_ETH_IWARP: 1727 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD; 1728 if (!IS_ECORE_PACING(p_hwfn)) 1729 flags |= PQ_FLAGS_MCOS; 1730 break; 1731 default: 1732 DP_ERR(p_hwfn, "unknown personality %d\n", 1733 p_hwfn->hw_info.personality); 1734 return 0; 1735 } 1736 return flags; 1737 } 1738 1739 /* Getters for resource amounts necessary for qm initialization */ 1740 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn) 1741 { 1742 return p_hwfn->hw_info.num_hw_tc; 1743 } 1744 1745 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn) 1746 { 1747 return IS_ECORE_SRIOV(p_hwfn->p_dev) ? 1748 p_hwfn->p_dev->p_iov_info->total_vfs : 0; 1749 } 1750 1751 #define NUM_DEFAULT_RLS 1 1752 1753 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn) 1754 { 1755 u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn); 1756 1757 /* num RLs can't exceed resource amount of rls or vports or the 1758 * dcqcn qps 1759 */ 1760 num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL), 1761 RESC_NUM(p_hwfn, ECORE_VPORT)); 1762 1763 /* make sure after we reserve the default and VF rls we'll have 1764 * something left 1765 */ 1766 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) { 1767 DP_NOTICE(p_hwfn, false, 1768 "no rate limiters left for PF rate limiting" 1769 " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs); 1770 return 0; 1771 } 1772 1773 /* subtract rls necessary for VFs and one default one for the PF */ 1774 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS; 1775 1776 return num_pf_rls; 1777 } 1778 1779 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn) 1780 { 1781 u32 pq_flags = ecore_get_pq_flags(p_hwfn); 1782 1783 /* all pqs share the same vport (hence the 1 below), except for vfs 1784 * and pf_rl pqs 1785 */ 1786 return (!!(PQ_FLAGS_RLS & pq_flags)) * 1787 ecore_init_qm_get_num_pf_rls(p_hwfn) + 1788 (!!(PQ_FLAGS_VFS & pq_flags)) * 1789 ecore_init_qm_get_num_vfs(p_hwfn) + 1; 1790 } 1791 1792 /* calc amount of PQs according to the requested flags */ 1793 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn) 1794 { 1795 u32 pq_flags = ecore_get_pq_flags(p_hwfn); 1796 1797 return (!!(PQ_FLAGS_RLS & pq_flags)) * 1798 ecore_init_qm_get_num_pf_rls(p_hwfn) + 1799 (!!(PQ_FLAGS_MCOS & pq_flags)) * 1800 ecore_init_qm_get_num_tcs(p_hwfn) + 1801 (!!(PQ_FLAGS_LB & pq_flags)) + 1802 (!!(PQ_FLAGS_OOO & pq_flags)) + 1803 (!!(PQ_FLAGS_ACK & pq_flags)) + 1804 (!!(PQ_FLAGS_OFLD & pq_flags)) + 1805 (!!(PQ_FLAGS_VFS & pq_flags)) * 1806 ecore_init_qm_get_num_vfs(p_hwfn); 1807 } 1808 1809 /* initialize the top level QM params */ 1810 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn) 1811 { 1812 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 1813 bool four_port; 1814 1815 /* pq and vport bases for this PF */ 1816 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ); 1817 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT); 1818 1819 /* rate limiting and weighted fair queueing are always enabled */ 1820 qm_info->vport_rl_en = 1; 1821 qm_info->vport_wfq_en = 1; 1822 1823 /* TC config is different for AH 4 port */ 1824 four_port = p_hwfn->p_dev->num_ports_in_engine == MAX_NUM_PORTS_K2; 1825 1826 /* in AH 4 port we have fewer TCs per port */ 1827 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 : 1828 NUM_OF_PHYS_TCS; 1829 1830 /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and 1831 * 4 otherwise 1832 */ 1833 if (!qm_info->ooo_tc) 1834 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC : 1835 DCBX_TCP_OOO_TC; 1836 } 1837 1838 /* initialize qm vport params */ 1839 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn) 1840 { 1841 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 1842 u8 i; 1843 1844 /* all vports participate in weighted fair queueing */ 1845 for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++) 1846 qm_info->qm_vport_params[i].wfq = 1; 1847 } 1848 1849 /* initialize qm port params */ 1850 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn) 1851 { 1852 /* Initialize qm port parameters */ 1853 u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engine; 1854 1855 /* indicate how ooo and high pri traffic is dealt with */ 1856 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ? 1857 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP; 1858 1859 for (i = 0; i < num_ports; i++) { 1860 struct init_qm_port_params *p_qm_port = 1861 &p_hwfn->qm_info.qm_port_params[i]; 1862 1863 p_qm_port->active = 1; 1864 p_qm_port->active_phys_tcs = active_phys_tcs; 1865 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports; 1866 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports; 1867 } 1868 } 1869 1870 /* Reset the params which must be reset for qm init. QM init may be called as 1871 * a result of flows other than driver load (e.g. dcbx renegotiation). Other 1872 * params may be affected by the init but would simply recalculate to the same 1873 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not 1874 * affected as these amounts stay the same. 1875 */ 1876 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn) 1877 { 1878 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 1879 1880 qm_info->num_pqs = 0; 1881 qm_info->num_vports = 0; 1882 qm_info->num_pf_rls = 0; 1883 qm_info->num_vf_pqs = 0; 1884 qm_info->first_vf_pq = 0; 1885 qm_info->first_mcos_pq = 0; 1886 qm_info->first_rl_pq = 0; 1887 } 1888 1889 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn) 1890 { 1891 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 1892 1893 qm_info->num_vports++; 1894 1895 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn)) 1896 DP_ERR(p_hwfn, 1897 "vport overflow! qm_info->num_vports %d," 1898 " qm_init_get_num_vports() %d\n", 1899 qm_info->num_vports, 1900 ecore_init_qm_get_num_vports(p_hwfn)); 1901 } 1902 1903 /* initialize a single pq and manage qm_info resources accounting. 1904 * The pq_init_flags param determines whether the PQ is rate limited 1905 * (for VF or PF) 1906 * and whether a new vport is allocated to the pq or not (i.e. vport will be 1907 * shared) 1908 */ 1909 1910 /* flags for pq init */ 1911 #define PQ_INIT_SHARE_VPORT (1 << 0) 1912 #define PQ_INIT_PF_RL (1 << 1) 1913 #define PQ_INIT_VF_RL (1 << 2) 1914 1915 /* defines for pq init */ 1916 #define PQ_INIT_DEFAULT_WRR_GROUP 1 1917 #define PQ_INIT_DEFAULT_TC 0 1918 #define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc) 1919 1920 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn, 1921 struct ecore_qm_info *qm_info, 1922 u8 tc, u32 pq_init_flags) 1923 { 1924 u16 pq_idx = qm_info->num_pqs, max_pq = 1925 ecore_init_qm_get_num_pqs(p_hwfn); 1926 1927 if (pq_idx > max_pq) 1928 DP_ERR(p_hwfn, 1929 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq); 1930 1931 /* init pq params */ 1932 qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id; 1933 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport + 1934 qm_info->num_vports; 1935 qm_info->qm_pq_params[pq_idx].tc_id = tc; 1936 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP; 1937 qm_info->qm_pq_params[pq_idx].rl_valid = 1938 (pq_init_flags & PQ_INIT_PF_RL || 1939 pq_init_flags & PQ_INIT_VF_RL); 1940 1941 /* qm params accounting */ 1942 qm_info->num_pqs++; 1943 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT)) 1944 qm_info->num_vports++; 1945 1946 if (pq_init_flags & PQ_INIT_PF_RL) 1947 qm_info->num_pf_rls++; 1948 1949 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn)) 1950 DP_ERR(p_hwfn, 1951 "vport overflow! qm_info->num_vports %d," 1952 " qm_init_get_num_vports() %d\n", 1953 qm_info->num_vports, 1954 ecore_init_qm_get_num_vports(p_hwfn)); 1955 1956 if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn)) 1957 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d," 1958 " qm_init_get_num_pf_rls() %d\n", 1959 qm_info->num_pf_rls, 1960 ecore_init_qm_get_num_pf_rls(p_hwfn)); 1961 } 1962 1963 /* get pq index according to PQ_FLAGS */ 1964 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn, 1965 u32 pq_flags) 1966 { 1967 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 1968 1969 /* Can't have multiple flags set here */ 1970 if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags, 1971 sizeof(pq_flags)) > 1) 1972 goto err; 1973 1974 switch (pq_flags) { 1975 case PQ_FLAGS_RLS: 1976 return &qm_info->first_rl_pq; 1977 case PQ_FLAGS_MCOS: 1978 return &qm_info->first_mcos_pq; 1979 case PQ_FLAGS_LB: 1980 return &qm_info->pure_lb_pq; 1981 case PQ_FLAGS_OOO: 1982 return &qm_info->ooo_pq; 1983 case PQ_FLAGS_ACK: 1984 return &qm_info->pure_ack_pq; 1985 case PQ_FLAGS_OFLD: 1986 return &qm_info->offload_pq; 1987 case PQ_FLAGS_VFS: 1988 return &qm_info->first_vf_pq; 1989 default: 1990 goto err; 1991 } 1992 1993 err: 1994 DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags); 1995 return OSAL_NULL; 1996 } 1997 1998 /* save pq index in qm info */ 1999 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn, 2000 u32 pq_flags, u16 pq_val) 2001 { 2002 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags); 2003 2004 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val; 2005 } 2006 2007 /* get tx pq index, with the PQ TX base already set (ready for context init) */ 2008 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags) 2009 { 2010 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags); 2011 2012 return *base_pq_idx + CM_TX_PQ_BASE; 2013 } 2014 2015 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc) 2016 { 2017 u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn); 2018 2019 if (tc > max_tc) 2020 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc); 2021 2022 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc); 2023 } 2024 2025 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf) 2026 { 2027 u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn); 2028 2029 if (vf > max_vf) 2030 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf); 2031 2032 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf); 2033 } 2034 2035 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl) 2036 { 2037 u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn); 2038 2039 /* for rate limiters, it is okay to use the modulo behavior - no 2040 * DP_ERR 2041 */ 2042 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + (rl % max_rl); 2043 } 2044 2045 u16 ecore_get_qm_vport_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl) 2046 { 2047 u16 start_pq, pq, qm_pq_idx; 2048 2049 pq = ecore_get_cm_pq_idx_rl(p_hwfn, rl); 2050 start_pq = p_hwfn->qm_info.start_pq; 2051 qm_pq_idx = pq - start_pq - CM_TX_PQ_BASE; 2052 2053 if (qm_pq_idx > p_hwfn->qm_info.num_pqs) { 2054 DP_ERR(p_hwfn, 2055 "qm_pq_idx %d must be smaller than %d\n", 2056 qm_pq_idx, p_hwfn->qm_info.num_pqs); 2057 } 2058 2059 return p_hwfn->qm_info.qm_pq_params[qm_pq_idx].vport_id; 2060 } 2061 2062 /* Functions for creating specific types of pqs */ 2063 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn) 2064 { 2065 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 2066 2067 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB)) 2068 return; 2069 2070 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs); 2071 ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT); 2072 } 2073 2074 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn) 2075 { 2076 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 2077 2078 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO)) 2079 return; 2080 2081 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs); 2082 ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT); 2083 } 2084 2085 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn) 2086 { 2087 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 2088 2089 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK)) 2090 return; 2091 2092 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs); 2093 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT); 2094 } 2095 2096 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn) 2097 { 2098 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 2099 2100 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD)) 2101 return; 2102 2103 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs); 2104 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT); 2105 } 2106 2107 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn) 2108 { 2109 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 2110 u8 tc_idx; 2111 2112 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS)) 2113 return; 2114 2115 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs); 2116 for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++) 2117 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT); 2118 } 2119 2120 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn) 2121 { 2122 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 2123 u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn); 2124 2125 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS)) 2126 return; 2127 2128 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs); 2129 2130 qm_info->num_vf_pqs = num_vfs; 2131 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++) 2132 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC, 2133 PQ_INIT_VF_RL); 2134 } 2135 2136 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn) 2137 { 2138 u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn); 2139 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 2140 2141 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS)) 2142 return; 2143 2144 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs); 2145 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++) 2146 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, 2147 PQ_INIT_PF_RL); 2148 } 2149 2150 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn) 2151 { 2152 /* rate limited pqs, must come first (FW assumption) */ 2153 ecore_init_qm_rl_pqs(p_hwfn); 2154 2155 /* pqs for multi cos */ 2156 ecore_init_qm_mcos_pqs(p_hwfn); 2157 2158 /* pure loopback pq */ 2159 ecore_init_qm_lb_pq(p_hwfn); 2160 2161 /* out of order pq */ 2162 ecore_init_qm_ooo_pq(p_hwfn); 2163 2164 /* pure ack pq */ 2165 ecore_init_qm_pure_ack_pq(p_hwfn); 2166 2167 /* pq for offloaded protocol */ 2168 ecore_init_qm_offload_pq(p_hwfn); 2169 2170 /* done sharing vports */ 2171 ecore_init_qm_advance_vport(p_hwfn); 2172 2173 /* pqs for vfs */ 2174 ecore_init_qm_vf_pqs(p_hwfn); 2175 } 2176 2177 /* compare values of getters against resources amounts */ 2178 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn) 2179 { 2180 if (ecore_init_qm_get_num_vports(p_hwfn) > 2181 RESC_NUM(p_hwfn, ECORE_VPORT)) { 2182 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n"); 2183 return ECORE_INVAL; 2184 } 2185 2186 if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) { 2187 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n"); 2188 return ECORE_INVAL; 2189 } 2190 2191 return ECORE_SUCCESS; 2192 } 2193 2194 /* 2195 * Function for verbose printing of the qm initialization results 2196 */ 2197 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn) 2198 { 2199 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 2200 struct init_qm_vport_params *vport; 2201 struct init_qm_port_params *port; 2202 struct init_qm_pq_params *pq; 2203 int i, tc; 2204 2205 /* top level params */ 2206 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 2207 "qm init top level params: start_pq %d, start_vport %d," 2208 " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n", 2209 qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq, 2210 qm_info->offload_pq, qm_info->pure_ack_pq); 2211 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 2212 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d," 2213 " num_vports %d, max_phys_tcs_per_port %d\n", 2214 qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs, 2215 qm_info->num_vf_pqs, qm_info->num_vports, 2216 qm_info->max_phys_tcs_per_port); 2217 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 2218 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d," 2219 " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n", 2220 qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en, 2221 qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl, 2222 qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn)); 2223 2224 /* port table */ 2225 for (i = 0; i < p_hwfn->p_dev->num_ports_in_engine; i++) { 2226 port = &qm_info->qm_port_params[i]; 2227 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 2228 "port idx %d, active %d, active_phys_tcs %d," 2229 " num_pbf_cmd_lines %d, num_btb_blocks %d," 2230 " reserved %d\n", 2231 i, port->active, port->active_phys_tcs, 2232 port->num_pbf_cmd_lines, port->num_btb_blocks, 2233 port->reserved); 2234 } 2235 2236 /* vport table */ 2237 for (i = 0; i < qm_info->num_vports; i++) { 2238 vport = &qm_info->qm_vport_params[i]; 2239 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "vport idx %d, wfq %d, first_tx_pq_id [ ", 2240 qm_info->start_vport + i, vport->wfq); 2241 for (tc = 0; tc < NUM_OF_TCS; tc++) 2242 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ", 2243 vport->first_tx_pq_id[tc]); 2244 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n"); 2245 } 2246 2247 /* pq table */ 2248 for (i = 0; i < qm_info->num_pqs; i++) { 2249 pq = &qm_info->qm_pq_params[i]; 2250 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 2251 "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n", 2252 qm_info->start_pq + i, pq->port_id, pq->vport_id, 2253 pq->tc_id, pq->wrr_group, pq->rl_valid); 2254 } 2255 } 2256 2257 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn) 2258 { 2259 /* reset params required for init run */ 2260 ecore_init_qm_reset_params(p_hwfn); 2261 2262 /* init QM top level params */ 2263 ecore_init_qm_params(p_hwfn); 2264 2265 /* init QM port params */ 2266 ecore_init_qm_port_params(p_hwfn); 2267 2268 /* init QM vport params */ 2269 ecore_init_qm_vport_params(p_hwfn); 2270 2271 /* init QM physical queue params */ 2272 ecore_init_qm_pq_params(p_hwfn); 2273 2274 /* display all that init */ 2275 ecore_dp_init_qm_params(p_hwfn); 2276 } 2277 2278 /* This function reconfigures the QM pf on the fly. 2279 * For this purpose we: 2280 * 1. reconfigure the QM database 2281 * 2. set new values to runtime array 2282 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM 2283 * 4. activate init tool in QM_PF stage 2284 * 5. send an sdm_qm_cmd through rbc interface to release the QM 2285 */ 2286 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn, 2287 struct ecore_ptt *p_ptt) 2288 { 2289 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 2290 bool b_rc; 2291 enum _ecore_status_t rc = ECORE_SUCCESS; 2292 2293 /* multiple flows can issue qm reconf. Need to lock */ 2294 OSAL_SPIN_LOCK(&qm_lock); 2295 2296 /* initialize ecore's qm data structure */ 2297 ecore_init_qm_info(p_hwfn); 2298 2299 /* stop PF's qm queues */ 2300 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true, 2301 qm_info->start_pq, qm_info->num_pqs); 2302 if (!b_rc) { 2303 rc = ECORE_INVAL; 2304 goto unlock; 2305 } 2306 2307 /* clear the QM_PF runtime phase leftovers from previous init */ 2308 ecore_init_clear_rt_data(p_hwfn); 2309 2310 /* prepare QM portion of runtime array */ 2311 ecore_qm_init_pf(p_hwfn, p_ptt, false); 2312 2313 /* activate init tool on runtime array */ 2314 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id, 2315 p_hwfn->hw_info.hw_mode); 2316 2317 /* start PF's qm queues */ 2318 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true, 2319 qm_info->start_pq, qm_info->num_pqs); 2320 if (!b_rc) 2321 rc = ECORE_INVAL; 2322 2323 unlock: 2324 OSAL_SPIN_UNLOCK(&qm_lock); 2325 2326 return rc; 2327 } 2328 2329 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn) 2330 { 2331 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 2332 enum _ecore_status_t rc; 2333 2334 rc = ecore_init_qm_sanity(p_hwfn); 2335 if (rc != ECORE_SUCCESS) 2336 goto alloc_err; 2337 2338 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, 2339 sizeof(struct init_qm_pq_params) * 2340 ecore_init_qm_get_num_pqs(p_hwfn)); 2341 if (!qm_info->qm_pq_params) 2342 goto alloc_err; 2343 2344 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, 2345 sizeof(struct init_qm_vport_params) * 2346 ecore_init_qm_get_num_vports(p_hwfn)); 2347 if (!qm_info->qm_vport_params) 2348 goto alloc_err; 2349 2350 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, 2351 sizeof(struct init_qm_port_params) * 2352 p_hwfn->p_dev->num_ports_in_engine); 2353 if (!qm_info->qm_port_params) 2354 goto alloc_err; 2355 2356 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, 2357 sizeof(struct ecore_wfq_data) * 2358 ecore_init_qm_get_num_vports(p_hwfn)); 2359 if (!qm_info->wfq_data) 2360 goto alloc_err; 2361 2362 return ECORE_SUCCESS; 2363 2364 alloc_err: 2365 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n"); 2366 ecore_qm_info_free(p_hwfn); 2367 return ECORE_NOMEM; 2368 } 2369 /******************** End QM initialization ***************/ 2370 2371 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev) 2372 { 2373 enum _ecore_status_t rc = ECORE_SUCCESS; 2374 int i; 2375 2376 if (IS_VF(p_dev)) { 2377 for_each_hwfn(p_dev, i) { 2378 rc = ecore_l2_alloc(&p_dev->hwfns[i]); 2379 if (rc != ECORE_SUCCESS) 2380 return rc; 2381 } 2382 return rc; 2383 } 2384 2385 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL, 2386 sizeof(*p_dev->fw_data)); 2387 if (!p_dev->fw_data) 2388 return ECORE_NOMEM; 2389 2390 for_each_hwfn(p_dev, i) { 2391 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 2392 u32 n_eqes, num_cons; 2393 2394 /* initialize the doorbell recovery mechanism */ 2395 rc = ecore_db_recovery_setup(p_hwfn); 2396 if (rc) 2397 goto alloc_err; 2398 2399 /* First allocate the context manager structure */ 2400 rc = ecore_cxt_mngr_alloc(p_hwfn); 2401 if (rc) 2402 goto alloc_err; 2403 2404 /* Set the HW cid/tid numbers (in the context manager) 2405 * Must be done prior to any further computations. 2406 */ 2407 rc = ecore_cxt_set_pf_params(p_hwfn); 2408 if (rc) 2409 goto alloc_err; 2410 2411 rc = ecore_alloc_qm_data(p_hwfn); 2412 if (rc) 2413 goto alloc_err; 2414 2415 /* init qm info */ 2416 ecore_init_qm_info(p_hwfn); 2417 2418 /* Compute the ILT client partition */ 2419 rc = ecore_cxt_cfg_ilt_compute(p_hwfn); 2420 if (rc) 2421 goto alloc_err; 2422 2423 /* CID map / ILT shadow table / T2 2424 * The talbes sizes are determined by the computations above 2425 */ 2426 rc = ecore_cxt_tables_alloc(p_hwfn); 2427 if (rc) 2428 goto alloc_err; 2429 2430 /* SPQ, must follow ILT because initializes SPQ context */ 2431 rc = ecore_spq_alloc(p_hwfn); 2432 if (rc) 2433 goto alloc_err; 2434 2435 /* SP status block allocation */ 2436 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn, 2437 RESERVED_PTT_DPC); 2438 2439 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt); 2440 if (rc) 2441 goto alloc_err; 2442 2443 rc = ecore_iov_alloc(p_hwfn); 2444 if (rc) 2445 goto alloc_err; 2446 2447 /* EQ */ 2448 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain); 2449 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) { 2450 /* Calculate the EQ size 2451 * --------------------- 2452 * Each ICID may generate up to one event at a time i.e. 2453 * the event must be handled/cleared before a new one 2454 * can be generated. We calculate the sum of events per 2455 * protocol and create an EQ deep enough to handle the 2456 * worst case: 2457 * - Core - according to SPQ. 2458 * - RoCE - per QP there are a couple of ICIDs, one 2459 * responder and one requester, each can 2460 * generate an EQE => n_eqes_qp = 2 * n_qp. 2461 * Each CQ can generate an EQE. There are 2 CQs 2462 * per QP => n_eqes_cq = 2 * n_qp. 2463 * Hence the RoCE total is 4 * n_qp or 2464 * 2 * num_cons. 2465 * - ENet - There can be up to two events per VF. One 2466 * for VF-PF channel and another for VF FLR 2467 * initial cleanup. The number of VFs is 2468 * bounded by MAX_NUM_VFS_BB, and is much 2469 * smaller than RoCE's so we avoid exact 2470 * calculation. 2471 */ 2472 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) { 2473 num_cons = 2474 ecore_cxt_get_proto_cid_count( 2475 p_hwfn, 2476 PROTOCOLID_ROCE, 2477 OSAL_NULL); 2478 num_cons *= 2; 2479 } else { 2480 num_cons = ecore_cxt_get_proto_cid_count( 2481 p_hwfn, 2482 PROTOCOLID_IWARP, 2483 OSAL_NULL); 2484 } 2485 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB; 2486 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) { 2487 num_cons = 2488 ecore_cxt_get_proto_cid_count(p_hwfn, 2489 PROTOCOLID_ISCSI, 2490 OSAL_NULL); 2491 n_eqes += 2 * num_cons; 2492 } 2493 2494 if (n_eqes > 0xFFFF) { 2495 DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements." 2496 "The maximum of a u16 chain is 0x%x\n", 2497 n_eqes, 0xFFFF); 2498 goto alloc_no_mem; 2499 } 2500 2501 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes); 2502 if (rc) 2503 goto alloc_err; 2504 2505 rc = ecore_consq_alloc(p_hwfn); 2506 if (rc) 2507 goto alloc_err; 2508 2509 rc = ecore_l2_alloc(p_hwfn); 2510 if (rc != ECORE_SUCCESS) 2511 goto alloc_err; 2512 2513 /* DMA info initialization */ 2514 rc = ecore_dmae_info_alloc(p_hwfn); 2515 if (rc) { 2516 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for dmae_info structure\n"); 2517 goto alloc_err; 2518 } 2519 2520 /* DCBX initialization */ 2521 rc = ecore_dcbx_info_alloc(p_hwfn); 2522 if (rc) { 2523 DP_NOTICE(p_hwfn, false, 2524 "Failed to allocate memory for dcbx structure\n"); 2525 goto alloc_err; 2526 } 2527 2528 rc = OSAL_DBG_ALLOC_USER_DATA(p_hwfn, &p_hwfn->dbg_user_info); 2529 if (rc) { 2530 DP_NOTICE(p_hwfn, false, 2531 "Failed to allocate dbg user info structure\n"); 2532 goto alloc_err; 2533 } 2534 } /* hwfn loop */ 2535 2536 rc = ecore_llh_alloc(p_dev); 2537 if (rc != ECORE_SUCCESS) { 2538 DP_NOTICE(p_dev, true, 2539 "Failed to allocate memory for the llh_info structure\n"); 2540 goto alloc_err; 2541 } 2542 2543 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL, 2544 sizeof(*p_dev->reset_stats)); 2545 if (!p_dev->reset_stats) { 2546 DP_NOTICE(p_dev, false, "Failed to allocate reset statistics\n"); 2547 goto alloc_no_mem; 2548 } 2549 2550 return ECORE_SUCCESS; 2551 2552 alloc_no_mem: 2553 rc = ECORE_NOMEM; 2554 alloc_err: 2555 ecore_resc_free(p_dev); 2556 return rc; 2557 } 2558 2559 void ecore_resc_setup(struct ecore_dev *p_dev) 2560 { 2561 int i; 2562 2563 if (IS_VF(p_dev)) { 2564 for_each_hwfn(p_dev, i) 2565 ecore_l2_setup(&p_dev->hwfns[i]); 2566 return; 2567 } 2568 2569 for_each_hwfn(p_dev, i) { 2570 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 2571 2572 ecore_cxt_mngr_setup(p_hwfn); 2573 ecore_spq_setup(p_hwfn); 2574 ecore_eq_setup(p_hwfn); 2575 ecore_consq_setup(p_hwfn); 2576 2577 /* Read shadow of current MFW mailbox */ 2578 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt); 2579 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow, 2580 p_hwfn->mcp_info->mfw_mb_cur, 2581 p_hwfn->mcp_info->mfw_mb_length); 2582 2583 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt); 2584 2585 ecore_l2_setup(p_hwfn); 2586 ecore_iov_setup(p_hwfn); 2587 } 2588 } 2589 2590 #define FINAL_CLEANUP_POLL_CNT (100) 2591 #define FINAL_CLEANUP_POLL_TIME (10) 2592 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn, 2593 struct ecore_ptt *p_ptt, 2594 u16 id, bool is_vf) 2595 { 2596 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT; 2597 enum _ecore_status_t rc = ECORE_TIMEOUT; 2598 2599 #ifndef ASIC_ONLY 2600 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) || 2601 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { 2602 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n"); 2603 return ECORE_SUCCESS; 2604 } 2605 #endif 2606 2607 addr = GTT_BAR0_MAP_REG_USDM_RAM + 2608 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id); 2609 2610 if (is_vf) 2611 id += 0x10; 2612 2613 command |= X_FINAL_CLEANUP_AGG_INT << 2614 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT; 2615 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT; 2616 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT; 2617 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT; 2618 2619 /* Make sure notification is not set before initiating final cleanup */ 2620 2621 if (REG_RD(p_hwfn, addr)) { 2622 DP_NOTICE(p_hwfn, false, 2623 "Unexpected; Found final cleanup notification"); 2624 DP_NOTICE(p_hwfn, false, 2625 " before initiating final cleanup\n"); 2626 REG_WR(p_hwfn, addr, 0); 2627 } 2628 2629 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV, 2630 "Sending final cleanup for PFVF[%d] [Command %08x]\n", 2631 id, command); 2632 2633 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command); 2634 2635 /* Poll until completion */ 2636 while (!REG_RD(p_hwfn, addr) && count--) 2637 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME); 2638 2639 if (REG_RD(p_hwfn, addr)) 2640 rc = ECORE_SUCCESS; 2641 else 2642 DP_NOTICE(p_hwfn, true, 2643 "Failed to receive FW final cleanup notification\n"); 2644 2645 /* Cleanup afterwards */ 2646 REG_WR(p_hwfn, addr, 0); 2647 2648 return rc; 2649 } 2650 2651 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn) 2652 { 2653 int hw_mode = 0; 2654 2655 if (ECORE_IS_BB_B0(p_hwfn->p_dev)) { 2656 hw_mode |= 1 << MODE_BB; 2657 } else if (ECORE_IS_AH(p_hwfn->p_dev)) { 2658 hw_mode |= 1 << MODE_K2; 2659 } else { 2660 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n", 2661 p_hwfn->p_dev->type); 2662 return ECORE_INVAL; 2663 } 2664 2665 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */ 2666 switch (p_hwfn->p_dev->num_ports_in_engine) { 2667 case 1: 2668 hw_mode |= 1 << MODE_PORTS_PER_ENG_1; 2669 break; 2670 case 2: 2671 hw_mode |= 1 << MODE_PORTS_PER_ENG_2; 2672 break; 2673 case 4: 2674 hw_mode |= 1 << MODE_PORTS_PER_ENG_4; 2675 break; 2676 default: 2677 DP_NOTICE(p_hwfn, true, 2678 "num_ports_in_engine = %d not supported\n", 2679 p_hwfn->p_dev->num_ports_in_engine); 2680 return ECORE_INVAL; 2681 } 2682 2683 if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits)) 2684 hw_mode |= 1 << MODE_MF_SD; 2685 else 2686 hw_mode |= 1 << MODE_MF_SI; 2687 2688 #ifndef ASIC_ONLY 2689 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { 2690 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) { 2691 hw_mode |= 1 << MODE_FPGA; 2692 } else { 2693 if (p_hwfn->p_dev->b_is_emul_full) 2694 hw_mode |= 1 << MODE_EMUL_FULL; 2695 else 2696 hw_mode |= 1 << MODE_EMUL_REDUCED; 2697 } 2698 } else 2699 #endif 2700 hw_mode |= 1 << MODE_ASIC; 2701 2702 if (ECORE_IS_CMT(p_hwfn->p_dev)) 2703 hw_mode |= 1 << MODE_100G; 2704 2705 p_hwfn->hw_info.hw_mode = hw_mode; 2706 2707 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP), 2708 "Configuring function for hw_mode: 0x%08x\n", 2709 p_hwfn->hw_info.hw_mode); 2710 2711 return ECORE_SUCCESS; 2712 } 2713 2714 #ifndef ASIC_ONLY 2715 /* MFW-replacement initializations for non-ASIC */ 2716 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn, 2717 struct ecore_ptt *p_ptt) 2718 { 2719 struct ecore_dev *p_dev = p_hwfn->p_dev; 2720 u32 pl_hv = 1; 2721 int i; 2722 2723 if (CHIP_REV_IS_EMUL(p_dev)) { 2724 if (ECORE_IS_AH(p_dev)) 2725 pl_hv |= 0x600; 2726 } 2727 2728 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv); 2729 2730 if (ECORE_IS_AH(p_dev)) 2731 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2, 0x3ffffff); 2732 2733 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */ 2734 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */ 2735 if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev)) 2736 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4); 2737 2738 if (CHIP_REV_IS_EMUL(p_dev)) { 2739 if (ECORE_IS_AH(p_dev)) { 2740 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */ 2741 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE, 2742 (p_dev->num_ports_in_engine >> 1)); 2743 2744 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN, 2745 p_dev->num_ports_in_engine == 4 ? 0 : 3); 2746 } 2747 } 2748 2749 /* Poll on RBC */ 2750 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1); 2751 for (i = 0; i < 100; i++) { 2752 OSAL_UDELAY(50); 2753 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1) 2754 break; 2755 } 2756 if (i == 100) 2757 DP_NOTICE(p_hwfn, true, 2758 "RBC done failed to complete in PSWRQ2\n"); 2759 2760 return ECORE_SUCCESS; 2761 } 2762 #endif 2763 2764 /* Init run time data for all PFs and their VFs on an engine. 2765 * TBD - for VFs - Once we have parent PF info for each VF in 2766 * shmem available as CAU requires knowledge of parent PF for each VF. 2767 */ 2768 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev) 2769 { 2770 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET; 2771 int i, igu_sb_id; 2772 2773 for_each_hwfn(p_dev, i) { 2774 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 2775 struct ecore_igu_info *p_igu_info; 2776 struct ecore_igu_block *p_block; 2777 struct cau_sb_entry sb_entry; 2778 2779 p_igu_info = p_hwfn->hw_info.p_igu_info; 2780 2781 for (igu_sb_id = 0; 2782 igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev); 2783 igu_sb_id++) { 2784 p_block = &p_igu_info->entry[igu_sb_id]; 2785 2786 if (!p_block->is_pf) 2787 continue; 2788 2789 ecore_init_cau_sb_entry(p_hwfn, &sb_entry, 2790 p_block->function_id, 0, 0); 2791 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2, 2792 sb_entry); 2793 } 2794 } 2795 } 2796 2797 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn, 2798 struct ecore_ptt *p_ptt) 2799 { 2800 u32 val, wr_mbs, cache_line_size; 2801 2802 val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0); 2803 switch (val) { 2804 case 0: 2805 wr_mbs = 128; 2806 break; 2807 case 1: 2808 wr_mbs = 256; 2809 break; 2810 case 2: 2811 wr_mbs = 512; 2812 break; 2813 default: 2814 DP_INFO(p_hwfn, 2815 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n", 2816 val); 2817 return; 2818 } 2819 2820 cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs); 2821 switch (cache_line_size) { 2822 case 32: 2823 val = 0; 2824 break; 2825 case 64: 2826 val = 1; 2827 break; 2828 case 128: 2829 val = 2; 2830 break; 2831 case 256: 2832 val = 3; 2833 break; 2834 default: 2835 DP_INFO(p_hwfn, 2836 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n", 2837 cache_line_size); 2838 } 2839 2840 if (wr_mbs < OSAL_CACHE_LINE_SIZE) 2841 DP_INFO(p_hwfn, 2842 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n", 2843 OSAL_CACHE_LINE_SIZE, wr_mbs); 2844 2845 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val); 2846 if (val > 0) { 2847 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val); 2848 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val); 2849 } 2850 } 2851 2852 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn, 2853 struct ecore_ptt *p_ptt, 2854 int hw_mode) 2855 { 2856 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 2857 struct ecore_dev *p_dev = p_hwfn->p_dev; 2858 u8 vf_id, max_num_vfs; 2859 u16 num_pfs, pf_id; 2860 u32 concrete_fid; 2861 enum _ecore_status_t rc = ECORE_SUCCESS; 2862 2863 ecore_init_cau_rt_data(p_dev); 2864 2865 /* Program GTT windows */ 2866 ecore_gtt_init(p_hwfn); 2867 2868 #ifndef ASIC_ONLY 2869 if (CHIP_REV_IS_EMUL(p_dev)) { 2870 rc = ecore_hw_init_chip(p_hwfn, p_ptt); 2871 if (rc != ECORE_SUCCESS) 2872 return rc; 2873 } 2874 #endif 2875 2876 if (p_hwfn->mcp_info) { 2877 if (p_hwfn->mcp_info->func_info.bandwidth_max) 2878 qm_info->pf_rl_en = 1; 2879 if (p_hwfn->mcp_info->func_info.bandwidth_min) 2880 qm_info->pf_wfq_en = 1; 2881 } 2882 2883 ecore_qm_common_rt_init(p_hwfn, 2884 p_dev->num_ports_in_engine, 2885 qm_info->max_phys_tcs_per_port, 2886 qm_info->pf_rl_en, qm_info->pf_wfq_en, 2887 qm_info->vport_rl_en, qm_info->vport_wfq_en, 2888 qm_info->qm_port_params); 2889 2890 ecore_cxt_hw_init_common(p_hwfn); 2891 2892 ecore_init_cache_line_size(p_hwfn, p_ptt); 2893 2894 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ECORE_PATH_ID(p_hwfn), 2895 hw_mode); 2896 if (rc != ECORE_SUCCESS) 2897 return rc; 2898 2899 /* @@TBD MichalK - should add VALIDATE_VFID to init tool... 2900 * need to decide with which value, maybe runtime 2901 */ 2902 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0); 2903 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1); 2904 2905 if (ECORE_IS_BB(p_dev)) { 2906 /* Workaround clears ROCE search for all functions to prevent 2907 * involving non initialized function in processing ROCE packet. 2908 */ 2909 num_pfs = NUM_OF_ENG_PFS(p_dev); 2910 for (pf_id = 0; pf_id < num_pfs; pf_id++) { 2911 ecore_fid_pretend(p_hwfn, p_ptt, pf_id); 2912 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 2913 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 2914 } 2915 /* pretend to original PF */ 2916 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 2917 } 2918 2919 /* Workaround for avoiding CCFC execution error when getting packets 2920 * with CRC errors, and allowing instead the invoking of the FW error 2921 * handler. 2922 * This is not done inside the init tool since it currently can't 2923 * perform a pretending to VFs. 2924 */ 2925 max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB; 2926 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) { 2927 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id); 2928 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid); 2929 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1); 2930 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0); 2931 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1); 2932 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0); 2933 } 2934 /* pretend to original PF */ 2935 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 2936 2937 return rc; 2938 } 2939 2940 #ifndef ASIC_ONLY 2941 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4) 2942 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5) 2943 2944 #define PMEG_IF_BYTE_COUNT 8 2945 2946 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn, 2947 struct ecore_ptt *p_ptt, 2948 u32 addr, u64 data, u8 reg_type, u8 port) 2949 { 2950 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 2951 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n", 2952 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) | 2953 (8 << PMEG_IF_BYTE_COUNT), 2954 (reg_type << 25) | (addr << 8) | port, 2955 (u32)((data >> 32) & 0xffffffff), 2956 (u32)(data & 0xffffffff)); 2957 2958 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB, 2959 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) & 2960 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT)); 2961 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB, 2962 (reg_type << 25) | (addr << 8) | port); 2963 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff); 2964 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, 2965 (data >> 32) & 0xffffffff); 2966 } 2967 2968 #define XLPORT_MODE_REG (0x20a) 2969 #define XLPORT_MAC_CONTROL (0x210) 2970 #define XLPORT_FLOW_CONTROL_CONFIG (0x207) 2971 #define XLPORT_ENABLE_REG (0x20b) 2972 2973 #define XLMAC_CTRL (0x600) 2974 #define XLMAC_MODE (0x601) 2975 #define XLMAC_RX_MAX_SIZE (0x608) 2976 #define XLMAC_TX_CTRL (0x604) 2977 #define XLMAC_PAUSE_CTRL (0x60d) 2978 #define XLMAC_PFC_CTRL (0x60e) 2979 2980 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn, 2981 struct ecore_ptt *p_ptt) 2982 { 2983 u8 loopback = 0, port = p_hwfn->port_id * 2; 2984 2985 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port); 2986 2987 /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */ 2988 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1, 2989 port); 2990 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port); 2991 /* XLMAC: SOFT RESET */ 2992 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port); 2993 /* XLMAC: Port Speed >= 10Gbps */ 2994 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port); 2995 /* XLMAC: Max Size */ 2996 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port); 2997 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL, 2998 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38), 2999 0, port); 3000 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port); 3001 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL, 3002 0x30ffffc000ULL, 0, port); 3003 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0, 3004 port); /* XLMAC: TX_EN, RX_EN */ 3005 /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */ 3006 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 3007 0x1003 | (loopback << 2), 0, port); 3008 /* Enabled Parallel PFC interface */ 3009 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port); 3010 3011 /* XLPORT port enable */ 3012 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port); 3013 } 3014 3015 static void ecore_emul_link_init_ah(struct ecore_hwfn *p_hwfn, 3016 struct ecore_ptt *p_ptt) 3017 { 3018 u32 mac_base, mac_config_val = 0xa853; 3019 u8 port = p_hwfn->port_id; 3020 3021 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2 + (port << 2), 3022 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_SHIFT) | 3023 (port << 3024 CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_SHIFT) | 3025 (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_SHIFT)); 3026 3027 mac_base = NWM_REG_MAC0_K2 + (port << 2) * NWM_REG_MAC0_SIZE; 3028 3029 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2, 3030 1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_SHIFT); 3031 3032 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2, 3033 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_SHIFT); 3034 3035 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2, 3036 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_SHIFT); 3037 3038 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2, 3039 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_SHIFT); 3040 3041 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2, 3042 (0xA << 3043 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_SHIFT) | 3044 (8 << 3045 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_SHIFT)); 3046 3047 /* Strip the CRC field from the frame */ 3048 mac_config_val &= ~ETH_MAC_REG_COMMAND_CONFIG_CRC_FWD_K2; 3049 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2, 3050 mac_config_val); 3051 } 3052 3053 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn, 3054 struct ecore_ptt *p_ptt) 3055 { 3056 u8 port = ECORE_IS_BB(p_hwfn->p_dev) ? p_hwfn->port_id * 2 3057 : p_hwfn->port_id; 3058 3059 DP_INFO(p_hwfn->p_dev, "Emulation: Configuring Link [port %02x]\n", 3060 port); 3061 3062 if (ECORE_IS_BB(p_hwfn->p_dev)) 3063 ecore_emul_link_init_bb(p_hwfn, p_ptt); 3064 else 3065 ecore_emul_link_init_ah(p_hwfn, p_ptt); 3066 3067 return; 3068 } 3069 3070 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn, 3071 struct ecore_ptt *p_ptt, u8 port) 3072 { 3073 int port_offset = port ? 0x800 : 0; 3074 u32 xmac_rxctrl = 0; 3075 3076 /* Reset of XMAC */ 3077 /* FIXME: move to common start */ 3078 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32), 3079 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */ 3080 OSAL_MSLEEP(1); 3081 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32), 3082 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */ 3083 3084 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1); 3085 3086 /* Set the number of ports on the Warp Core to 10G */ 3087 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3); 3088 3089 /* Soft reset of XMAC */ 3090 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32), 3091 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT); 3092 OSAL_MSLEEP(1); 3093 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32), 3094 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT); 3095 3096 /* FIXME: move to common end */ 3097 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) 3098 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20); 3099 3100 /* Set Max packet size: initialize XMAC block register for port 0 */ 3101 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710); 3102 3103 /* CRC append for Tx packets: init XMAC block register for port 1 */ 3104 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800); 3105 3106 /* Enable TX and RX: initialize XMAC block register for port 1 */ 3107 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset, 3108 XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB); 3109 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt, 3110 XMAC_REG_RX_CTRL_BB + port_offset); 3111 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB; 3112 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl); 3113 } 3114 #endif 3115 3116 static enum _ecore_status_t 3117 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn, 3118 struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus) 3119 { 3120 u32 dpi_bit_shift, dpi_count, dpi_page_size; 3121 u32 min_dpis; 3122 u32 n_wids; 3123 3124 /* Calculate DPI size 3125 * ------------------ 3126 * The PWM region contains Doorbell Pages. The first is reserverd for 3127 * the kernel for, e.g, L2. The others are free to be used by non- 3128 * trusted applications, typically from user space. Each page, called a 3129 * doorbell page is sectioned into windows that allow doorbells to be 3130 * issued in parallel by the kernel/application. The size of such a 3131 * window (a.k.a. WID) is 1kB. 3132 * Summary: 3133 * 1kB WID x N WIDS = DPI page size 3134 * DPI page size x N DPIs = PWM region size 3135 * Notes: 3136 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE 3137 * in order to ensure that two applications won't share the same page. 3138 * It also must contain at least one WID per CPU to allow parallelism. 3139 * It also must be a power of 2, since it is stored as a bit shift. 3140 * 3141 * The DPI page size is stored in a register as 'dpi_bit_shift' so that 3142 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096 3143 * containing 4 WIDs. 3144 */ 3145 n_wids = OSAL_MAX_T(u32, ECORE_MIN_WIDS, n_cpus); 3146 dpi_page_size = ECORE_WID_SIZE * OSAL_ROUNDUP_POW_OF_TWO(n_wids); 3147 dpi_page_size = (dpi_page_size + OSAL_PAGE_SIZE - 1) & 3148 ~(OSAL_PAGE_SIZE - 1); 3149 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096); 3150 dpi_count = pwm_region_size / dpi_page_size; 3151 3152 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis; 3153 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis); 3154 3155 /* Update hwfn */ 3156 p_hwfn->dpi_size = dpi_page_size; 3157 p_hwfn->dpi_count = dpi_count; 3158 3159 /* Update registers */ 3160 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift); 3161 3162 if (dpi_count < min_dpis) 3163 return ECORE_NORESOURCES; 3164 3165 return ECORE_SUCCESS; 3166 } 3167 3168 enum ECORE_ROCE_EDPM_MODE { 3169 ECORE_ROCE_EDPM_MODE_ENABLE = 0, 3170 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1, 3171 ECORE_ROCE_EDPM_MODE_DISABLE = 2, 3172 }; 3173 3174 bool ecore_edpm_enabled(struct ecore_hwfn *p_hwfn) 3175 { 3176 if (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm) 3177 return false; 3178 3179 return true; 3180 } 3181 3182 static enum _ecore_status_t 3183 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn, 3184 struct ecore_ptt *p_ptt) 3185 { 3186 u32 pwm_regsize, norm_regsize; 3187 u32 non_pwm_conn, min_addr_reg1; 3188 u32 db_bar_size, n_cpus; 3189 u32 roce_edpm_mode; 3190 u32 pf_dems_shift; 3191 enum _ecore_status_t rc = ECORE_SUCCESS; 3192 u8 cond; 3193 3194 db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1); 3195 if (ECORE_IS_CMT(p_hwfn->p_dev)) 3196 db_bar_size /= 2; 3197 3198 /* Calculate doorbell regions 3199 * ----------------------------------- 3200 * The doorbell BAR is made of two regions. The first is called normal 3201 * region and the second is called PWM region. In the normal region 3202 * each ICID has its own set of addresses so that writing to that 3203 * specific address identifies the ICID. In the Process Window Mode 3204 * region the ICID is given in the data written to the doorbell. The 3205 * above per PF register denotes the offset in the doorbell BAR in which 3206 * the PWM region begins. 3207 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per 3208 * non-PWM connection. The calculation below computes the total non-PWM 3209 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is 3210 * in units of 4,096 bytes. 3211 */ 3212 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) + 3213 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE, 3214 OSAL_NULL) + 3215 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL); 3216 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 3217 OSAL_PAGE_SIZE); 3218 min_addr_reg1 = norm_regsize / 4096; 3219 pwm_regsize = db_bar_size - norm_regsize; 3220 3221 /* Check that the normal and PWM sizes are valid */ 3222 if (db_bar_size < norm_regsize) { 3223 DP_ERR(p_hwfn->p_dev, 3224 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n", 3225 db_bar_size, norm_regsize); 3226 return ECORE_NORESOURCES; 3227 } 3228 if (pwm_regsize < ECORE_MIN_PWM_REGION) { 3229 DP_ERR(p_hwfn->p_dev, 3230 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n", 3231 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size, 3232 norm_regsize); 3233 return ECORE_NORESOURCES; 3234 } 3235 3236 /* Calculate number of DPIs */ 3237 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode; 3238 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) || 3239 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) { 3240 /* Either EDPM is mandatory, or we are attempting to allocate a 3241 * WID per CPU. 3242 */ 3243 n_cpus = OSAL_NUM_CPUS(); 3244 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 3245 } 3246 3247 cond = ((rc != ECORE_SUCCESS) && 3248 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) || 3249 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE); 3250 if (cond || p_hwfn->dcbx_no_edpm) { 3251 /* Either EDPM is disabled from user configuration, or it is 3252 * disabled via DCBx, or it is not mandatory and we failed to 3253 * allocated a WID per CPU. 3254 */ 3255 n_cpus = 1; 3256 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 3257 3258 /* If we entered this flow due to DCBX then the DPM register is 3259 * already configured. 3260 */ 3261 } 3262 3263 DP_INFO(p_hwfn, 3264 "doorbell bar: normal_region_size=%d, pwm_region_size=%d", 3265 norm_regsize, pwm_regsize); 3266 DP_INFO(p_hwfn, 3267 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n", 3268 p_hwfn->dpi_size, p_hwfn->dpi_count, 3269 (!ecore_edpm_enabled(p_hwfn)) ? 3270 "disabled" : "enabled"); 3271 3272 /* Check return codes from above calls */ 3273 if (rc != ECORE_SUCCESS) { 3274 DP_ERR(p_hwfn, 3275 "Failed to allocate enough DPIs\n"); 3276 return ECORE_NORESOURCES; 3277 } 3278 3279 /* Update hwfn */ 3280 p_hwfn->dpi_start_offset = norm_regsize; 3281 3282 /* Update registers */ 3283 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */ 3284 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4); 3285 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift); 3286 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1); 3287 3288 return ECORE_SUCCESS; 3289 } 3290 3291 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn, 3292 struct ecore_ptt *p_ptt, 3293 int hw_mode) 3294 { 3295 enum _ecore_status_t rc = ECORE_SUCCESS; 3296 3297 /* In CMT the gate should be cleared by the 2nd hwfn */ 3298 if (!ECORE_IS_CMT(p_hwfn->p_dev) || !IS_LEAD_HWFN(p_hwfn)) 3299 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0); 3300 3301 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, 3302 hw_mode); 3303 if (rc != ECORE_SUCCESS) 3304 return rc; 3305 3306 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0); 3307 3308 #ifndef ASIC_ONLY 3309 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) 3310 return ECORE_SUCCESS; 3311 3312 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) { 3313 if (ECORE_IS_AH(p_hwfn->p_dev)) 3314 return ECORE_SUCCESS; 3315 else if (ECORE_IS_BB(p_hwfn->p_dev)) 3316 ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id); 3317 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) { 3318 if (ECORE_IS_CMT(p_hwfn->p_dev)) { 3319 /* Activate OPTE in CMT */ 3320 u32 val; 3321 3322 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV); 3323 val |= 0x10; 3324 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val); 3325 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1); 3326 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1); 3327 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1); 3328 ecore_wr(p_hwfn, p_ptt, 3329 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1); 3330 ecore_wr(p_hwfn, p_ptt, 3331 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555); 3332 ecore_wr(p_hwfn, p_ptt, 3333 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4, 3334 0x55555555); 3335 } 3336 3337 ecore_emul_link_init(p_hwfn, p_ptt); 3338 } else { 3339 DP_INFO(p_hwfn->p_dev, "link is not being configured\n"); 3340 } 3341 #endif 3342 3343 return rc; 3344 } 3345 3346 static enum _ecore_status_t 3347 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 3348 int hw_mode, struct ecore_hw_init_params *p_params) 3349 { 3350 u8 rel_pf_id = p_hwfn->rel_pf_id; 3351 u32 prs_reg; 3352 enum _ecore_status_t rc = ECORE_SUCCESS; 3353 u16 ctrl; 3354 int pos; 3355 3356 if (p_hwfn->mcp_info) { 3357 struct ecore_mcp_function_info *p_info; 3358 3359 p_info = &p_hwfn->mcp_info->func_info; 3360 if (p_info->bandwidth_min) 3361 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min; 3362 3363 /* Update rate limit once we'll actually have a link */ 3364 p_hwfn->qm_info.pf_rl = 100000; 3365 } 3366 ecore_cxt_hw_init_pf(p_hwfn, p_ptt); 3367 3368 ecore_int_igu_init_rt(p_hwfn); 3369 3370 /* Set VLAN in NIG if needed */ 3371 if (hw_mode & (1 << MODE_MF_SD)) { 3372 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n"); 3373 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1); 3374 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET, 3375 p_hwfn->hw_info.ovlan); 3376 3377 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 3378 "Configuring LLH_FUNC_FILTER_HDR_SEL\n"); 3379 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET, 3380 1); 3381 } 3382 3383 /* Enable classification by MAC if needed */ 3384 if (hw_mode & (1 << MODE_MF_SI)) { 3385 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 3386 "Configuring TAGMAC_CLS_TYPE\n"); 3387 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 3388 1); 3389 } 3390 3391 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */ 3392 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 3393 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0); 3394 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 3395 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0); 3396 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0); 3397 3398 /* perform debug configuration when chip is out of reset */ 3399 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id); 3400 3401 /* Sanity check before the PF init sequence that uses DMAE */ 3402 rc = ecore_dmae_sanity(p_hwfn, p_ptt, "pf_phase"); 3403 if (rc) 3404 return rc; 3405 3406 /* PF Init sequence */ 3407 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode); 3408 if (rc) 3409 return rc; 3410 3411 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */ 3412 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode); 3413 if (rc) 3414 return rc; 3415 3416 /* Pure runtime initializations - directly to the HW */ 3417 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true); 3418 3419 /* PCI relaxed ordering causes a decrease in the performance on some 3420 * systems. Till a root cause is found, disable this attribute in the 3421 * PCI config space. 3422 */ 3423 /* Not in use @DPDK 3424 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP); 3425 * if (!pos) { 3426 * DP_NOTICE(p_hwfn, true, 3427 * "Failed to find the PCIe Cap\n"); 3428 * return ECORE_IO; 3429 * } 3430 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl); 3431 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN; 3432 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl); 3433 */ 3434 3435 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt); 3436 if (rc != ECORE_SUCCESS) 3437 return rc; 3438 3439 /* Use the leading hwfn since in CMT only NIG #0 is operational */ 3440 if (IS_LEAD_HWFN(p_hwfn)) { 3441 rc = ecore_llh_hw_init_pf(p_hwfn, p_ptt, 3442 p_params->avoid_eng_affin); 3443 if (rc) 3444 return rc; 3445 } 3446 3447 if (p_params->b_hw_start) { 3448 /* enable interrupts */ 3449 rc = ecore_int_igu_enable(p_hwfn, p_ptt, p_params->int_mode); 3450 if (rc != ECORE_SUCCESS) 3451 return rc; 3452 3453 /* send function start command */ 3454 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_params->p_tunn, 3455 p_params->allow_npar_tx_switch); 3456 if (rc) { 3457 DP_NOTICE(p_hwfn, true, 3458 "Function start ramrod failed\n"); 3459 } else { 3460 return rc; 3461 } 3462 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1); 3463 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 3464 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg); 3465 3466 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) { 3467 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, 3468 (1 << 2)); 3469 ecore_wr(p_hwfn, p_ptt, 3470 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST, 3471 0x100); 3472 } 3473 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 3474 "PRS_REG_SEARCH registers after start PFn\n"); 3475 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP); 3476 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 3477 "PRS_REG_SEARCH_TCP: %x\n", prs_reg); 3478 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP); 3479 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 3480 "PRS_REG_SEARCH_UDP: %x\n", prs_reg); 3481 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE); 3482 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 3483 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg); 3484 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE); 3485 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 3486 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg); 3487 prs_reg = ecore_rd(p_hwfn, p_ptt, 3488 PRS_REG_SEARCH_TCP_FIRST_FRAG); 3489 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 3490 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n", 3491 prs_reg); 3492 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1); 3493 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 3494 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg); 3495 } 3496 return ECORE_SUCCESS; 3497 } 3498 3499 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn, 3500 struct ecore_ptt *p_ptt, 3501 bool b_enable) 3502 { 3503 u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0; 3504 3505 /* Configure the PF's internal FID_enable for master transactions */ 3506 ecore_wr(p_hwfn, p_ptt, 3507 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val); 3508 3509 /* Wait until value is set - try for 1 second every 50us */ 3510 for (delay_idx = 0; delay_idx < 20000; delay_idx++) { 3511 val = ecore_rd(p_hwfn, p_ptt, 3512 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 3513 if (val == set_val) 3514 break; 3515 3516 OSAL_UDELAY(50); 3517 } 3518 3519 if (val != set_val) { 3520 DP_NOTICE(p_hwfn, true, 3521 "PFID_ENABLE_MASTER wasn't changed after a second\n"); 3522 return ECORE_UNKNOWN_ERROR; 3523 } 3524 3525 return ECORE_SUCCESS; 3526 } 3527 3528 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn, 3529 struct ecore_ptt *p_main_ptt) 3530 { 3531 /* Read shadow of current MFW mailbox */ 3532 ecore_mcp_read_mb(p_hwfn, p_main_ptt); 3533 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow, 3534 p_hwfn->mcp_info->mfw_mb_cur, 3535 p_hwfn->mcp_info->mfw_mb_length); 3536 } 3537 3538 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn, 3539 struct ecore_ptt *p_ptt) 3540 { 3541 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 3542 1 << p_hwfn->abs_pf_id); 3543 } 3544 3545 static enum _ecore_status_t 3546 ecore_fill_load_req_params(struct ecore_hwfn *p_hwfn, 3547 struct ecore_load_req_params *p_load_req, 3548 struct ecore_drv_load_params *p_drv_load) 3549 { 3550 /* Make sure that if ecore-client didn't provide inputs, all the 3551 * expected defaults are indeed zero. 3552 */ 3553 OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0); 3554 OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0); 3555 OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0); 3556 3557 OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req)); 3558 3559 if (p_drv_load == OSAL_NULL) 3560 goto out; 3561 3562 p_load_req->drv_role = p_drv_load->is_crash_kernel ? 3563 ECORE_DRV_ROLE_KDUMP : 3564 ECORE_DRV_ROLE_OS; 3565 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset; 3566 p_load_req->override_force_load = p_drv_load->override_force_load; 3567 3568 /* Old MFW versions don't support timeout values other than default and 3569 * none, so these values are replaced according to the fall-back action. 3570 */ 3571 3572 if (p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT || 3573 p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_NONE || 3574 (p_hwfn->mcp_info->capabilities & 3575 FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO)) { 3576 p_load_req->timeout_val = p_drv_load->mfw_timeout_val; 3577 goto out; 3578 } 3579 3580 switch (p_drv_load->mfw_timeout_fallback) { 3581 case ECORE_TO_FALLBACK_TO_NONE: 3582 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_NONE; 3583 break; 3584 case ECORE_TO_FALLBACK_TO_DEFAULT: 3585 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_DEFAULT; 3586 break; 3587 case ECORE_TO_FALLBACK_FAIL_LOAD: 3588 DP_NOTICE(p_hwfn, false, 3589 "Received %d as a value for MFW timeout while the MFW supports only default [%d] or none [%d]. Abort.\n", 3590 p_drv_load->mfw_timeout_val, 3591 ECORE_LOAD_REQ_LOCK_TO_DEFAULT, 3592 ECORE_LOAD_REQ_LOCK_TO_NONE); 3593 return ECORE_ABORTED; 3594 } 3595 3596 DP_INFO(p_hwfn, 3597 "Modified the MFW timeout value from %d to %s [%d] due to lack of MFW support\n", 3598 p_drv_load->mfw_timeout_val, 3599 (p_load_req->timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT) ? 3600 "default" : "none", 3601 p_load_req->timeout_val); 3602 out: 3603 return ECORE_SUCCESS; 3604 } 3605 3606 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn, 3607 struct ecore_hw_init_params *p_params) 3608 { 3609 if (p_params->p_tunn) { 3610 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn); 3611 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn); 3612 } 3613 3614 p_hwfn->b_int_enabled = 1; 3615 3616 return ECORE_SUCCESS; 3617 } 3618 3619 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev, 3620 struct ecore_hw_init_params *p_params) 3621 { 3622 struct ecore_load_req_params load_req_params; 3623 u32 load_code, resp, param, drv_mb_param; 3624 bool b_default_mtu = true; 3625 struct ecore_hwfn *p_hwfn; 3626 enum _ecore_status_t rc = ECORE_SUCCESS; 3627 u16 ether_type; 3628 int i; 3629 3630 if ((p_params->int_mode == ECORE_INT_MODE_MSI) && ECORE_IS_CMT(p_dev)) { 3631 DP_NOTICE(p_dev, false, 3632 "MSI mode is not supported for CMT devices\n"); 3633 return ECORE_INVAL; 3634 } 3635 3636 if (IS_PF(p_dev)) { 3637 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data); 3638 if (rc != ECORE_SUCCESS) 3639 return rc; 3640 } 3641 3642 for_each_hwfn(p_dev, i) { 3643 p_hwfn = &p_dev->hwfns[i]; 3644 3645 /* If management didn't provide a default, set one of our own */ 3646 if (!p_hwfn->hw_info.mtu) { 3647 p_hwfn->hw_info.mtu = 1500; 3648 b_default_mtu = false; 3649 } 3650 3651 if (IS_VF(p_dev)) { 3652 ecore_vf_start(p_hwfn, p_params); 3653 continue; 3654 } 3655 3656 rc = ecore_calc_hw_mode(p_hwfn); 3657 if (rc != ECORE_SUCCESS) 3658 return rc; 3659 3660 if (IS_PF(p_dev) && (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING, 3661 &p_dev->mf_bits) || 3662 OSAL_TEST_BIT(ECORE_MF_8021AD_TAGGING, 3663 &p_dev->mf_bits))) { 3664 if (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING, 3665 &p_dev->mf_bits)) 3666 ether_type = ETHER_TYPE_VLAN; 3667 else 3668 ether_type = ETHER_TYPE_QINQ; 3669 STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET, 3670 ether_type); 3671 STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET, 3672 ether_type); 3673 STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET, 3674 ether_type); 3675 STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET, 3676 ether_type); 3677 } 3678 3679 ecore_set_spq_block_timeout(p_hwfn, p_params->spq_timeout_ms); 3680 3681 rc = ecore_fill_load_req_params(p_hwfn, &load_req_params, 3682 p_params->p_drv_load_params); 3683 if (rc != ECORE_SUCCESS) 3684 return rc; 3685 3686 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, 3687 &load_req_params); 3688 if (rc != ECORE_SUCCESS) { 3689 DP_NOTICE(p_hwfn, false, 3690 "Failed sending a LOAD_REQ command\n"); 3691 return rc; 3692 } 3693 3694 load_code = load_req_params.load_code; 3695 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, 3696 "Load request was sent. Load code: 0x%x\n", 3697 load_code); 3698 3699 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt); 3700 3701 /* CQ75580: 3702 * When coming back from hiberbate state, the registers from 3703 * which shadow is read initially are not initialized. It turns 3704 * out that these registers get initialized during the call to 3705 * ecore_mcp_load_req request. So we need to reread them here 3706 * to get the proper shadow register value. 3707 * Note: This is a workaround for the missing MFW 3708 * initialization. It may be removed once the implementation 3709 * is done. 3710 */ 3711 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt); 3712 3713 /* Only relevant for recovery: 3714 * Clear the indication after the LOAD_REQ command is responded 3715 * by the MFW. 3716 */ 3717 p_dev->recov_in_prog = false; 3718 3719 p_hwfn->first_on_engine = (load_code == 3720 FW_MSG_CODE_DRV_LOAD_ENGINE); 3721 3722 if (!qm_lock_ref_cnt) { 3723 #ifdef CONFIG_ECORE_LOCK_ALLOC 3724 rc = OSAL_SPIN_LOCK_ALLOC(p_hwfn, &qm_lock); 3725 if (rc) { 3726 DP_ERR(p_hwfn, "qm_lock allocation failed\n"); 3727 goto qm_lock_fail; 3728 } 3729 #endif 3730 OSAL_SPIN_LOCK_INIT(&qm_lock); 3731 } 3732 ++qm_lock_ref_cnt; 3733 3734 /* Clean up chip from previous driver if such remains exist. 3735 * This is not needed when the PF is the first one on the 3736 * engine, since afterwards we are going to init the FW. 3737 */ 3738 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) { 3739 rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt, 3740 p_hwfn->rel_pf_id, false); 3741 if (rc != ECORE_SUCCESS) { 3742 ecore_hw_err_notify(p_hwfn, 3743 ECORE_HW_ERR_RAMROD_FAIL); 3744 goto load_err; 3745 } 3746 } 3747 3748 /* Log and clear previous pglue_b errors if such exist */ 3749 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt, true); 3750 3751 /* Enable the PF's internal FID_enable in the PXP */ 3752 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt, 3753 true); 3754 if (rc != ECORE_SUCCESS) 3755 goto load_err; 3756 3757 /* Clear the pglue_b was_error indication. 3758 * In E4 it must be done after the BME and the internal 3759 * FID_enable for the PF are set, since VDMs may cause the 3760 * indication to be set again. 3761 */ 3762 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt); 3763 3764 switch (load_code) { 3765 case FW_MSG_CODE_DRV_LOAD_ENGINE: 3766 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt, 3767 p_hwfn->hw_info.hw_mode); 3768 if (rc != ECORE_SUCCESS) 3769 break; 3770 /* Fall into */ 3771 case FW_MSG_CODE_DRV_LOAD_PORT: 3772 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt, 3773 p_hwfn->hw_info.hw_mode); 3774 if (rc != ECORE_SUCCESS) 3775 break; 3776 /* Fall into */ 3777 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 3778 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt, 3779 p_hwfn->hw_info.hw_mode, 3780 p_params); 3781 break; 3782 default: 3783 DP_NOTICE(p_hwfn, false, 3784 "Unexpected load code [0x%08x]", load_code); 3785 rc = ECORE_NOTIMPL; 3786 break; 3787 } 3788 3789 if (rc != ECORE_SUCCESS) { 3790 DP_NOTICE(p_hwfn, false, 3791 "init phase failed for loadcode 0x%x (rc %d)\n", 3792 load_code, rc); 3793 goto load_err; 3794 } 3795 3796 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt); 3797 if (rc != ECORE_SUCCESS) { 3798 DP_NOTICE(p_hwfn, false, 3799 "Sending load done failed, rc = %d\n", rc); 3800 if (rc == ECORE_NOMEM) { 3801 DP_NOTICE(p_hwfn, false, 3802 "Sending load done was failed due to memory allocation failure\n"); 3803 goto load_err; 3804 } 3805 return rc; 3806 } 3807 3808 /* send DCBX attention request command */ 3809 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 3810 "sending phony dcbx set command to trigger DCBx attention handling\n"); 3811 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 3812 DRV_MSG_CODE_SET_DCBX, 3813 1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET, &resp, 3814 ¶m); 3815 if (rc != ECORE_SUCCESS) { 3816 DP_NOTICE(p_hwfn, false, 3817 "Failed to send DCBX attention request\n"); 3818 return rc; 3819 } 3820 3821 p_hwfn->hw_init_done = true; 3822 } 3823 3824 if (IS_PF(p_dev)) { 3825 /* Get pre-negotiated values for stag, bandwidth etc. */ 3826 p_hwfn = ECORE_LEADING_HWFN(p_dev); 3827 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, 3828 "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n"); 3829 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 3830 DRV_MSG_CODE_GET_OEM_UPDATES, 3831 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET, 3832 &resp, ¶m); 3833 if (rc != ECORE_SUCCESS) 3834 DP_NOTICE(p_hwfn, false, 3835 "Failed to send GET_OEM_UPDATES attention request\n"); 3836 } 3837 3838 if (IS_PF(p_dev)) { 3839 /* Get pre-negotiated values for stag, bandwidth etc. */ 3840 p_hwfn = ECORE_LEADING_HWFN(p_dev); 3841 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, 3842 "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n"); 3843 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 3844 DRV_MSG_CODE_GET_OEM_UPDATES, 3845 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET, 3846 &resp, ¶m); 3847 if (rc != ECORE_SUCCESS) 3848 DP_NOTICE(p_hwfn, false, 3849 "Failed to send GET_OEM_UPDATES attention request\n"); 3850 } 3851 3852 if (IS_PF(p_dev)) { 3853 p_hwfn = ECORE_LEADING_HWFN(p_dev); 3854 drv_mb_param = STORM_FW_VERSION; 3855 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 3856 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER, 3857 drv_mb_param, &resp, ¶m); 3858 if (rc != ECORE_SUCCESS) 3859 DP_INFO(p_hwfn, "Failed to update firmware version\n"); 3860 3861 if (!b_default_mtu) { 3862 rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt, 3863 p_hwfn->hw_info.mtu); 3864 if (rc != ECORE_SUCCESS) 3865 DP_INFO(p_hwfn, "Failed to update default mtu\n"); 3866 } 3867 3868 rc = ecore_mcp_ov_update_driver_state(p_hwfn, 3869 p_hwfn->p_main_ptt, 3870 ECORE_OV_DRIVER_STATE_DISABLED); 3871 if (rc != ECORE_SUCCESS) 3872 DP_INFO(p_hwfn, "Failed to update driver state\n"); 3873 3874 rc = ecore_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt, 3875 ECORE_OV_ESWITCH_NONE); 3876 if (rc != ECORE_SUCCESS) 3877 DP_INFO(p_hwfn, "Failed to update eswitch mode\n"); 3878 } 3879 3880 return rc; 3881 3882 load_err: 3883 --qm_lock_ref_cnt; 3884 #ifdef CONFIG_ECORE_LOCK_ALLOC 3885 if (!qm_lock_ref_cnt) 3886 OSAL_SPIN_LOCK_DEALLOC(&qm_lock); 3887 qm_lock_fail: 3888 #endif 3889 /* The MFW load lock should be released regardless of success or failure 3890 * of initialization. 3891 * TODO: replace this with an attempt to send cancel_load. 3892 */ 3893 ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt); 3894 return rc; 3895 } 3896 3897 #define ECORE_HW_STOP_RETRY_LIMIT (10) 3898 static void ecore_hw_timers_stop(struct ecore_dev *p_dev, 3899 struct ecore_hwfn *p_hwfn, 3900 struct ecore_ptt *p_ptt) 3901 { 3902 int i; 3903 3904 /* close timers */ 3905 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0); 3906 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0); 3907 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog; 3908 i++) { 3909 if ((!ecore_rd(p_hwfn, p_ptt, 3910 TM_REG_PF_SCAN_ACTIVE_CONN)) && 3911 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK))) 3912 break; 3913 3914 /* Dependent on number of connection/tasks, possibly 3915 * 1ms sleep is required between polls 3916 */ 3917 OSAL_MSLEEP(1); 3918 } 3919 3920 if (i < ECORE_HW_STOP_RETRY_LIMIT) 3921 return; 3922 3923 DP_NOTICE(p_hwfn, false, 3924 "Timers linear scans are not over [Connection %02x Tasks %02x]\n", 3925 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN), 3926 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)); 3927 } 3928 3929 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev) 3930 { 3931 int j; 3932 3933 for_each_hwfn(p_dev, j) { 3934 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j]; 3935 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt; 3936 3937 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt); 3938 } 3939 } 3940 3941 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn, 3942 struct ecore_ptt *p_ptt, 3943 u32 addr, u32 expected_val) 3944 { 3945 u32 val = ecore_rd(p_hwfn, p_ptt, addr); 3946 3947 if (val != expected_val) { 3948 DP_NOTICE(p_hwfn, true, 3949 "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n", 3950 addr, val, expected_val); 3951 return ECORE_UNKNOWN_ERROR; 3952 } 3953 3954 return ECORE_SUCCESS; 3955 } 3956 3957 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev) 3958 { 3959 struct ecore_hwfn *p_hwfn; 3960 struct ecore_ptt *p_ptt; 3961 enum _ecore_status_t rc, rc2 = ECORE_SUCCESS; 3962 int j; 3963 3964 for_each_hwfn(p_dev, j) { 3965 p_hwfn = &p_dev->hwfns[j]; 3966 p_ptt = p_hwfn->p_main_ptt; 3967 3968 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n"); 3969 3970 if (IS_VF(p_dev)) { 3971 ecore_vf_pf_int_cleanup(p_hwfn); 3972 rc = ecore_vf_pf_reset(p_hwfn); 3973 if (rc != ECORE_SUCCESS) { 3974 DP_NOTICE(p_hwfn, true, 3975 "ecore_vf_pf_reset failed. rc = %d.\n", 3976 rc); 3977 rc2 = ECORE_UNKNOWN_ERROR; 3978 } 3979 continue; 3980 } 3981 3982 /* mark the hw as uninitialized... */ 3983 p_hwfn->hw_init_done = false; 3984 3985 /* Send unload command to MCP */ 3986 if (!p_dev->recov_in_prog) { 3987 rc = ecore_mcp_unload_req(p_hwfn, p_ptt); 3988 if (rc != ECORE_SUCCESS) { 3989 DP_NOTICE(p_hwfn, false, 3990 "Failed sending a UNLOAD_REQ command. rc = %d.\n", 3991 rc); 3992 rc2 = ECORE_UNKNOWN_ERROR; 3993 } 3994 } 3995 3996 OSAL_DPC_SYNC(p_hwfn); 3997 3998 /* After this point no MFW attentions are expected, e.g. prevent 3999 * race between pf stop and dcbx pf update. 4000 */ 4001 4002 rc = ecore_sp_pf_stop(p_hwfn); 4003 if (rc != ECORE_SUCCESS) { 4004 DP_NOTICE(p_hwfn, false, 4005 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n", 4006 rc); 4007 rc2 = ECORE_UNKNOWN_ERROR; 4008 } 4009 4010 OSAL_DPC_SYNC(p_hwfn); 4011 4012 /* After this point we don't expect the FW to send us async 4013 * events 4014 */ 4015 4016 /* perform debug action after PF stop was sent */ 4017 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id); 4018 4019 /* close NIG to BRB gate */ 4020 ecore_wr(p_hwfn, p_ptt, 4021 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 4022 4023 /* close parser */ 4024 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 4025 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 4026 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 4027 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 4028 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 4029 4030 /* @@@TBD - clean transmission queues (5.b) */ 4031 /* @@@TBD - clean BTB (5.c) */ 4032 4033 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt); 4034 4035 /* @@@TBD - verify DMAE requests are done (8) */ 4036 4037 /* Disable Attention Generation */ 4038 ecore_int_igu_disable_int(p_hwfn, p_ptt); 4039 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0); 4040 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0); 4041 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true); 4042 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt); 4043 if (rc != ECORE_SUCCESS) { 4044 DP_NOTICE(p_hwfn, true, 4045 "Failed to return IGU CAM to default\n"); 4046 rc2 = ECORE_UNKNOWN_ERROR; 4047 } 4048 4049 /* Need to wait 1ms to guarantee SBs are cleared */ 4050 OSAL_MSLEEP(1); 4051 4052 if (IS_LEAD_HWFN(p_hwfn) && 4053 OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) && 4054 !ECORE_IS_FCOE_PERSONALITY(p_hwfn)) 4055 ecore_llh_remove_mac_filter(p_dev, 0, 4056 p_hwfn->hw_info.hw_mac_addr); 4057 4058 if (!p_dev->recov_in_prog) { 4059 ecore_verify_reg_val(p_hwfn, p_ptt, 4060 QM_REG_USG_CNT_PF_TX, 0); 4061 ecore_verify_reg_val(p_hwfn, p_ptt, 4062 QM_REG_USG_CNT_PF_OTHER, 0); 4063 /* @@@TBD - assert on incorrect xCFC values (10.b) */ 4064 } 4065 4066 /* Disable PF in HW blocks */ 4067 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0); 4068 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0); 4069 4070 --qm_lock_ref_cnt; 4071 #ifdef CONFIG_ECORE_LOCK_ALLOC 4072 if (!qm_lock_ref_cnt) 4073 OSAL_SPIN_LOCK_DEALLOC(&qm_lock); 4074 #endif 4075 4076 if (!p_dev->recov_in_prog) { 4077 rc = ecore_mcp_unload_done(p_hwfn, p_ptt); 4078 if (rc == ECORE_NOMEM) { 4079 DP_NOTICE(p_hwfn, false, 4080 "Failed sending an UNLOAD_DONE command due to a memory allocation failure. Resending.\n"); 4081 rc = ecore_mcp_unload_done(p_hwfn, p_ptt); 4082 } 4083 if (rc != ECORE_SUCCESS) { 4084 DP_NOTICE(p_hwfn, false, 4085 "Failed sending a UNLOAD_DONE command. rc = %d.\n", 4086 rc); 4087 rc2 = ECORE_UNKNOWN_ERROR; 4088 } 4089 } 4090 } /* hwfn loop */ 4091 4092 if (IS_PF(p_dev) && !p_dev->recov_in_prog) { 4093 p_hwfn = ECORE_LEADING_HWFN(p_dev); 4094 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt; 4095 4096 /* Clear the PF's internal FID_enable in the PXP. 4097 * In CMT this should only be done for first hw-function, and 4098 * only after all transactions have stopped for all active 4099 * hw-functions. 4100 */ 4101 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt, 4102 false); 4103 if (rc != ECORE_SUCCESS) { 4104 DP_NOTICE(p_hwfn, true, 4105 "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n", 4106 rc); 4107 rc2 = ECORE_UNKNOWN_ERROR; 4108 } 4109 } 4110 4111 return rc2; 4112 } 4113 4114 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev) 4115 { 4116 int j; 4117 4118 for_each_hwfn(p_dev, j) { 4119 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j]; 4120 struct ecore_ptt *p_ptt; 4121 4122 if (IS_VF(p_dev)) { 4123 ecore_vf_pf_int_cleanup(p_hwfn); 4124 continue; 4125 } 4126 p_ptt = ecore_ptt_acquire(p_hwfn); 4127 if (!p_ptt) 4128 return ECORE_AGAIN; 4129 4130 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, 4131 "Shutting down the fastpath\n"); 4132 4133 ecore_wr(p_hwfn, p_ptt, 4134 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 4135 4136 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 4137 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 4138 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 4139 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 4140 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 4141 4142 /* @@@TBD - clean transmission queues (5.b) */ 4143 /* @@@TBD - clean BTB (5.c) */ 4144 4145 /* @@@TBD - verify DMAE requests are done (8) */ 4146 4147 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false); 4148 /* Need to wait 1ms to guarantee SBs are cleared */ 4149 OSAL_MSLEEP(1); 4150 ecore_ptt_release(p_hwfn, p_ptt); 4151 } 4152 4153 return ECORE_SUCCESS; 4154 } 4155 4156 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn) 4157 { 4158 struct ecore_ptt *p_ptt; 4159 4160 if (IS_VF(p_hwfn->p_dev)) 4161 return ECORE_SUCCESS; 4162 4163 p_ptt = ecore_ptt_acquire(p_hwfn); 4164 if (!p_ptt) 4165 return ECORE_AGAIN; 4166 4167 /* If roce info is allocated it means roce is initialized and should 4168 * be enabled in searcher. 4169 */ 4170 if (p_hwfn->p_rdma_info) { 4171 if (p_hwfn->b_rdma_enabled_in_prs) 4172 ecore_wr(p_hwfn, p_ptt, 4173 p_hwfn->rdma_prs_search_reg, 0x1); 4174 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1); 4175 } 4176 4177 /* Re-open incoming traffic */ 4178 ecore_wr(p_hwfn, p_ptt, 4179 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0); 4180 ecore_ptt_release(p_hwfn, p_ptt); 4181 4182 return ECORE_SUCCESS; 4183 } 4184 4185 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */ 4186 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn) 4187 { 4188 ecore_ptt_pool_free(p_hwfn); 4189 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info); 4190 } 4191 4192 /* Setup bar access */ 4193 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn) 4194 { 4195 /* clear indirect access */ 4196 if (ECORE_IS_AH(p_hwfn->p_dev)) { 4197 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 4198 PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0); 4199 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 4200 PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0); 4201 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 4202 PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0); 4203 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 4204 PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0); 4205 } else { 4206 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 4207 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0); 4208 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 4209 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0); 4210 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 4211 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0); 4212 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 4213 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0); 4214 } 4215 4216 /* Clean previous pglue_b errors if such exist */ 4217 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt); 4218 4219 /* enable internal target-read */ 4220 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 4221 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 4222 } 4223 4224 static void get_function_id(struct ecore_hwfn *p_hwfn) 4225 { 4226 /* ME Register */ 4227 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, 4228 PXP_PF_ME_OPAQUE_ADDR); 4229 4230 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); 4231 4232 /* Bits 16-19 from the ME registers are the pf_num */ 4233 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf; 4234 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 4235 PXP_CONCRETE_FID_PFID); 4236 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 4237 PXP_CONCRETE_FID_PORT); 4238 4239 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, 4240 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n", 4241 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid); 4242 } 4243 4244 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn) 4245 { 4246 u32 *feat_num = p_hwfn->hw_info.feat_num; 4247 struct ecore_sb_cnt_info sb_cnt; 4248 u32 non_l2_sbs = 0; 4249 4250 OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt)); 4251 ecore_int_get_num_sbs(p_hwfn, &sb_cnt); 4252 4253 /* L2 Queues require each: 1 status block. 1 L2 queue */ 4254 if (ECORE_IS_L2_PERSONALITY(p_hwfn)) { 4255 /* Start by allocating VF queues, then PF's */ 4256 feat_num[ECORE_VF_L2_QUE] = 4257 OSAL_MIN_T(u32, 4258 RESC_NUM(p_hwfn, ECORE_L2_QUEUE), 4259 sb_cnt.iov_cnt); 4260 feat_num[ECORE_PF_L2_QUE] = 4261 OSAL_MIN_T(u32, 4262 sb_cnt.cnt - non_l2_sbs, 4263 RESC_NUM(p_hwfn, ECORE_L2_QUEUE) - 4264 FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE)); 4265 } 4266 4267 if (ECORE_IS_FCOE_PERSONALITY(p_hwfn) || 4268 ECORE_IS_ISCSI_PERSONALITY(p_hwfn)) { 4269 u32 *p_storage_feat = ECORE_IS_FCOE_PERSONALITY(p_hwfn) ? 4270 &feat_num[ECORE_FCOE_CQ] : 4271 &feat_num[ECORE_ISCSI_CQ]; 4272 u32 limit = sb_cnt.cnt; 4273 4274 /* The number of queues should not exceed the number of FP SBs. 4275 * In storage target, the queues are divided into pairs of a CQ 4276 * and a CmdQ, and each pair uses a single SB. The limit in 4277 * this case should allow a max ratio of 2:1 instead of 1:1. 4278 */ 4279 if (p_hwfn->p_dev->b_is_target) 4280 limit *= 2; 4281 *p_storage_feat = OSAL_MIN_T(u32, limit, 4282 RESC_NUM(p_hwfn, ECORE_CMDQS_CQS)); 4283 4284 /* @DPDK */ 4285 /* The size of "cq_cmdq_sb_num_arr" in the fcoe/iscsi init 4286 * ramrod is limited to "NUM_OF_GLOBAL_QUEUES / 2". 4287 */ 4288 *p_storage_feat = OSAL_MIN_T(u32, *p_storage_feat, 4289 (NUM_OF_GLOBAL_QUEUES / 2)); 4290 } 4291 4292 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, 4293 "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n", 4294 (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE), 4295 (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE), 4296 (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ), 4297 (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ), 4298 (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ), 4299 (int)sb_cnt.cnt); 4300 } 4301 4302 const char *ecore_hw_get_resc_name(enum ecore_resources res_id) 4303 { 4304 switch (res_id) { 4305 case ECORE_L2_QUEUE: 4306 return "L2_QUEUE"; 4307 case ECORE_VPORT: 4308 return "VPORT"; 4309 case ECORE_RSS_ENG: 4310 return "RSS_ENG"; 4311 case ECORE_PQ: 4312 return "PQ"; 4313 case ECORE_RL: 4314 return "RL"; 4315 case ECORE_MAC: 4316 return "MAC"; 4317 case ECORE_VLAN: 4318 return "VLAN"; 4319 case ECORE_RDMA_CNQ_RAM: 4320 return "RDMA_CNQ_RAM"; 4321 case ECORE_ILT: 4322 return "ILT"; 4323 case ECORE_LL2_QUEUE: 4324 return "LL2_QUEUE"; 4325 case ECORE_CMDQS_CQS: 4326 return "CMDQS_CQS"; 4327 case ECORE_RDMA_STATS_QUEUE: 4328 return "RDMA_STATS_QUEUE"; 4329 case ECORE_BDQ: 4330 return "BDQ"; 4331 case ECORE_SB: 4332 return "SB"; 4333 default: 4334 return "UNKNOWN_RESOURCE"; 4335 } 4336 } 4337 4338 static enum _ecore_status_t 4339 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn, 4340 struct ecore_ptt *p_ptt, 4341 enum ecore_resources res_id, 4342 u32 resc_max_val, 4343 u32 *p_mcp_resp) 4344 { 4345 enum _ecore_status_t rc; 4346 4347 rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id, 4348 resc_max_val, p_mcp_resp); 4349 if (rc != ECORE_SUCCESS) { 4350 DP_NOTICE(p_hwfn, false, 4351 "MFW response failure for a max value setting of resource %d [%s]\n", 4352 res_id, ecore_hw_get_resc_name(res_id)); 4353 return rc; 4354 } 4355 4356 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) 4357 DP_INFO(p_hwfn, 4358 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n", 4359 res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp); 4360 4361 return ECORE_SUCCESS; 4362 } 4363 4364 static enum _ecore_status_t 4365 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn, 4366 struct ecore_ptt *p_ptt) 4367 { 4368 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev); 4369 u32 resc_max_val, mcp_resp; 4370 u8 res_id; 4371 enum _ecore_status_t rc; 4372 4373 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) { 4374 /* @DPDK */ 4375 switch (res_id) { 4376 case ECORE_LL2_QUEUE: 4377 case ECORE_RDMA_CNQ_RAM: 4378 case ECORE_RDMA_STATS_QUEUE: 4379 case ECORE_BDQ: 4380 resc_max_val = 0; 4381 break; 4382 default: 4383 continue; 4384 } 4385 4386 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id, 4387 resc_max_val, &mcp_resp); 4388 if (rc != ECORE_SUCCESS) 4389 return rc; 4390 4391 /* There's no point to continue to the next resource if the 4392 * command is not supported by the MFW. 4393 * We do continue if the command is supported but the resource 4394 * is unknown to the MFW. Such a resource will be later 4395 * configured with the default allocation values. 4396 */ 4397 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED) 4398 return ECORE_NOTIMPL; 4399 } 4400 4401 return ECORE_SUCCESS; 4402 } 4403 4404 static 4405 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn, 4406 enum ecore_resources res_id, 4407 u32 *p_resc_num, u32 *p_resc_start) 4408 { 4409 u8 num_funcs = p_hwfn->num_funcs_on_engine; 4410 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev); 4411 4412 switch (res_id) { 4413 case ECORE_L2_QUEUE: 4414 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 : 4415 MAX_NUM_L2_QUEUES_BB) / num_funcs; 4416 break; 4417 case ECORE_VPORT: 4418 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 : 4419 MAX_NUM_VPORTS_BB) / num_funcs; 4420 break; 4421 case ECORE_RSS_ENG: 4422 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 : 4423 ETH_RSS_ENGINE_NUM_BB) / num_funcs; 4424 break; 4425 case ECORE_PQ: 4426 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 : 4427 MAX_QM_TX_QUEUES_BB) / num_funcs; 4428 break; 4429 case ECORE_RL: 4430 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs; 4431 break; 4432 case ECORE_MAC: 4433 case ECORE_VLAN: 4434 /* Each VFC resource can accommodate both a MAC and a VLAN */ 4435 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs; 4436 break; 4437 case ECORE_ILT: 4438 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 : 4439 PXP_NUM_ILT_RECORDS_BB) / num_funcs; 4440 break; 4441 case ECORE_LL2_QUEUE: 4442 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs; 4443 break; 4444 case ECORE_RDMA_CNQ_RAM: 4445 case ECORE_CMDQS_CQS: 4446 /* CNQ/CMDQS are the same resource */ 4447 /* @DPDK */ 4448 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs; 4449 break; 4450 case ECORE_RDMA_STATS_QUEUE: 4451 /* @DPDK */ 4452 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 : 4453 MAX_NUM_VPORTS_BB) / num_funcs; 4454 break; 4455 case ECORE_BDQ: 4456 /* @DPDK */ 4457 *p_resc_num = 0; 4458 break; 4459 default: 4460 break; 4461 } 4462 4463 4464 switch (res_id) { 4465 case ECORE_BDQ: 4466 if (!*p_resc_num) 4467 *p_resc_start = 0; 4468 break; 4469 case ECORE_SB: 4470 /* Since we want its value to reflect whether MFW supports 4471 * the new scheme, have a default of 0. 4472 */ 4473 *p_resc_num = 0; 4474 break; 4475 default: 4476 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx; 4477 break; 4478 } 4479 4480 return ECORE_SUCCESS; 4481 } 4482 4483 static enum _ecore_status_t 4484 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id, 4485 bool drv_resc_alloc) 4486 { 4487 u32 dflt_resc_num = 0, dflt_resc_start = 0; 4488 u32 mcp_resp, *p_resc_num, *p_resc_start; 4489 enum _ecore_status_t rc; 4490 4491 p_resc_num = &RESC_NUM(p_hwfn, res_id); 4492 p_resc_start = &RESC_START(p_hwfn, res_id); 4493 4494 rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num, 4495 &dflt_resc_start); 4496 if (rc != ECORE_SUCCESS) { 4497 DP_ERR(p_hwfn, 4498 "Failed to get default amount for resource %d [%s]\n", 4499 res_id, ecore_hw_get_resc_name(res_id)); 4500 return rc; 4501 } 4502 4503 #ifndef ASIC_ONLY 4504 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { 4505 *p_resc_num = dflt_resc_num; 4506 *p_resc_start = dflt_resc_start; 4507 goto out; 4508 } 4509 #endif 4510 4511 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id, 4512 &mcp_resp, p_resc_num, p_resc_start); 4513 if (rc != ECORE_SUCCESS) { 4514 DP_NOTICE(p_hwfn, true, 4515 "MFW response failure for an allocation request for" 4516 " resource %d [%s]\n", 4517 res_id, ecore_hw_get_resc_name(res_id)); 4518 return rc; 4519 } 4520 4521 /* Default driver values are applied in the following cases: 4522 * - The resource allocation MB command is not supported by the MFW 4523 * - There is an internal error in the MFW while processing the request 4524 * - The resource ID is unknown to the MFW 4525 */ 4526 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) { 4527 DP_INFO(p_hwfn, 4528 "Failed to receive allocation info for resource %d [%s]." 4529 " mcp_resp = 0x%x. Applying default values" 4530 " [%d,%d].\n", 4531 res_id, ecore_hw_get_resc_name(res_id), mcp_resp, 4532 dflt_resc_num, dflt_resc_start); 4533 4534 *p_resc_num = dflt_resc_num; 4535 *p_resc_start = dflt_resc_start; 4536 goto out; 4537 } 4538 4539 if ((*p_resc_num != dflt_resc_num || 4540 *p_resc_start != dflt_resc_start) && 4541 res_id != ECORE_SB) { 4542 DP_INFO(p_hwfn, 4543 "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n", 4544 res_id, ecore_hw_get_resc_name(res_id), *p_resc_num, 4545 *p_resc_start, dflt_resc_num, dflt_resc_start, 4546 drv_resc_alloc ? " - Applying default values" : ""); 4547 if (drv_resc_alloc) { 4548 *p_resc_num = dflt_resc_num; 4549 *p_resc_start = dflt_resc_start; 4550 } 4551 } 4552 out: 4553 return ECORE_SUCCESS; 4554 } 4555 4556 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, 4557 bool drv_resc_alloc) 4558 { 4559 enum _ecore_status_t rc; 4560 u8 res_id; 4561 4562 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) { 4563 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc); 4564 if (rc != ECORE_SUCCESS) 4565 return rc; 4566 } 4567 4568 return ECORE_SUCCESS; 4569 } 4570 4571 #define ECORE_NONUSED_PPFID_MASK_BB_4P_LO_PORTS 0xaa 4572 #define ECORE_NONUSED_PPFID_MASK_BB_4P_HI_PORTS 0x55 4573 #define ECORE_NONUSED_PPFID_MASK_AH_4P 0xf0 4574 4575 static enum _ecore_status_t ecore_hw_get_ppfid_bitmap(struct ecore_hwfn *p_hwfn, 4576 struct ecore_ptt *p_ptt) 4577 { 4578 u8 native_ppfid_idx = ECORE_PPFID_BY_PFID(p_hwfn), new_bitmap; 4579 struct ecore_dev *p_dev = p_hwfn->p_dev; 4580 enum _ecore_status_t rc; 4581 4582 rc = ecore_mcp_get_ppfid_bitmap(p_hwfn, p_ptt); 4583 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) 4584 return rc; 4585 else if (rc == ECORE_NOTIMPL) 4586 p_dev->ppfid_bitmap = 0x1 << native_ppfid_idx; 4587 4588 /* 4-ports mode has limitations that should be enforced: 4589 * - BB: the MFW can access only PPFIDs which their corresponding PFIDs 4590 * belong to this certain port. 4591 * - AH/E5: only 4 PPFIDs per port are available. 4592 */ 4593 if (ecore_device_num_ports(p_dev) == 4) { 4594 u8 mask; 4595 4596 if (ECORE_IS_BB(p_dev)) 4597 mask = MFW_PORT(p_hwfn) > 1 ? 4598 ECORE_NONUSED_PPFID_MASK_BB_4P_HI_PORTS : 4599 ECORE_NONUSED_PPFID_MASK_BB_4P_LO_PORTS; 4600 else 4601 mask = ECORE_NONUSED_PPFID_MASK_AH_4P; 4602 4603 if (p_dev->ppfid_bitmap & mask) { 4604 new_bitmap = p_dev->ppfid_bitmap & ~mask; 4605 DP_INFO(p_hwfn, 4606 "Fix the PPFID bitmap for 4-ports mode: 0x%hhx -> 0x%hhx\n", 4607 p_dev->ppfid_bitmap, new_bitmap); 4608 p_dev->ppfid_bitmap = new_bitmap; 4609 } 4610 } 4611 4612 /* The native PPFID is expected to be part of the allocated bitmap */ 4613 if (!(p_dev->ppfid_bitmap & (0x1 << native_ppfid_idx))) { 4614 new_bitmap = 0x1 << native_ppfid_idx; 4615 DP_INFO(p_hwfn, 4616 "Fix the PPFID bitmap to inculde the native PPFID: %hhd -> 0x%hhx\n", 4617 p_dev->ppfid_bitmap, new_bitmap); 4618 p_dev->ppfid_bitmap = new_bitmap; 4619 } 4620 4621 return ECORE_SUCCESS; 4622 } 4623 4624 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn, 4625 struct ecore_ptt *p_ptt, 4626 bool drv_resc_alloc) 4627 { 4628 struct ecore_resc_unlock_params resc_unlock_params; 4629 struct ecore_resc_lock_params resc_lock_params; 4630 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev); 4631 u8 res_id; 4632 enum _ecore_status_t rc; 4633 #ifndef ASIC_ONLY 4634 u32 *resc_start = p_hwfn->hw_info.resc_start; 4635 u32 *resc_num = p_hwfn->hw_info.resc_num; 4636 /* For AH, an equal share of the ILT lines between the maximal number of 4637 * PFs is not enough for RoCE. This would be solved by the future 4638 * resource allocation scheme, but isn't currently present for 4639 * FPGA/emulation. For now we keep a number that is sufficient for RoCE 4640 * to work - the BB number of ILT lines divided by its max PFs number. 4641 */ 4642 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB; 4643 #endif 4644 4645 /* Setting the max values of the soft resources and the following 4646 * resources allocation queries should be atomic. Since several PFs can 4647 * run in parallel - a resource lock is needed. 4648 * If either the resource lock or resource set value commands are not 4649 * supported - skip the max values setting, release the lock if 4650 * needed, and proceed to the queries. Other failures, including a 4651 * failure to acquire the lock, will cause this function to fail. 4652 * Old drivers that don't acquire the lock can run in parallel, and 4653 * their allocation values won't be affected by the updated max values. 4654 */ 4655 ecore_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params, 4656 ECORE_RESC_LOCK_RESC_ALLOC, false); 4657 4658 rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params); 4659 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) { 4660 return rc; 4661 } else if (rc == ECORE_NOTIMPL) { 4662 DP_INFO(p_hwfn, 4663 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n"); 4664 } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) { 4665 DP_NOTICE(p_hwfn, false, 4666 "Failed to acquire the resource lock for the resource allocation commands\n"); 4667 rc = ECORE_BUSY; 4668 goto unlock_and_exit; 4669 } else { 4670 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt); 4671 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) { 4672 DP_NOTICE(p_hwfn, false, 4673 "Failed to set the max values of the soft resources\n"); 4674 goto unlock_and_exit; 4675 } else if (rc == ECORE_NOTIMPL) { 4676 DP_INFO(p_hwfn, 4677 "Skip the max values setting of the soft resources since it is not supported by the MFW\n"); 4678 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt, 4679 &resc_unlock_params); 4680 if (rc != ECORE_SUCCESS) 4681 DP_INFO(p_hwfn, 4682 "Failed to release the resource lock for the resource allocation commands\n"); 4683 } 4684 } 4685 4686 rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc); 4687 if (rc != ECORE_SUCCESS) 4688 goto unlock_and_exit; 4689 4690 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) { 4691 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt, 4692 &resc_unlock_params); 4693 if (rc != ECORE_SUCCESS) 4694 DP_INFO(p_hwfn, 4695 "Failed to release the resource lock for the resource allocation commands\n"); 4696 } 4697 4698 /* PPFID bitmap */ 4699 if (IS_LEAD_HWFN(p_hwfn)) { 4700 rc = ecore_hw_get_ppfid_bitmap(p_hwfn, p_ptt); 4701 if (rc != ECORE_SUCCESS) 4702 return rc; 4703 } 4704 4705 #ifndef ASIC_ONLY 4706 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { 4707 /* Reduced build contains less PQs */ 4708 if (!(p_hwfn->p_dev->b_is_emul_full)) { 4709 resc_num[ECORE_PQ] = 32; 4710 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] * 4711 p_hwfn->enabled_func_idx; 4712 } 4713 4714 /* For AH emulation, since we have a possible maximal number of 4715 * 16 enabled PFs, in case there are not enough ILT lines - 4716 * allocate only first PF as RoCE and have all the other ETH 4717 * only with less ILT lines. 4718 */ 4719 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full) 4720 resc_num[ECORE_ILT] = OSAL_MAX_T(u32, 4721 resc_num[ECORE_ILT], 4722 roce_min_ilt_lines); 4723 } 4724 4725 /* Correct the common ILT calculation if PF0 has more */ 4726 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) && 4727 p_hwfn->p_dev->b_is_emul_full && 4728 p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines) 4729 resc_start[ECORE_ILT] += roce_min_ilt_lines - 4730 resc_num[ECORE_ILT]; 4731 #endif 4732 4733 /* Sanity for ILT */ 4734 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) || 4735 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) { 4736 DP_NOTICE(p_hwfn, true, 4737 "Can't assign ILT pages [%08x,...,%08x]\n", 4738 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn, 4739 ECORE_ILT) - 4740 1); 4741 return ECORE_INVAL; 4742 } 4743 4744 /* This will also learn the number of SBs from MFW */ 4745 if (ecore_int_igu_reset_cam(p_hwfn, p_ptt)) 4746 return ECORE_INVAL; 4747 4748 ecore_hw_set_feat(p_hwfn); 4749 4750 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, 4751 "The numbers for each resource are:\n"); 4752 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) 4753 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n", 4754 ecore_hw_get_resc_name(res_id), 4755 RESC_NUM(p_hwfn, res_id), 4756 RESC_START(p_hwfn, res_id)); 4757 4758 return ECORE_SUCCESS; 4759 4760 unlock_and_exit: 4761 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) 4762 ecore_mcp_resc_unlock(p_hwfn, p_ptt, 4763 &resc_unlock_params); 4764 return rc; 4765 } 4766 4767 static enum _ecore_status_t 4768 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn, 4769 struct ecore_ptt *p_ptt, 4770 struct ecore_hw_prepare_params *p_params) 4771 { 4772 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode; 4773 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities; 4774 struct ecore_mcp_link_capabilities *p_caps; 4775 struct ecore_mcp_link_params *link; 4776 enum _ecore_status_t rc; 4777 4778 /* Read global nvm_cfg address */ 4779 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 4780 4781 /* Verify MCP has initialized it */ 4782 if (!nvm_cfg_addr) { 4783 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n"); 4784 if (p_params->b_relaxed_probe) 4785 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM; 4786 return ECORE_INVAL; 4787 } 4788 4789 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */ 4790 4791 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 4792 4793 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 4794 OFFSETOF(struct nvm_cfg1, glob) + 4795 OFFSETOF(struct nvm_cfg1_glob, core_cfg); 4796 4797 core_cfg = ecore_rd(p_hwfn, p_ptt, addr); 4798 4799 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >> 4800 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) { 4801 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G: 4802 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G; 4803 break; 4804 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G: 4805 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G; 4806 break; 4807 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G: 4808 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G; 4809 break; 4810 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F: 4811 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F; 4812 break; 4813 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E: 4814 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E; 4815 break; 4816 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G: 4817 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G; 4818 break; 4819 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G: 4820 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G; 4821 break; 4822 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G: 4823 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G; 4824 break; 4825 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G: 4826 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G; 4827 break; 4828 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G: 4829 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G; 4830 break; 4831 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G: 4832 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G; 4833 break; 4834 default: 4835 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n", 4836 core_cfg); 4837 break; 4838 } 4839 4840 /* Read DCBX configuration */ 4841 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 4842 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 4843 dcbx_mode = ecore_rd(p_hwfn, p_ptt, 4844 port_cfg_addr + 4845 OFFSETOF(struct nvm_cfg1_port, generic_cont0)); 4846 dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK) 4847 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET; 4848 switch (dcbx_mode) { 4849 case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC: 4850 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC; 4851 break; 4852 case NVM_CFG1_PORT_DCBX_MODE_CEE: 4853 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE; 4854 break; 4855 case NVM_CFG1_PORT_DCBX_MODE_IEEE: 4856 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE; 4857 break; 4858 default: 4859 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED; 4860 } 4861 4862 /* Read default link configuration */ 4863 link = &p_hwfn->mcp_info->link_input; 4864 p_caps = &p_hwfn->mcp_info->link_capabilities; 4865 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 4866 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 4867 link_temp = ecore_rd(p_hwfn, p_ptt, 4868 port_cfg_addr + 4869 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask)); 4870 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK; 4871 link->speed.advertised_speeds = link_temp; 4872 p_caps->speed_capabilities = link->speed.advertised_speeds; 4873 4874 link_temp = ecore_rd(p_hwfn, p_ptt, 4875 port_cfg_addr + 4876 OFFSETOF(struct nvm_cfg1_port, link_settings)); 4877 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >> 4878 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) { 4879 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG: 4880 link->speed.autoneg = true; 4881 break; 4882 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G: 4883 link->speed.forced_speed = 1000; 4884 break; 4885 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G: 4886 link->speed.forced_speed = 10000; 4887 break; 4888 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G: 4889 link->speed.forced_speed = 25000; 4890 break; 4891 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G: 4892 link->speed.forced_speed = 40000; 4893 break; 4894 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G: 4895 link->speed.forced_speed = 50000; 4896 break; 4897 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G: 4898 link->speed.forced_speed = 100000; 4899 break; 4900 default: 4901 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp); 4902 } 4903 4904 p_caps->default_speed = link->speed.forced_speed; 4905 p_caps->default_speed_autoneg = link->speed.autoneg; 4906 4907 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK; 4908 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET; 4909 link->pause.autoneg = !!(link_temp & 4910 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG); 4911 link->pause.forced_rx = !!(link_temp & 4912 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX); 4913 link->pause.forced_tx = !!(link_temp & 4914 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX); 4915 link->loopback_mode = 0; 4916 4917 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) { 4918 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr + 4919 OFFSETOF(struct nvm_cfg1_port, ext_phy)); 4920 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK; 4921 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET; 4922 p_caps->default_eee = ECORE_MCP_EEE_ENABLED; 4923 link->eee.enable = true; 4924 switch (link_temp) { 4925 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED: 4926 p_caps->default_eee = ECORE_MCP_EEE_DISABLED; 4927 link->eee.enable = false; 4928 break; 4929 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED: 4930 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME; 4931 break; 4932 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE: 4933 p_caps->eee_lpi_timer = 4934 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME; 4935 break; 4936 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY: 4937 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME; 4938 break; 4939 } 4940 4941 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer; 4942 link->eee.tx_lpi_enable = link->eee.enable; 4943 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV; 4944 } else { 4945 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED; 4946 } 4947 4948 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 4949 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n EEE: %02x [%08x usec]", 4950 link->speed.forced_speed, link->speed.advertised_speeds, 4951 link->speed.autoneg, link->pause.autoneg, 4952 p_caps->default_eee, p_caps->eee_lpi_timer); 4953 4954 /* Read Multi-function information from shmem */ 4955 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 4956 OFFSETOF(struct nvm_cfg1, glob) + 4957 OFFSETOF(struct nvm_cfg1_glob, generic_cont0); 4958 4959 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr); 4960 4961 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >> 4962 NVM_CFG1_GLOB_MF_MODE_OFFSET; 4963 4964 switch (mf_mode) { 4965 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED: 4966 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS; 4967 break; 4968 case NVM_CFG1_GLOB_MF_MODE_UFP: 4969 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS | 4970 1 << ECORE_MF_UFP_SPECIFIC | 4971 1 << ECORE_MF_8021Q_TAGGING; 4972 break; 4973 case NVM_CFG1_GLOB_MF_MODE_BD: 4974 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS | 4975 1 << ECORE_MF_LLH_PROTO_CLSS | 4976 1 << ECORE_MF_8021AD_TAGGING | 4977 1 << ECORE_MF_FIP_SPECIAL; 4978 break; 4979 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0: 4980 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS | 4981 1 << ECORE_MF_LLH_PROTO_CLSS | 4982 1 << ECORE_MF_LL2_NON_UNICAST | 4983 1 << ECORE_MF_INTER_PF_SWITCH | 4984 1 << ECORE_MF_DISABLE_ARFS; 4985 break; 4986 case NVM_CFG1_GLOB_MF_MODE_DEFAULT: 4987 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS | 4988 1 << ECORE_MF_LLH_PROTO_CLSS | 4989 1 << ECORE_MF_LL2_NON_UNICAST; 4990 if (ECORE_IS_BB(p_hwfn->p_dev)) 4991 p_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF; 4992 break; 4993 } 4994 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n", 4995 p_hwfn->p_dev->mf_bits); 4996 4997 if (ECORE_IS_CMT(p_hwfn->p_dev)) 4998 p_hwfn->p_dev->mf_bits |= (1 << ECORE_MF_DISABLE_ARFS); 4999 5000 /* It's funny since we have another switch, but it's easier 5001 * to throw this away in linux this way. Long term, it might be 5002 * better to have have getters for needed ECORE_MF_* fields, 5003 * convert client code and eliminate this. 5004 */ 5005 switch (mf_mode) { 5006 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED: 5007 case NVM_CFG1_GLOB_MF_MODE_BD: 5008 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN; 5009 break; 5010 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0: 5011 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR; 5012 break; 5013 case NVM_CFG1_GLOB_MF_MODE_DEFAULT: 5014 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT; 5015 break; 5016 case NVM_CFG1_GLOB_MF_MODE_UFP: 5017 p_hwfn->p_dev->mf_mode = ECORE_MF_UFP; 5018 break; 5019 } 5020 5021 /* Read Multi-function information from shmem */ 5022 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 5023 OFFSETOF(struct nvm_cfg1, glob) + 5024 OFFSETOF(struct nvm_cfg1_glob, device_capabilities); 5025 5026 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr); 5027 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET) 5028 OSAL_SET_BIT(ECORE_DEV_CAP_ETH, 5029 &p_hwfn->hw_info.device_capabilities); 5030 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE) 5031 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE, 5032 &p_hwfn->hw_info.device_capabilities); 5033 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI) 5034 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI, 5035 &p_hwfn->hw_info.device_capabilities); 5036 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE) 5037 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE, 5038 &p_hwfn->hw_info.device_capabilities); 5039 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP) 5040 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP, 5041 &p_hwfn->hw_info.device_capabilities); 5042 5043 rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt); 5044 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) { 5045 rc = ECORE_SUCCESS; 5046 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP; 5047 } 5048 5049 return rc; 5050 } 5051 5052 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn, 5053 struct ecore_ptt *p_ptt) 5054 { 5055 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id; 5056 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask; 5057 struct ecore_dev *p_dev = p_hwfn->p_dev; 5058 5059 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB; 5060 5061 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values 5062 * in the other bits are selected. 5063 * Bits 1-15 are for functions 1-15, respectively, and their value is 5064 * '0' only for enabled functions (function 0 always exists and 5065 * enabled). 5066 * In case of CMT in BB, only the "even" functions are enabled, and thus 5067 * the number of functions for both hwfns is learnt from the same bits. 5068 */ 5069 if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) { 5070 reg_function_hide = ecore_rd(p_hwfn, p_ptt, 5071 MISCS_REG_FUNCTION_HIDE_BB_K2); 5072 } else { /* E5 */ 5073 reg_function_hide = 0; 5074 } 5075 5076 if (reg_function_hide & 0x1) { 5077 if (ECORE_IS_BB(p_dev)) { 5078 if (ECORE_PATH_ID(p_hwfn) && !ECORE_IS_CMT(p_dev)) { 5079 num_funcs = 0; 5080 eng_mask = 0xaaaa; 5081 } else { 5082 num_funcs = 1; 5083 eng_mask = 0x5554; 5084 } 5085 } else { 5086 num_funcs = 1; 5087 eng_mask = 0xfffe; 5088 } 5089 5090 /* Get the number of the enabled functions on the engine */ 5091 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask; 5092 while (tmp) { 5093 if (tmp & 0x1) 5094 num_funcs++; 5095 tmp >>= 0x1; 5096 } 5097 5098 /* Get the PF index within the enabled functions */ 5099 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1; 5100 tmp = reg_function_hide & eng_mask & low_pfs_mask; 5101 while (tmp) { 5102 if (tmp & 0x1) 5103 enabled_func_idx--; 5104 tmp >>= 0x1; 5105 } 5106 } 5107 5108 p_hwfn->num_funcs_on_engine = num_funcs; 5109 p_hwfn->enabled_func_idx = enabled_func_idx; 5110 5111 #ifndef ASIC_ONLY 5112 if (CHIP_REV_IS_FPGA(p_dev)) { 5113 DP_NOTICE(p_hwfn, false, 5114 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n"); 5115 p_hwfn->num_funcs_on_engine = 4; 5116 } 5117 #endif 5118 5119 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, 5120 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n", 5121 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id, 5122 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine); 5123 } 5124 5125 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn, 5126 struct ecore_ptt *p_ptt) 5127 { 5128 struct ecore_dev *p_dev = p_hwfn->p_dev; 5129 u32 port_mode; 5130 5131 #ifndef ASIC_ONLY 5132 /* Read the port mode */ 5133 if (CHIP_REV_IS_FPGA(p_dev)) 5134 port_mode = 4; 5135 else if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_CMT(p_dev)) 5136 /* In CMT on emulation, assume 1 port */ 5137 port_mode = 1; 5138 else 5139 #endif 5140 port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB); 5141 5142 if (port_mode < 3) { 5143 p_dev->num_ports_in_engine = 1; 5144 } else if (port_mode <= 5) { 5145 p_dev->num_ports_in_engine = 2; 5146 } else { 5147 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n", 5148 p_dev->num_ports_in_engine); 5149 5150 /* Default num_ports_in_engine to something */ 5151 p_dev->num_ports_in_engine = 1; 5152 } 5153 } 5154 5155 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn, 5156 struct ecore_ptt *p_ptt) 5157 { 5158 struct ecore_dev *p_dev = p_hwfn->p_dev; 5159 u32 port; 5160 int i; 5161 5162 p_dev->num_ports_in_engine = 0; 5163 5164 #ifndef ASIC_ONLY 5165 if (CHIP_REV_IS_EMUL(p_dev)) { 5166 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED); 5167 switch ((port & 0xf000) >> 12) { 5168 case 1: 5169 p_dev->num_ports_in_engine = 1; 5170 break; 5171 case 3: 5172 p_dev->num_ports_in_engine = 2; 5173 break; 5174 case 0xf: 5175 p_dev->num_ports_in_engine = 4; 5176 break; 5177 default: 5178 DP_NOTICE(p_hwfn, false, 5179 "Unknown port mode in ECO_RESERVED %08x\n", 5180 port); 5181 } 5182 } else 5183 #endif 5184 for (i = 0; i < MAX_NUM_PORTS_K2; i++) { 5185 port = ecore_rd(p_hwfn, p_ptt, 5186 CNIG_REG_NIG_PORT0_CONF_K2 + 5187 (i * 4)); 5188 if (port & 1) 5189 p_dev->num_ports_in_engine++; 5190 } 5191 5192 if (!p_dev->num_ports_in_engine) { 5193 DP_NOTICE(p_hwfn, true, "All NIG ports are inactive\n"); 5194 5195 /* Default num_ports_in_engine to something */ 5196 p_dev->num_ports_in_engine = 1; 5197 } 5198 } 5199 5200 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn, 5201 struct ecore_ptt *p_ptt) 5202 { 5203 struct ecore_dev *p_dev = p_hwfn->p_dev; 5204 5205 /* Determine the number of ports per engine */ 5206 if (ECORE_IS_BB(p_dev)) 5207 ecore_hw_info_port_num_bb(p_hwfn, p_ptt); 5208 else 5209 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt); 5210 5211 /* Get the total number of ports of the device */ 5212 if (ECORE_IS_CMT(p_dev)) { 5213 /* In CMT there is always only one port */ 5214 p_dev->num_ports = 1; 5215 #ifndef ASIC_ONLY 5216 } else if (CHIP_REV_IS_EMUL(p_dev) || CHIP_REV_IS_TEDIBEAR(p_dev)) { 5217 p_dev->num_ports = p_dev->num_ports_in_engine * 5218 ecore_device_num_engines(p_dev); 5219 #endif 5220 } else { 5221 u32 addr, global_offsize, global_addr; 5222 5223 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 5224 PUBLIC_GLOBAL); 5225 global_offsize = ecore_rd(p_hwfn, p_ptt, addr); 5226 global_addr = SECTION_ADDR(global_offsize, 0); 5227 addr = global_addr + OFFSETOF(struct public_global, max_ports); 5228 p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr); 5229 } 5230 } 5231 5232 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn, 5233 struct ecore_ptt *p_ptt) 5234 { 5235 struct ecore_mcp_link_capabilities *p_caps; 5236 u32 eee_status; 5237 5238 p_caps = &p_hwfn->mcp_info->link_capabilities; 5239 if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED) 5240 return; 5241 5242 p_caps->eee_speed_caps = 0; 5243 eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 5244 OFFSETOF(struct public_port, eee_status)); 5245 eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >> 5246 EEE_SUPPORTED_SPEED_OFFSET; 5247 if (eee_status & EEE_1G_SUPPORTED) 5248 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV; 5249 if (eee_status & EEE_10G_ADV) 5250 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV; 5251 } 5252 5253 static enum _ecore_status_t 5254 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 5255 enum ecore_pci_personality personality, 5256 struct ecore_hw_prepare_params *p_params) 5257 { 5258 bool drv_resc_alloc = p_params->drv_resc_alloc; 5259 enum _ecore_status_t rc; 5260 5261 if (IS_ECORE_PACING(p_hwfn)) { 5262 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_IOV, 5263 "Skipping IOV as packet pacing is requested\n"); 5264 } 5265 5266 /* Since all information is common, only first hwfns should do this */ 5267 if (IS_LEAD_HWFN(p_hwfn) && !IS_ECORE_PACING(p_hwfn)) { 5268 rc = ecore_iov_hw_info(p_hwfn); 5269 if (rc != ECORE_SUCCESS) { 5270 if (p_params->b_relaxed_probe) 5271 p_params->p_relaxed_res = 5272 ECORE_HW_PREPARE_BAD_IOV; 5273 else 5274 return rc; 5275 } 5276 } 5277 5278 if (IS_LEAD_HWFN(p_hwfn)) 5279 ecore_hw_info_port_num(p_hwfn, p_ptt); 5280 5281 ecore_mcp_get_capabilities(p_hwfn, p_ptt); 5282 5283 #ifndef ASIC_ONLY 5284 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) { 5285 #endif 5286 rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params); 5287 if (rc != ECORE_SUCCESS) 5288 return rc; 5289 #ifndef ASIC_ONLY 5290 } 5291 #endif 5292 5293 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt); 5294 if (rc != ECORE_SUCCESS) { 5295 if (p_params->b_relaxed_probe) 5296 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU; 5297 else 5298 return rc; 5299 } 5300 5301 #ifndef ASIC_ONLY 5302 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) { 5303 #endif 5304 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, 5305 p_hwfn->mcp_info->func_info.mac, ETH_ALEN); 5306 #ifndef ASIC_ONLY 5307 } else { 5308 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 }; 5309 5310 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN); 5311 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id; 5312 } 5313 #endif 5314 5315 if (ecore_mcp_is_init(p_hwfn)) { 5316 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET) 5317 p_hwfn->hw_info.ovlan = 5318 p_hwfn->mcp_info->func_info.ovlan; 5319 5320 ecore_mcp_cmd_port_init(p_hwfn, p_ptt); 5321 5322 ecore_mcp_get_eee_caps(p_hwfn, p_ptt); 5323 5324 ecore_mcp_read_ufp_config(p_hwfn, p_ptt); 5325 } 5326 5327 if (personality != ECORE_PCI_DEFAULT) { 5328 p_hwfn->hw_info.personality = personality; 5329 } else if (ecore_mcp_is_init(p_hwfn)) { 5330 enum ecore_pci_personality protocol; 5331 5332 protocol = p_hwfn->mcp_info->func_info.protocol; 5333 p_hwfn->hw_info.personality = protocol; 5334 } 5335 5336 #ifndef ASIC_ONLY 5337 /* To overcome ILT lack for emulation, until at least until we'll have 5338 * a definite answer from system about it, allow only PF0 to be RoCE. 5339 */ 5340 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) { 5341 if (!p_hwfn->rel_pf_id) 5342 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE; 5343 else 5344 p_hwfn->hw_info.personality = ECORE_PCI_ETH; 5345 } 5346 #endif 5347 5348 /* although in BB some constellations may support more than 4 tcs, 5349 * that can result in performance penalty in some cases. 4 5350 * represents a good tradeoff between performance and flexibility. 5351 */ 5352 if (IS_ECORE_PACING(p_hwfn)) 5353 p_hwfn->hw_info.num_hw_tc = 1; 5354 else 5355 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2; 5356 5357 /* start out with a single active tc. This can be increased either 5358 * by dcbx negotiation or by upper layer driver 5359 */ 5360 p_hwfn->hw_info.num_active_tc = 1; 5361 5362 ecore_get_num_funcs(p_hwfn, p_ptt); 5363 5364 if (ecore_mcp_is_init(p_hwfn)) 5365 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu; 5366 5367 /* In case of forcing the driver's default resource allocation, calling 5368 * ecore_hw_get_resc() should come after initializing the personality 5369 * and after getting the number of functions, since the calculation of 5370 * the resources/features depends on them. 5371 * This order is not harmful if not forcing. 5372 */ 5373 rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc); 5374 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) { 5375 rc = ECORE_SUCCESS; 5376 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP; 5377 } 5378 5379 return rc; 5380 } 5381 5382 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn, 5383 struct ecore_ptt *p_ptt) 5384 { 5385 struct ecore_dev *p_dev = p_hwfn->p_dev; 5386 u16 device_id_mask; 5387 u32 tmp; 5388 5389 /* Read Vendor Id / Device Id */ 5390 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET, 5391 &p_dev->vendor_id); 5392 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET, 5393 &p_dev->device_id); 5394 5395 /* Determine type */ 5396 device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK; 5397 switch (device_id_mask) { 5398 case ECORE_DEV_ID_MASK_BB: 5399 p_dev->type = ECORE_DEV_TYPE_BB; 5400 break; 5401 case ECORE_DEV_ID_MASK_AH: 5402 p_dev->type = ECORE_DEV_TYPE_AH; 5403 break; 5404 default: 5405 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n", 5406 p_dev->device_id); 5407 return ECORE_ABORTED; 5408 } 5409 5410 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM); 5411 p_dev->chip_num = (u16)GET_FIELD(tmp, CHIP_NUM); 5412 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV); 5413 p_dev->chip_rev = (u8)GET_FIELD(tmp, CHIP_REV); 5414 5415 /* Learn number of HW-functions */ 5416 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR); 5417 5418 if (tmp & (1 << p_hwfn->rel_pf_id)) { 5419 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n"); 5420 p_dev->num_hwfns = 2; 5421 } else { 5422 p_dev->num_hwfns = 1; 5423 } 5424 5425 #ifndef ASIC_ONLY 5426 if (CHIP_REV_IS_EMUL(p_dev)) { 5427 /* For some reason we have problems with this register 5428 * in B0 emulation; Simply assume no CMT 5429 */ 5430 DP_NOTICE(p_dev->hwfns, false, 5431 "device on emul - assume no CMT\n"); 5432 p_dev->num_hwfns = 1; 5433 } 5434 #endif 5435 5436 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_TEST_REG); 5437 p_dev->chip_bond_id = (u8)GET_FIELD(tmp, CHIP_BOND_ID); 5438 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL); 5439 p_dev->chip_metal = (u8)GET_FIELD(tmp, CHIP_METAL); 5440 5441 DP_INFO(p_dev->hwfns, 5442 "Chip details - %s %c%d, Num: %04x Rev: %02x Bond id: %02x Metal: %02x\n", 5443 ECORE_IS_BB(p_dev) ? "BB" : "AH", 5444 'A' + p_dev->chip_rev, (int)p_dev->chip_metal, 5445 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id, 5446 p_dev->chip_metal); 5447 5448 if (ECORE_IS_BB_A0(p_dev)) { 5449 DP_NOTICE(p_dev->hwfns, false, 5450 "The chip type/rev (BB A0) is not supported!\n"); 5451 return ECORE_ABORTED; 5452 } 5453 #ifndef ASIC_ONLY 5454 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev)) 5455 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1); 5456 5457 if (CHIP_REV_IS_EMUL(p_dev)) { 5458 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED); 5459 if (tmp & (1 << 29)) { 5460 DP_NOTICE(p_hwfn, false, 5461 "Emulation: Running on a FULL build\n"); 5462 p_dev->b_is_emul_full = true; 5463 } else { 5464 DP_NOTICE(p_hwfn, false, 5465 "Emulation: Running on a REDUCED build\n"); 5466 } 5467 } 5468 #endif 5469 5470 return ECORE_SUCCESS; 5471 } 5472 5473 #ifndef LINUX_REMOVE 5474 void ecore_prepare_hibernate(struct ecore_dev *p_dev) 5475 { 5476 int j; 5477 5478 if (IS_VF(p_dev)) 5479 return; 5480 5481 for_each_hwfn(p_dev, j) { 5482 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j]; 5483 5484 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, 5485 "Mark hw/fw uninitialized\n"); 5486 5487 p_hwfn->hw_init_done = false; 5488 5489 ecore_ptt_invalidate(p_hwfn); 5490 } 5491 } 5492 #endif 5493 5494 static enum _ecore_status_t 5495 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, void OSAL_IOMEM *p_regview, 5496 void OSAL_IOMEM *p_doorbells, u64 db_phys_addr, 5497 struct ecore_hw_prepare_params *p_params) 5498 { 5499 struct ecore_mdump_retain_data mdump_retain; 5500 struct ecore_dev *p_dev = p_hwfn->p_dev; 5501 struct ecore_mdump_info mdump_info; 5502 enum _ecore_status_t rc = ECORE_SUCCESS; 5503 5504 /* Split PCI bars evenly between hwfns */ 5505 p_hwfn->regview = p_regview; 5506 p_hwfn->doorbells = p_doorbells; 5507 p_hwfn->db_phys_addr = db_phys_addr; 5508 5509 if (IS_VF(p_dev)) 5510 return ecore_vf_hw_prepare(p_hwfn); 5511 5512 /* Validate that chip access is feasible */ 5513 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { 5514 DP_ERR(p_hwfn, 5515 "Reading the ME register returns all Fs; Preventing further chip access\n"); 5516 if (p_params->b_relaxed_probe) 5517 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME; 5518 return ECORE_INVAL; 5519 } 5520 5521 get_function_id(p_hwfn); 5522 5523 /* Allocate PTT pool */ 5524 rc = ecore_ptt_pool_alloc(p_hwfn); 5525 if (rc) { 5526 DP_NOTICE(p_hwfn, false, "Failed to prepare hwfn's hw\n"); 5527 if (p_params->b_relaxed_probe) 5528 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM; 5529 goto err0; 5530 } 5531 5532 /* Allocate the main PTT */ 5533 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN); 5534 5535 /* First hwfn learns basic information, e.g., number of hwfns */ 5536 if (!p_hwfn->my_id) { 5537 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt); 5538 if (rc != ECORE_SUCCESS) { 5539 if (p_params->b_relaxed_probe) 5540 p_params->p_relaxed_res = 5541 ECORE_HW_PREPARE_FAILED_DEV; 5542 goto err1; 5543 } 5544 } 5545 5546 ecore_hw_hwfn_prepare(p_hwfn); 5547 5548 /* Initialize MCP structure */ 5549 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt); 5550 if (rc) { 5551 DP_NOTICE(p_hwfn, false, "Failed initializing mcp command\n"); 5552 if (p_params->b_relaxed_probe) 5553 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM; 5554 goto err1; 5555 } 5556 5557 /* Read the device configuration information from the HW and SHMEM */ 5558 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, 5559 p_params->personality, p_params); 5560 if (rc) { 5561 DP_NOTICE(p_hwfn, false, "Failed to get HW information\n"); 5562 goto err2; 5563 } 5564 5565 /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is 5566 * called, since among others it sets the ports number in an engine. 5567 */ 5568 if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) && 5569 !p_dev->recov_in_prog) { 5570 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt); 5571 if (rc != ECORE_SUCCESS) 5572 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n"); 5573 5574 /* Workaround for MFW issue where PF FLR does not cleanup 5575 * IGU block 5576 */ 5577 if (!(p_hwfn->mcp_info->capabilities & 5578 FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP)) 5579 ecore_pf_flr_igu_cleanup(p_hwfn); 5580 } 5581 5582 /* Check if mdump logs/data are present and update the epoch value */ 5583 if (IS_LEAD_HWFN(p_hwfn)) { 5584 #ifndef ASIC_ONLY 5585 if (!CHIP_REV_IS_EMUL(p_dev)) { 5586 #endif 5587 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt, 5588 &mdump_info); 5589 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs) 5590 DP_NOTICE(p_hwfn, false, 5591 "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n"); 5592 5593 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt, 5594 &mdump_retain); 5595 if (rc == ECORE_SUCCESS && mdump_retain.valid) 5596 DP_NOTICE(p_hwfn, false, 5597 "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n", 5598 mdump_retain.epoch, mdump_retain.pf, 5599 mdump_retain.status); 5600 5601 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt, 5602 p_params->epoch); 5603 #ifndef ASIC_ONLY 5604 } 5605 #endif 5606 } 5607 5608 /* Allocate the init RT array and initialize the init-ops engine */ 5609 rc = ecore_init_alloc(p_hwfn); 5610 if (rc) { 5611 DP_NOTICE(p_hwfn, false, "Failed to allocate the init array\n"); 5612 if (p_params->b_relaxed_probe) 5613 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM; 5614 goto err2; 5615 } 5616 #ifndef ASIC_ONLY 5617 if (CHIP_REV_IS_FPGA(p_dev)) { 5618 DP_NOTICE(p_hwfn, false, 5619 "FPGA: workaround; Prevent DMAE parities\n"); 5620 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2, 5621 7); 5622 5623 DP_NOTICE(p_hwfn, false, 5624 "FPGA: workaround: Set VF bar0 size\n"); 5625 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 5626 PGLUE_B_REG_VF_BAR0_SIZE_K2, 4); 5627 } 5628 #endif 5629 5630 return rc; 5631 err2: 5632 if (IS_LEAD_HWFN(p_hwfn)) 5633 ecore_iov_free_hw_info(p_dev); 5634 ecore_mcp_free(p_hwfn); 5635 err1: 5636 ecore_hw_hwfn_free(p_hwfn); 5637 err0: 5638 return rc; 5639 } 5640 5641 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev, 5642 struct ecore_hw_prepare_params *p_params) 5643 { 5644 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev); 5645 enum _ecore_status_t rc; 5646 5647 p_dev->chk_reg_fifo = p_params->chk_reg_fifo; 5648 p_dev->allow_mdump = p_params->allow_mdump; 5649 p_hwfn->b_en_pacing = p_params->b_en_pacing; 5650 p_dev->b_is_target = p_params->b_is_target; 5651 5652 if (p_params->b_relaxed_probe) 5653 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS; 5654 5655 /* Store the precompiled init data ptrs */ 5656 if (IS_PF(p_dev)) 5657 ecore_init_iro_array(p_dev); 5658 5659 /* Initialize the first hwfn - will learn number of hwfns */ 5660 rc = ecore_hw_prepare_single(p_hwfn, p_dev->regview, 5661 p_dev->doorbells, p_dev->db_phys_addr, 5662 p_params); 5663 if (rc != ECORE_SUCCESS) 5664 return rc; 5665 5666 p_params->personality = p_hwfn->hw_info.personality; 5667 5668 /* initilalize 2nd hwfn if necessary */ 5669 if (ECORE_IS_CMT(p_dev)) { 5670 void OSAL_IOMEM *p_regview, *p_doorbell; 5671 u8 OSAL_IOMEM *addr; 5672 u64 db_phys_addr; 5673 u32 offset; 5674 5675 /* adjust bar offset for second engine */ 5676 offset = ecore_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt, 5677 BAR_ID_0) / 2; 5678 addr = (u8 OSAL_IOMEM *)p_dev->regview + offset; 5679 p_regview = (void OSAL_IOMEM *)addr; 5680 5681 offset = ecore_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt, 5682 BAR_ID_1) / 2; 5683 addr = (u8 OSAL_IOMEM *)p_dev->doorbells + offset; 5684 p_doorbell = (void OSAL_IOMEM *)addr; 5685 db_phys_addr = p_dev->db_phys_addr + offset; 5686 5687 p_dev->hwfns[1].b_en_pacing = p_params->b_en_pacing; 5688 /* prepare second hw function */ 5689 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview, 5690 p_doorbell, db_phys_addr, 5691 p_params); 5692 5693 /* in case of error, need to free the previously 5694 * initiliazed hwfn 0. 5695 */ 5696 if (rc != ECORE_SUCCESS) { 5697 if (p_params->b_relaxed_probe) 5698 p_params->p_relaxed_res = 5699 ECORE_HW_PREPARE_FAILED_ENG2; 5700 5701 if (IS_PF(p_dev)) { 5702 ecore_init_free(p_hwfn); 5703 ecore_mcp_free(p_hwfn); 5704 ecore_hw_hwfn_free(p_hwfn); 5705 } else { 5706 DP_NOTICE(p_dev, false, "What do we need to free when VF hwfn1 init fails\n"); 5707 } 5708 return rc; 5709 } 5710 } 5711 5712 return rc; 5713 } 5714 5715 void ecore_hw_remove(struct ecore_dev *p_dev) 5716 { 5717 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev); 5718 int i; 5719 5720 if (IS_PF(p_dev)) 5721 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt, 5722 ECORE_OV_DRIVER_STATE_NOT_LOADED); 5723 5724 for_each_hwfn(p_dev, i) { 5725 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 5726 5727 if (IS_VF(p_dev)) { 5728 ecore_vf_pf_release(p_hwfn); 5729 continue; 5730 } 5731 5732 ecore_init_free(p_hwfn); 5733 ecore_hw_hwfn_free(p_hwfn); 5734 ecore_mcp_free(p_hwfn); 5735 5736 #ifdef CONFIG_ECORE_LOCK_ALLOC 5737 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock); 5738 #endif 5739 } 5740 5741 ecore_iov_free_hw_info(p_dev); 5742 } 5743 5744 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev, 5745 struct ecore_chain *p_chain) 5746 { 5747 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL; 5748 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0; 5749 struct ecore_chain_next *p_next; 5750 u32 size, i; 5751 5752 if (!p_virt) 5753 return; 5754 5755 size = p_chain->elem_size * p_chain->usable_per_page; 5756 5757 for (i = 0; i < p_chain->page_cnt; i++) { 5758 if (!p_virt) 5759 break; 5760 5761 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size); 5762 p_virt_next = p_next->next_virt; 5763 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys); 5764 5765 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys, 5766 ECORE_CHAIN_PAGE_SIZE); 5767 5768 p_virt = p_virt_next; 5769 p_phys = p_phys_next; 5770 } 5771 } 5772 5773 static void ecore_chain_free_single(struct ecore_dev *p_dev, 5774 struct ecore_chain *p_chain) 5775 { 5776 if (!p_chain->p_virt_addr) 5777 return; 5778 5779 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr, 5780 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE); 5781 } 5782 5783 static void ecore_chain_free_pbl(struct ecore_dev *p_dev, 5784 struct ecore_chain *p_chain) 5785 { 5786 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl; 5787 u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table; 5788 u32 page_cnt = p_chain->page_cnt, i, pbl_size; 5789 5790 if (!pp_virt_addr_tbl) 5791 return; 5792 5793 if (!p_pbl_virt) 5794 goto out; 5795 5796 for (i = 0; i < page_cnt; i++) { 5797 if (!pp_virt_addr_tbl[i]) 5798 break; 5799 5800 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i], 5801 *(dma_addr_t *)p_pbl_virt, 5802 ECORE_CHAIN_PAGE_SIZE); 5803 5804 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE; 5805 } 5806 5807 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE; 5808 5809 if (!p_chain->b_external_pbl) 5810 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table, 5811 p_chain->pbl_sp.p_phys_table, pbl_size); 5812 out: 5813 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl); 5814 } 5815 5816 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain) 5817 { 5818 switch (p_chain->mode) { 5819 case ECORE_CHAIN_MODE_NEXT_PTR: 5820 ecore_chain_free_next_ptr(p_dev, p_chain); 5821 break; 5822 case ECORE_CHAIN_MODE_SINGLE: 5823 ecore_chain_free_single(p_dev, p_chain); 5824 break; 5825 case ECORE_CHAIN_MODE_PBL: 5826 ecore_chain_free_pbl(p_dev, p_chain); 5827 break; 5828 } 5829 } 5830 5831 static enum _ecore_status_t 5832 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev, 5833 enum ecore_chain_cnt_type cnt_type, 5834 osal_size_t elem_size, u32 page_cnt) 5835 { 5836 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt; 5837 5838 /* The actual chain size can be larger than the maximal possible value 5839 * after rounding up the requested elements number to pages, and after 5840 * taking into acount the unusuable elements (next-ptr elements). 5841 * The size of a "u16" chain can be (U16_MAX + 1) since the chain 5842 * size/capacity fields are of a u32 type. 5843 */ 5844 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 && 5845 chain_size > ((u32)ECORE_U16_MAX + 1)) || 5846 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 && 5847 chain_size > ECORE_U32_MAX)) { 5848 DP_NOTICE(p_dev, true, 5849 "The actual chain size (0x%lx) is larger than the maximal possible value\n", 5850 (unsigned long)chain_size); 5851 return ECORE_INVAL; 5852 } 5853 5854 return ECORE_SUCCESS; 5855 } 5856 5857 static enum _ecore_status_t 5858 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain) 5859 { 5860 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL; 5861 dma_addr_t p_phys = 0; 5862 u32 i; 5863 5864 for (i = 0; i < p_chain->page_cnt; i++) { 5865 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, 5866 ECORE_CHAIN_PAGE_SIZE); 5867 if (!p_virt) { 5868 DP_NOTICE(p_dev, false, 5869 "Failed to allocate chain memory\n"); 5870 return ECORE_NOMEM; 5871 } 5872 5873 if (i == 0) { 5874 ecore_chain_init_mem(p_chain, p_virt, p_phys); 5875 ecore_chain_reset(p_chain); 5876 } else { 5877 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev, 5878 p_virt, p_phys); 5879 } 5880 5881 p_virt_prev = p_virt; 5882 } 5883 /* Last page's next element should point to the beginning of the 5884 * chain. 5885 */ 5886 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev, 5887 p_chain->p_virt_addr, 5888 p_chain->p_phys_addr); 5889 5890 return ECORE_SUCCESS; 5891 } 5892 5893 static enum _ecore_status_t 5894 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain) 5895 { 5896 dma_addr_t p_phys = 0; 5897 void *p_virt = OSAL_NULL; 5898 5899 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE); 5900 if (!p_virt) { 5901 DP_NOTICE(p_dev, false, "Failed to allocate chain memory\n"); 5902 return ECORE_NOMEM; 5903 } 5904 5905 ecore_chain_init_mem(p_chain, p_virt, p_phys); 5906 ecore_chain_reset(p_chain); 5907 5908 return ECORE_SUCCESS; 5909 } 5910 5911 static enum _ecore_status_t 5912 ecore_chain_alloc_pbl(struct ecore_dev *p_dev, 5913 struct ecore_chain *p_chain, 5914 struct ecore_chain_ext_pbl *ext_pbl) 5915 { 5916 u32 page_cnt = p_chain->page_cnt, size, i; 5917 dma_addr_t p_phys = 0, p_pbl_phys = 0; 5918 void **pp_virt_addr_tbl = OSAL_NULL; 5919 u8 *p_pbl_virt = OSAL_NULL; 5920 void *p_virt = OSAL_NULL; 5921 5922 size = page_cnt * sizeof(*pp_virt_addr_tbl); 5923 pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size); 5924 if (!pp_virt_addr_tbl) { 5925 DP_NOTICE(p_dev, false, 5926 "Failed to allocate memory for the chain virtual addresses table\n"); 5927 return ECORE_NOMEM; 5928 } 5929 5930 /* The allocation of the PBL table is done with its full size, since it 5931 * is expected to be successive. 5932 * ecore_chain_init_pbl_mem() is called even in a case of an allocation 5933 * failure, since pp_virt_addr_tbl was previously allocated, and it 5934 * should be saved to allow its freeing during the error flow. 5935 */ 5936 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE; 5937 5938 if (ext_pbl == OSAL_NULL) { 5939 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size); 5940 } else { 5941 p_pbl_virt = ext_pbl->p_pbl_virt; 5942 p_pbl_phys = ext_pbl->p_pbl_phys; 5943 p_chain->b_external_pbl = true; 5944 } 5945 5946 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys, 5947 pp_virt_addr_tbl); 5948 if (!p_pbl_virt) { 5949 DP_NOTICE(p_dev, false, "Failed to allocate chain pbl memory\n"); 5950 return ECORE_NOMEM; 5951 } 5952 5953 for (i = 0; i < page_cnt; i++) { 5954 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, 5955 ECORE_CHAIN_PAGE_SIZE); 5956 if (!p_virt) { 5957 DP_NOTICE(p_dev, false, 5958 "Failed to allocate chain memory\n"); 5959 return ECORE_NOMEM; 5960 } 5961 5962 if (i == 0) { 5963 ecore_chain_init_mem(p_chain, p_virt, p_phys); 5964 ecore_chain_reset(p_chain); 5965 } 5966 5967 /* Fill the PBL table with the physical address of the page */ 5968 *(dma_addr_t *)p_pbl_virt = p_phys; 5969 /* Keep the virtual address of the page */ 5970 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt; 5971 5972 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE; 5973 } 5974 5975 return ECORE_SUCCESS; 5976 } 5977 5978 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev, 5979 enum ecore_chain_use_mode intended_use, 5980 enum ecore_chain_mode mode, 5981 enum ecore_chain_cnt_type cnt_type, 5982 u32 num_elems, osal_size_t elem_size, 5983 struct ecore_chain *p_chain, 5984 struct ecore_chain_ext_pbl *ext_pbl) 5985 { 5986 u32 page_cnt; 5987 enum _ecore_status_t rc = ECORE_SUCCESS; 5988 5989 if (mode == ECORE_CHAIN_MODE_SINGLE) 5990 page_cnt = 1; 5991 else 5992 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode); 5993 5994 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size, 5995 page_cnt); 5996 if (rc) { 5997 DP_NOTICE(p_dev, false, 5998 "Cannot allocate a chain with the given arguments:\n" 5999 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n", 6000 intended_use, mode, cnt_type, num_elems, elem_size); 6001 return rc; 6002 } 6003 6004 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use, 6005 mode, cnt_type, p_dev->dp_ctx); 6006 6007 switch (mode) { 6008 case ECORE_CHAIN_MODE_NEXT_PTR: 6009 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain); 6010 break; 6011 case ECORE_CHAIN_MODE_SINGLE: 6012 rc = ecore_chain_alloc_single(p_dev, p_chain); 6013 break; 6014 case ECORE_CHAIN_MODE_PBL: 6015 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl); 6016 break; 6017 } 6018 if (rc) 6019 goto nomem; 6020 6021 return ECORE_SUCCESS; 6022 6023 nomem: 6024 ecore_chain_free(p_dev, p_chain); 6025 return rc; 6026 } 6027 6028 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn, 6029 u16 src_id, u16 *dst_id) 6030 { 6031 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) { 6032 u16 min, max; 6033 6034 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE); 6035 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE); 6036 DP_NOTICE(p_hwfn, true, 6037 "l2_queue id [%d] is not valid, available indices [%d - %d]\n", 6038 src_id, min, max); 6039 6040 return ECORE_INVAL; 6041 } 6042 6043 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id; 6044 6045 return ECORE_SUCCESS; 6046 } 6047 6048 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn, 6049 u8 src_id, u8 *dst_id) 6050 { 6051 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) { 6052 u8 min, max; 6053 6054 min = (u8)RESC_START(p_hwfn, ECORE_VPORT); 6055 max = min + RESC_NUM(p_hwfn, ECORE_VPORT); 6056 DP_NOTICE(p_hwfn, true, 6057 "vport id [%d] is not valid, available indices [%d - %d]\n", 6058 src_id, min, max); 6059 6060 return ECORE_INVAL; 6061 } 6062 6063 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id; 6064 6065 return ECORE_SUCCESS; 6066 } 6067 6068 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn, 6069 u8 src_id, u8 *dst_id) 6070 { 6071 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) { 6072 u8 min, max; 6073 6074 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG); 6075 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG); 6076 DP_NOTICE(p_hwfn, true, 6077 "rss_eng id [%d] is not valid, available indices [%d - %d]\n", 6078 src_id, min, max); 6079 6080 return ECORE_INVAL; 6081 } 6082 6083 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id; 6084 6085 return ECORE_SUCCESS; 6086 } 6087 6088 enum _ecore_status_t 6089 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn, 6090 struct ecore_ptt *p_ptt) 6091 { 6092 if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) { 6093 ecore_wr(p_hwfn, p_ptt, 6094 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR, 6095 1 << p_hwfn->abs_pf_id / 2); 6096 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0); 6097 return ECORE_SUCCESS; 6098 } 6099 6100 DP_NOTICE(p_hwfn, false, 6101 "This function can't be set as default\n"); 6102 return ECORE_INVAL; 6103 } 6104 6105 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn, 6106 struct ecore_ptt *p_ptt, 6107 u32 hw_addr, void *p_eth_qzone, 6108 osal_size_t eth_qzone_size, 6109 u8 timeset) 6110 { 6111 struct coalescing_timeset *p_coal_timeset; 6112 6113 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) { 6114 DP_NOTICE(p_hwfn, true, 6115 "Coalescing configuration not enabled\n"); 6116 return ECORE_INVAL; 6117 } 6118 6119 p_coal_timeset = p_eth_qzone; 6120 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size); 6121 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset); 6122 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1); 6123 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size); 6124 6125 return ECORE_SUCCESS; 6126 } 6127 6128 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn, 6129 u16 rx_coal, u16 tx_coal, 6130 void *p_handle) 6131 { 6132 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle; 6133 enum _ecore_status_t rc = ECORE_SUCCESS; 6134 struct ecore_ptt *p_ptt; 6135 6136 /* TODO - Configuring a single queue's coalescing but 6137 * claiming all queues are abiding same configuration 6138 * for PF and VF both. 6139 */ 6140 6141 if (IS_VF(p_hwfn->p_dev)) 6142 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal, 6143 tx_coal, p_cid); 6144 6145 p_ptt = ecore_ptt_acquire(p_hwfn); 6146 if (!p_ptt) 6147 return ECORE_AGAIN; 6148 6149 if (rx_coal) { 6150 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid); 6151 if (rc) 6152 goto out; 6153 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal; 6154 } 6155 6156 if (tx_coal) { 6157 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid); 6158 if (rc) 6159 goto out; 6160 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal; 6161 } 6162 out: 6163 ecore_ptt_release(p_hwfn, p_ptt); 6164 6165 return rc; 6166 } 6167 6168 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn, 6169 struct ecore_ptt *p_ptt, 6170 u16 coalesce, 6171 struct ecore_queue_cid *p_cid) 6172 { 6173 struct ustorm_eth_queue_zone eth_qzone; 6174 u8 timeset, timer_res; 6175 u32 address; 6176 enum _ecore_status_t rc; 6177 6178 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 6179 if (coalesce <= 0x7F) { 6180 timer_res = 0; 6181 } else if (coalesce <= 0xFF) { 6182 timer_res = 1; 6183 } else if (coalesce <= 0x1FF) { 6184 timer_res = 2; 6185 } else { 6186 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 6187 return ECORE_INVAL; 6188 } 6189 timeset = (u8)(coalesce >> timer_res); 6190 6191 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, 6192 p_cid->sb_igu_id, false); 6193 if (rc != ECORE_SUCCESS) 6194 goto out; 6195 6196 address = BAR0_MAP_REG_USDM_RAM + 6197 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id); 6198 6199 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 6200 sizeof(struct ustorm_eth_queue_zone), timeset); 6201 if (rc != ECORE_SUCCESS) 6202 goto out; 6203 6204 out: 6205 return rc; 6206 } 6207 6208 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn, 6209 struct ecore_ptt *p_ptt, 6210 u16 coalesce, 6211 struct ecore_queue_cid *p_cid) 6212 { 6213 struct xstorm_eth_queue_zone eth_qzone; 6214 u8 timeset, timer_res; 6215 u32 address; 6216 enum _ecore_status_t rc; 6217 6218 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 6219 if (coalesce <= 0x7F) { 6220 timer_res = 0; 6221 } else if (coalesce <= 0xFF) { 6222 timer_res = 1; 6223 } else if (coalesce <= 0x1FF) { 6224 timer_res = 2; 6225 } else { 6226 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 6227 return ECORE_INVAL; 6228 } 6229 6230 timeset = (u8)(coalesce >> timer_res); 6231 6232 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, 6233 p_cid->sb_igu_id, true); 6234 if (rc != ECORE_SUCCESS) 6235 goto out; 6236 6237 address = BAR0_MAP_REG_XSDM_RAM + 6238 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id); 6239 6240 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 6241 sizeof(struct xstorm_eth_queue_zone), timeset); 6242 out: 6243 return rc; 6244 } 6245 6246 /* Calculate final WFQ values for all vports and configure it. 6247 * After this configuration each vport must have 6248 * approx min rate = wfq * min_pf_rate / ECORE_WFQ_UNIT 6249 */ 6250 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn, 6251 struct ecore_ptt *p_ptt, 6252 u32 min_pf_rate) 6253 { 6254 struct init_qm_vport_params *vport_params; 6255 int i; 6256 6257 vport_params = p_hwfn->qm_info.qm_vport_params; 6258 6259 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 6260 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 6261 6262 vport_params[i].wfq = (wfq_speed * ECORE_WFQ_UNIT) / 6263 min_pf_rate; 6264 ecore_init_vport_wfq(p_hwfn, p_ptt, 6265 vport_params[i].first_tx_pq_id, 6266 vport_params[i].wfq); 6267 } 6268 } 6269 6270 static void ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn) 6271 { 6272 int i; 6273 6274 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) 6275 p_hwfn->qm_info.qm_vport_params[i].wfq = 1; 6276 } 6277 6278 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn, 6279 struct ecore_ptt *p_ptt) 6280 { 6281 struct init_qm_vport_params *vport_params; 6282 int i; 6283 6284 vport_params = p_hwfn->qm_info.qm_vport_params; 6285 6286 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 6287 ecore_init_wfq_default_param(p_hwfn); 6288 ecore_init_vport_wfq(p_hwfn, p_ptt, 6289 vport_params[i].first_tx_pq_id, 6290 vport_params[i].wfq); 6291 } 6292 } 6293 6294 /* This function performs several validations for WFQ 6295 * configuration and required min rate for a given vport 6296 * 1. req_rate must be greater than one percent of min_pf_rate. 6297 * 2. req_rate should not cause other vports [not configured for WFQ explicitly] 6298 * rates to get less than one percent of min_pf_rate. 6299 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate. 6300 */ 6301 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn, 6302 u16 vport_id, u32 req_rate, 6303 u32 min_pf_rate) 6304 { 6305 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0; 6306 int non_requested_count = 0, req_count = 0, i, num_vports; 6307 6308 num_vports = p_hwfn->qm_info.num_vports; 6309 6310 /* Accounting for the vports which are configured for WFQ explicitly */ 6311 6312 for (i = 0; i < num_vports; i++) { 6313 u32 tmp_speed; 6314 6315 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) { 6316 req_count++; 6317 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 6318 total_req_min_rate += tmp_speed; 6319 } 6320 } 6321 6322 /* Include current vport data as well */ 6323 req_count++; 6324 total_req_min_rate += req_rate; 6325 non_requested_count = num_vports - req_count; 6326 6327 /* validate possible error cases */ 6328 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) { 6329 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 6330 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 6331 vport_id, req_rate, min_pf_rate); 6332 return ECORE_INVAL; 6333 } 6334 6335 /* TBD - for number of vports greater than 100 */ 6336 if (num_vports > ECORE_WFQ_UNIT) { 6337 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 6338 "Number of vports is greater than %d\n", 6339 ECORE_WFQ_UNIT); 6340 return ECORE_INVAL; 6341 } 6342 6343 if (total_req_min_rate > min_pf_rate) { 6344 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 6345 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n", 6346 total_req_min_rate, min_pf_rate); 6347 return ECORE_INVAL; 6348 } 6349 6350 /* Data left for non requested vports */ 6351 total_left_rate = min_pf_rate - total_req_min_rate; 6352 left_rate_per_vp = total_left_rate / non_requested_count; 6353 6354 /* validate if non requested get < 1% of min bw */ 6355 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) { 6356 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 6357 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 6358 left_rate_per_vp, min_pf_rate); 6359 return ECORE_INVAL; 6360 } 6361 6362 /* now req_rate for given vport passes all scenarios. 6363 * assign final wfq rates to all vports. 6364 */ 6365 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate; 6366 p_hwfn->qm_info.wfq_data[vport_id].configured = true; 6367 6368 for (i = 0; i < num_vports; i++) { 6369 if (p_hwfn->qm_info.wfq_data[i].configured) 6370 continue; 6371 6372 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp; 6373 } 6374 6375 return ECORE_SUCCESS; 6376 } 6377 6378 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn, 6379 struct ecore_ptt *p_ptt, 6380 u16 vp_id, u32 rate) 6381 { 6382 struct ecore_mcp_link_state *p_link; 6383 int rc = ECORE_SUCCESS; 6384 6385 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output; 6386 6387 if (!p_link->min_pf_rate) { 6388 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate; 6389 p_hwfn->qm_info.wfq_data[vp_id].configured = true; 6390 return rc; 6391 } 6392 6393 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate); 6394 6395 if (rc == ECORE_SUCCESS) 6396 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, 6397 p_link->min_pf_rate); 6398 else 6399 DP_NOTICE(p_hwfn, false, 6400 "Validation failed while configuring min rate\n"); 6401 6402 return rc; 6403 } 6404 6405 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn, 6406 struct ecore_ptt *p_ptt, 6407 u32 min_pf_rate) 6408 { 6409 bool use_wfq = false; 6410 int rc = ECORE_SUCCESS; 6411 u16 i; 6412 6413 /* Validate all pre configured vports for wfq */ 6414 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 6415 u32 rate; 6416 6417 if (!p_hwfn->qm_info.wfq_data[i].configured) 6418 continue; 6419 6420 rate = p_hwfn->qm_info.wfq_data[i].min_speed; 6421 use_wfq = true; 6422 6423 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate); 6424 if (rc != ECORE_SUCCESS) { 6425 DP_NOTICE(p_hwfn, false, 6426 "WFQ validation failed while configuring min rate\n"); 6427 break; 6428 } 6429 } 6430 6431 if (rc == ECORE_SUCCESS && use_wfq) 6432 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 6433 else 6434 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt); 6435 6436 return rc; 6437 } 6438 6439 /* Main API for ecore clients to configure vport min rate. 6440 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)] 6441 * rate - Speed in Mbps needs to be assigned to a given vport. 6442 */ 6443 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate) 6444 { 6445 int i, rc = ECORE_INVAL; 6446 6447 /* TBD - for multiple hardware functions - that is 100 gig */ 6448 if (ECORE_IS_CMT(p_dev)) { 6449 DP_NOTICE(p_dev, false, 6450 "WFQ configuration is not supported for this device\n"); 6451 return rc; 6452 } 6453 6454 for_each_hwfn(p_dev, i) { 6455 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 6456 struct ecore_ptt *p_ptt; 6457 6458 p_ptt = ecore_ptt_acquire(p_hwfn); 6459 if (!p_ptt) 6460 return ECORE_TIMEOUT; 6461 6462 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate); 6463 6464 if (rc != ECORE_SUCCESS) { 6465 ecore_ptt_release(p_hwfn, p_ptt); 6466 return rc; 6467 } 6468 6469 ecore_ptt_release(p_hwfn, p_ptt); 6470 } 6471 6472 return rc; 6473 } 6474 6475 /* API to configure WFQ from mcp link change */ 6476 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev, 6477 struct ecore_ptt *p_ptt, 6478 u32 min_pf_rate) 6479 { 6480 int i; 6481 6482 /* TBD - for multiple hardware functions - that is 100 gig */ 6483 if (ECORE_IS_CMT(p_dev)) { 6484 DP_VERBOSE(p_dev, ECORE_MSG_LINK, 6485 "WFQ configuration is not supported for this device\n"); 6486 return; 6487 } 6488 6489 for_each_hwfn(p_dev, i) { 6490 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 6491 6492 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt, 6493 min_pf_rate); 6494 } 6495 } 6496 6497 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn, 6498 struct ecore_ptt *p_ptt, 6499 struct ecore_mcp_link_state *p_link, 6500 u8 max_bw) 6501 { 6502 int rc = ECORE_SUCCESS; 6503 6504 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw; 6505 6506 if (!p_link->line_speed && (max_bw != 100)) 6507 return rc; 6508 6509 p_link->speed = (p_link->line_speed * max_bw) / 100; 6510 p_hwfn->qm_info.pf_rl = p_link->speed; 6511 6512 /* Since the limiter also affects Tx-switched traffic, we don't want it 6513 * to limit such traffic in case there's no actual limit. 6514 * In that case, set limit to imaginary high boundary. 6515 */ 6516 if (max_bw == 100) 6517 p_hwfn->qm_info.pf_rl = 100000; 6518 6519 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, 6520 p_hwfn->qm_info.pf_rl); 6521 6522 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 6523 "Configured MAX bandwidth to be %08x Mb/sec\n", 6524 p_link->speed); 6525 6526 return rc; 6527 } 6528 6529 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */ 6530 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw) 6531 { 6532 int i, rc = ECORE_INVAL; 6533 6534 if (max_bw < 1 || max_bw > 100) { 6535 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n"); 6536 return rc; 6537 } 6538 6539 for_each_hwfn(p_dev, i) { 6540 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 6541 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev); 6542 struct ecore_mcp_link_state *p_link; 6543 struct ecore_ptt *p_ptt; 6544 6545 p_link = &p_lead->mcp_info->link_output; 6546 6547 p_ptt = ecore_ptt_acquire(p_hwfn); 6548 if (!p_ptt) 6549 return ECORE_TIMEOUT; 6550 6551 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt, 6552 p_link, max_bw); 6553 6554 ecore_ptt_release(p_hwfn, p_ptt); 6555 6556 if (rc != ECORE_SUCCESS) 6557 break; 6558 } 6559 6560 return rc; 6561 } 6562 6563 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn, 6564 struct ecore_ptt *p_ptt, 6565 struct ecore_mcp_link_state *p_link, 6566 u8 min_bw) 6567 { 6568 int rc = ECORE_SUCCESS; 6569 6570 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw; 6571 p_hwfn->qm_info.pf_wfq = min_bw; 6572 6573 if (!p_link->line_speed) 6574 return rc; 6575 6576 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100; 6577 6578 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw); 6579 6580 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 6581 "Configured MIN bandwidth to be %d Mb/sec\n", 6582 p_link->min_pf_rate); 6583 6584 return rc; 6585 } 6586 6587 /* Main API to configure PF min bandwidth where bw range is [1-100] */ 6588 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw) 6589 { 6590 int i, rc = ECORE_INVAL; 6591 6592 if (min_bw < 1 || min_bw > 100) { 6593 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n"); 6594 return rc; 6595 } 6596 6597 for_each_hwfn(p_dev, i) { 6598 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 6599 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev); 6600 struct ecore_mcp_link_state *p_link; 6601 struct ecore_ptt *p_ptt; 6602 6603 p_link = &p_lead->mcp_info->link_output; 6604 6605 p_ptt = ecore_ptt_acquire(p_hwfn); 6606 if (!p_ptt) 6607 return ECORE_TIMEOUT; 6608 6609 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt, 6610 p_link, min_bw); 6611 if (rc != ECORE_SUCCESS) { 6612 ecore_ptt_release(p_hwfn, p_ptt); 6613 return rc; 6614 } 6615 6616 if (p_link->min_pf_rate) { 6617 u32 min_rate = p_link->min_pf_rate; 6618 6619 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn, 6620 p_ptt, 6621 min_rate); 6622 } 6623 6624 ecore_ptt_release(p_hwfn, p_ptt); 6625 } 6626 6627 return rc; 6628 } 6629 6630 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) 6631 { 6632 struct ecore_mcp_link_state *p_link; 6633 6634 p_link = &p_hwfn->mcp_info->link_output; 6635 6636 if (p_link->min_pf_rate) 6637 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt); 6638 6639 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0, 6640 sizeof(*p_hwfn->qm_info.wfq_data) * 6641 p_hwfn->qm_info.num_vports); 6642 } 6643 6644 int ecore_device_num_engines(struct ecore_dev *p_dev) 6645 { 6646 return ECORE_IS_BB(p_dev) ? 2 : 1; 6647 } 6648 6649 int ecore_device_num_ports(struct ecore_dev *p_dev) 6650 { 6651 return p_dev->num_ports; 6652 } 6653 6654 void ecore_set_fw_mac_addr(__le16 *fw_msb, 6655 __le16 *fw_mid, 6656 __le16 *fw_lsb, 6657 u8 *mac) 6658 { 6659 ((u8 *)fw_msb)[0] = mac[1]; 6660 ((u8 *)fw_msb)[1] = mac[0]; 6661 ((u8 *)fw_mid)[0] = mac[3]; 6662 ((u8 *)fw_mid)[1] = mac[2]; 6663 ((u8 *)fw_lsb)[0] = mac[5]; 6664 ((u8 *)fw_lsb)[1] = mac[4]; 6665 } 6666 6667 bool ecore_is_mf_fip_special(struct ecore_dev *p_dev) 6668 { 6669 return !!OSAL_TEST_BIT(ECORE_MF_FIP_SPECIAL, &p_dev->mf_bits); 6670 } 6671