common/mlx5: add global MR cache create function

Add function for global shared MR cache structure initialization.
This function include:
- btree initialization.
- set callbacks for reg and dereg

common/mlx5: add global MR cache create function

Add function for global shared MR cache structure initialization.
This function include:
- btree initialization.
- set callbacks for reg and dereg MR.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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common/mlx5: add MR control initialization

Add function for MR control structure initialization.
This function include:
- btree initialization.
- dev_gen_ptr initialization.

Signed-off-by: Michae

common/mlx5: add MR control initialization

Add function for MR control structure initialization.
This function include:
- btree initialization.
- dev_gen_ptr initialization.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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mempool: add namespace to flags

Fix the mempool flags namespace by adding an RTE_ prefix to the name.
The old flags remain usable, to be deprecated in the future.

Flag MEMPOOL_F_NON_IO added in the

mempool: add namespace to flags

Fix the mempool flags namespace by adding an RTE_ prefix to the name.
The old flags remain usable, to be deprecated in the future.

Flag MEMPOOL_F_NON_IO added in the release is just renamed to have RTE_
prefix.

Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Acked-by: Olivier Matz <olivier.matz@6wind.com>

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common/mlx5: add mempool registration facilities

Add internal API to register mempools, that is, to create memory
regions (MR) for their memory and store them in a separate database.
Implementation

common/mlx5: add mempool registration facilities

Add internal API to register mempools, that is, to create memory
regions (MR) for their memory and store them in a separate database.
Implementation deals with multi-process, so that class drivers don't
need to. Each protection domain has its own database. Memory regions
can be shared within a database if they represent a single hugepage
covering one or more mempools entirely.

Add internal API to lookup an MR key for an address that belongs
to a known mempool. It is a responsibility of a class driver
to extract the mempool from an mbuf.

Signed-off-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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common/mlx5: fix memory region leak

All the mlx5 drivers using MRs for data-path must unregister the mapped
memory when it is freed by the dpdk process.

Currently, only the net/eth driver unregiste

common/mlx5: fix memory region leak

All the mlx5 drivers using MRs for data-path must unregister the mapped
memory when it is freed by the dpdk process.

Currently, only the net/eth driver unregisters MRs in free event.

Move the net callback handler from net driver to common.

Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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common/mlx5: share hash list tool

In order to use the hash list defined in net in other drivers, the
hash list is moved to common utilities.

In addition, the log definition was moved from the commo

common/mlx5: share hash list tool

In order to use the hash list defined in net in other drivers, the
hash list is moved to common utilities.

In addition, the log definition was moved from the common utilities to
a dedicated new log file in common in order to prevent a conflict.

Signed-off-by: Shiri Kuzin <shirik@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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net/mlx5: enable debug logs dynamically

Most debug logs are using DRV_LOG(DEBUG,)
but some were using DEBUG().
The macro DEBUG is doing nothing if not compiled with
RTE_LIBRTE_MLX5_DEBUG.

As it is

net/mlx5: enable debug logs dynamically

Most debug logs are using DRV_LOG(DEBUG,)
but some were using DEBUG().
The macro DEBUG is doing nothing if not compiled with
RTE_LIBRTE_MLX5_DEBUG.

As it is not used in the data path, the macro DEBUG
can be replaced with DRV_LOG.
Then all debug logs can be enabled at runtime with:
--log-level pmd.net.mlx5:debug

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Matan Azrad <matan@nvidia.com>

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common/mlx5: free MR resource on device DMA unmap

mlx5 PMD created the MR (Memory Region) resource on the
mlx5_dma_map call to make the memory available for DMA
operations. On the mlx5_dma_unmap cal

common/mlx5: free MR resource on device DMA unmap

mlx5 PMD created the MR (Memory Region) resource on the
mlx5_dma_map call to make the memory available for DMA
operations. On the mlx5_dma_unmap call the MR resource
was not freed but inserted to MR Free list for further
garbage collection.
Actual MR resource destroying happened on device stop
call. That caused the runtime out of memory in case of
application performed multiple DMA map/unmap calls.

The fix immediately frees the MR resource on mlx5_dma_unmap
call not engaging the list. The export for mlx5_mr_free
function from common PMD part is added as well.

Fixes: 989e999d9305 ("net/mlx5: support PCI device DMA map and unmap")
Cc: stable@dpdk.org

Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

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common/mlx5: convert data path objects to unified malloc

This commit allocates the data path object page and B-tree table memory
from unified malloc function with explicit flag MLX5_MEM_RTE.

Signed

common/mlx5: convert data path objects to unified malloc

This commit allocates the data path object page and B-tree table memory
from unified malloc function with explicit flag MLX5_MEM_RTE.

Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>

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net/mlx5: add memory region callbacks in per-device cache

Prior to this commit MR operations were verbs based and hard coded under
common/mlx5/linux directory. This commit enables upper layers (e.g.

net/mlx5: add memory region callbacks in per-device cache

Prior to this commit MR operations were verbs based and hard coded under
common/mlx5/linux directory. This commit enables upper layers (e.g.
net/mlx5) to determine which MR operations to use. For example the net
layer could set devx based MR operations in non-Linux environments. The
reg_mr and dereg_mr callbacks are added to the global per-device MR
cache 'struct mlx5_mr_share_cache'.

Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>

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common/mlx5: export memory region Verbs operations

The glue verbs operations reg_mr and dereg_mr are wrapped and exported
in functions mlx5_common_verbs_reg_mr and mlx5_common_verbs_dereg_mr
respect

common/mlx5: export memory region Verbs operations

The glue verbs operations reg_mr and dereg_mr are wrapped and exported
in functions mlx5_common_verbs_reg_mr and mlx5_common_verbs_dereg_mr
respectively. The exported functions are added to a new file
linux/mlx5_common_verbs.c.

Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>

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common/mlx5: remove memory region dependency on Verbs

Replace 'struct ibv_mr *' (in 'struct mlx5_mr') with a new 'struct
mlx5_pmd_mr'. The new struct contains the required MR field: lkey,
addr, len

common/mlx5: remove memory region dependency on Verbs

Replace 'struct ibv_mr *' (in 'struct mlx5_mr') with a new 'struct
mlx5_pmd_mr'. The new struct contains the required MR field: lkey,
addr, len and is independent of ibv.

Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>

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common/mlx5: remove protection domain dependency on Verbs

Replace 'struct ibv_pd *' with 'void *' in struct mlx5_ctx_shared and
all function calls in mlx5 PMD.

Signed-off-by: Ophir Munk <ophirmu@me

common/mlx5: remove protection domain dependency on Verbs

Replace 'struct ibv_pd *' with 'void *' in struct mlx5_ctx_shared and
all function calls in mlx5 PMD.

Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>

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common/mlx5: disable relaxed ordering in unsuitable CPUs

Relaxed ordering is a PCI optimization that enables reordering
reads/writes in order to improve performance.

Relaxed ordering was enabled fo

common/mlx5: disable relaxed ordering in unsuitable CPUs

Relaxed ordering is a PCI optimization that enables reordering
reads/writes in order to improve performance.

Relaxed ordering was enabled for all processors causing
a degradation in performance in Haswell and Broadwell processors
that don't support this optimization.

In order to avoid that we check if the processor is Haswell
or Broadwell and if so we disable relaxed ordering.

Signed-off-by: Shiri Kuzin <shirik@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>

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common/mlx5: refactor memory management

Refactor common memory btree and cache management to common driver.
Replace some input parameters of MR APIs to more common data structure
like PD, port_id, s

common/mlx5: refactor memory management

Refactor common memory btree and cache management to common driver.
Replace some input parameters of MR APIs to more common data structure
like PD, port_id, share_cache,... so that multiple PMD drivers can
use those MR APIs.

Modify mlx5 net pmd driver to use MR management APIs from common driver.

Signed-off-by: Vu Pham <vuhuong@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>

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