1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefix=RV32I 4; RUN: llc -mtriple=riscv32 -target-abi ilp32e -verify-machineinstrs < %s \ 5; RUN: | FileCheck %s -check-prefix=RV32I-ILP32E 6; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ 7; RUN: | FileCheck %s -check-prefix=RV64I 8; RUN: llc -mtriple=riscv64 -target-abi lp64e -verify-machineinstrs < %s \ 9; RUN: | FileCheck %s -check-prefix=RV64I-LP64E 10 11declare void @callee(ptr, ptr) 12 13define void @caller(i32 %n) { 14; RV32I-LABEL: caller: 15; RV32I: # %bb.0: 16; RV32I-NEXT: addi sp, sp, -64 17; RV32I-NEXT: .cfi_def_cfa_offset 64 18; RV32I-NEXT: sw ra, 60(sp) # 4-byte Folded Spill 19; RV32I-NEXT: sw s0, 56(sp) # 4-byte Folded Spill 20; RV32I-NEXT: sw s1, 52(sp) # 4-byte Folded Spill 21; RV32I-NEXT: .cfi_offset ra, -4 22; RV32I-NEXT: .cfi_offset s0, -8 23; RV32I-NEXT: .cfi_offset s1, -12 24; RV32I-NEXT: addi s0, sp, 64 25; RV32I-NEXT: .cfi_def_cfa s0, 0 26; RV32I-NEXT: andi sp, sp, -64 27; RV32I-NEXT: mv s1, sp 28; RV32I-NEXT: addi a0, a0, 15 29; RV32I-NEXT: andi a0, a0, -16 30; RV32I-NEXT: sub a0, sp, a0 31; RV32I-NEXT: mv sp, a0 32; RV32I-NEXT: mv a1, s1 33; RV32I-NEXT: call callee 34; RV32I-NEXT: addi sp, s0, -64 35; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload 36; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload 37; RV32I-NEXT: lw s1, 52(sp) # 4-byte Folded Reload 38; RV32I-NEXT: addi sp, sp, 64 39; RV32I-NEXT: ret 40; 41; RV32I-ILP32E-LABEL: caller: 42; RV32I-ILP32E: # %bb.0: 43; RV32I-ILP32E-NEXT: addi sp, sp, -64 44; RV32I-ILP32E-NEXT: .cfi_def_cfa_offset 64 45; RV32I-ILP32E-NEXT: sw ra, 60(sp) # 4-byte Folded Spill 46; RV32I-ILP32E-NEXT: sw s0, 56(sp) # 4-byte Folded Spill 47; RV32I-ILP32E-NEXT: sw s1, 52(sp) # 4-byte Folded Spill 48; RV32I-ILP32E-NEXT: .cfi_offset ra, -4 49; RV32I-ILP32E-NEXT: .cfi_offset s0, -8 50; RV32I-ILP32E-NEXT: .cfi_offset s1, -12 51; RV32I-ILP32E-NEXT: addi s0, sp, 64 52; RV32I-ILP32E-NEXT: .cfi_def_cfa s0, 0 53; RV32I-ILP32E-NEXT: andi sp, sp, -64 54; RV32I-ILP32E-NEXT: mv s1, sp 55; RV32I-ILP32E-NEXT: addi a0, a0, 3 56; RV32I-ILP32E-NEXT: andi a0, a0, -4 57; RV32I-ILP32E-NEXT: sub a0, sp, a0 58; RV32I-ILP32E-NEXT: mv sp, a0 59; RV32I-ILP32E-NEXT: mv a1, s1 60; RV32I-ILP32E-NEXT: call callee 61; RV32I-ILP32E-NEXT: addi sp, s0, -64 62; RV32I-ILP32E-NEXT: lw ra, 60(sp) # 4-byte Folded Reload 63; RV32I-ILP32E-NEXT: lw s0, 56(sp) # 4-byte Folded Reload 64; RV32I-ILP32E-NEXT: lw s1, 52(sp) # 4-byte Folded Reload 65; RV32I-ILP32E-NEXT: addi sp, sp, 64 66; RV32I-ILP32E-NEXT: ret 67; 68; RV64I-LABEL: caller: 69; RV64I: # %bb.0: 70; RV64I-NEXT: addi sp, sp, -64 71; RV64I-NEXT: .cfi_def_cfa_offset 64 72; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill 73; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill 74; RV64I-NEXT: sd s1, 40(sp) # 8-byte Folded Spill 75; RV64I-NEXT: .cfi_offset ra, -8 76; RV64I-NEXT: .cfi_offset s0, -16 77; RV64I-NEXT: .cfi_offset s1, -24 78; RV64I-NEXT: addi s0, sp, 64 79; RV64I-NEXT: .cfi_def_cfa s0, 0 80; RV64I-NEXT: andi sp, sp, -64 81; RV64I-NEXT: mv s1, sp 82; RV64I-NEXT: slli a0, a0, 32 83; RV64I-NEXT: srli a0, a0, 32 84; RV64I-NEXT: addi a0, a0, 15 85; RV64I-NEXT: andi a0, a0, -16 86; RV64I-NEXT: sub a0, sp, a0 87; RV64I-NEXT: mv sp, a0 88; RV64I-NEXT: mv a1, s1 89; RV64I-NEXT: call callee 90; RV64I-NEXT: addi sp, s0, -64 91; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload 92; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload 93; RV64I-NEXT: ld s1, 40(sp) # 8-byte Folded Reload 94; RV64I-NEXT: addi sp, sp, 64 95; RV64I-NEXT: ret 96; 97; RV64I-LP64E-LABEL: caller: 98; RV64I-LP64E: # %bb.0: 99; RV64I-LP64E-NEXT: addi sp, sp, -64 100; RV64I-LP64E-NEXT: .cfi_def_cfa_offset 64 101; RV64I-LP64E-NEXT: sd ra, 56(sp) # 8-byte Folded Spill 102; RV64I-LP64E-NEXT: sd s0, 48(sp) # 8-byte Folded Spill 103; RV64I-LP64E-NEXT: sd s1, 40(sp) # 8-byte Folded Spill 104; RV64I-LP64E-NEXT: .cfi_offset ra, -8 105; RV64I-LP64E-NEXT: .cfi_offset s0, -16 106; RV64I-LP64E-NEXT: .cfi_offset s1, -24 107; RV64I-LP64E-NEXT: addi s0, sp, 64 108; RV64I-LP64E-NEXT: .cfi_def_cfa s0, 0 109; RV64I-LP64E-NEXT: andi sp, sp, -64 110; RV64I-LP64E-NEXT: mv s1, sp 111; RV64I-LP64E-NEXT: slli a0, a0, 32 112; RV64I-LP64E-NEXT: srli a0, a0, 32 113; RV64I-LP64E-NEXT: addi a0, a0, 7 114; RV64I-LP64E-NEXT: andi a0, a0, -8 115; RV64I-LP64E-NEXT: sub a0, sp, a0 116; RV64I-LP64E-NEXT: mv sp, a0 117; RV64I-LP64E-NEXT: mv a1, s1 118; RV64I-LP64E-NEXT: call callee 119; RV64I-LP64E-NEXT: addi sp, s0, -64 120; RV64I-LP64E-NEXT: ld ra, 56(sp) # 8-byte Folded Reload 121; RV64I-LP64E-NEXT: ld s0, 48(sp) # 8-byte Folded Reload 122; RV64I-LP64E-NEXT: ld s1, 40(sp) # 8-byte Folded Reload 123; RV64I-LP64E-NEXT: addi sp, sp, 64 124; RV64I-LP64E-NEXT: ret 125 %1 = alloca i8, i32 %n 126 %2 = alloca i32, align 64 127 call void @callee(ptr %1, ptr %2) 128 ret void 129} 130