1; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=null %s 2>&1 | FileCheck -check-prefix=ERR %s 2 3; Diagnose register constraints that are not wide enough. 4 5; ERR: error: couldn't allocate output register for constraint '{v[8:15]}' 6define <9 x i32> @inline_asm_9xi32_in_8v_def() { 7 %asm = call <9 x i32> asm sideeffect "; def $0", "={v[8:15]}"() 8 ret <9 x i32> %asm 9} 10 11; ERR: error: couldn't allocate input reg for constraint '{v[8:15]}' 12define void @inline_asm_9xi32_in_8v_use(<9 x i32> %val) { 13 call void asm sideeffect "; use $0", "{v[8:15]}"(<9 x i32> %val) 14 ret void 15} 16 17; ERR: error: couldn't allocate output register for constraint '{s[8:15]}' 18define <9 x i32> @inline_asm_9xi32_in_8s_def() { 19 %asm = call <9 x i32> asm sideeffect "; def $0", "={s[8:15]}"() 20 ret <9 x i32> %asm 21} 22 23 24; Diagnose register constraints that are too wide. 25 26; ERR: error: couldn't allocate output register for constraint '{v[8:16]}' 27define <8 x i32> @inline_asm_8xi32_in_9v_def() { 28 %asm = call <8 x i32> asm sideeffect "; def $0", "={v[8:16]}"() 29 ret <8 x i32> %asm 30} 31 32; ERR: error: couldn't allocate input reg for constraint '{v[8:16]}' 33define void @inline_asm_8xi32_in_9v_use(<8 x i32> %val) { 34 call void asm sideeffect "; use $0", "{v[8:16]}"(<8 x i32> %val) 35 ret void 36} 37 38; ERR: error: couldn't allocate output register for constraint '{s[8:16]}' 39define <8 x i32> @inline_asm_8xi32_in_9s_def() { 40 %asm = call <8 x i32> asm sideeffect "; def $0", "={s[8:16]}"() 41 ret <8 x i32> %asm 42} 43 44 45; Diagnose mismatched scalars with register ranges 46 47; ERR: error: couldn't allocate output register for constraint '{s[4:5]}' 48define void @inline_asm_scalar_read_too_wide() { 49 %asm = call i32 asm sideeffect "; def $0 ", "={s[4:5]}"() 50 ret void 51} 52 53; ERR: error: couldn't allocate output register for constraint '{s[4:4]}' 54define void @inline_asm_scalar_read_too_narrow() { 55 %asm = call i64 asm sideeffect "; def $0 ", "={s[4:4]}"() 56 ret void 57} 58 59; Single registers for vector types that are too wide or too narrow should be 60; diagnosed. 61 62; ERR: error: couldn't allocate input reg for constraint '{v8}' 63define void @inline_asm_4xi32_in_v_use(<4 x i32> %val) { 64 call void asm sideeffect "; use $0", "{v8}"(<4 x i32> %val) 65 ret void 66} 67 68; ERR: error: couldn't allocate output register for constraint '{v8}' 69define <4 x i32> @inline_asm_4xi32_in_v_def() { 70 %asm = call <4 x i32> asm sideeffect "; def $0", "={v8}"() 71 ret <4 x i32> %asm 72} 73 74; ERR: error: couldn't allocate output register for constraint '{s8}' 75define <4 x i32> @inline_asm_4xi32_in_s_def() { 76 %asm = call <4 x i32> asm sideeffect "; def $0", "={s8}"() 77 ret <4 x i32> %asm 78} 79 80; ERR: error: couldn't allocate input reg for constraint '{v8}' 81; ERR: error: couldn't allocate input reg for constraint 'v' 82define void @inline_asm_2xi8_in_v_use(<2 x i8> %val) { 83 call void asm sideeffect "; use $0", "{v8}"(<2 x i8> %val) 84 call void asm sideeffect "; use $0", "v"(<2 x i8> %val) 85 ret void 86} 87 88; ERR: error: couldn't allocate output register for constraint '{v8}' 89; ERR: error: couldn't allocate output register for constraint 'v' 90define <2 x i8> @inline_asm_2xi8_in_v_def() { 91 %phys = call <2 x i8> asm sideeffect "; def $0", "={v8}"() 92 %virt = call <2 x i8> asm sideeffect "; def $0", "=v"() 93 %r = and <2 x i8> %phys, %virt 94 ret <2 x i8> %r 95} 96 97; ERR: error: couldn't allocate output register for constraint '{s8}' 98; ERR: error: couldn't allocate output register for constraint 's' 99define <2 x i8> @inline_asm_2xi8_in_s_def() { 100 %phys = call <2 x i8> asm sideeffect "; def $0", "={s8}"() 101 %virt = call <2 x i8> asm sideeffect "; def $0", "=s"() 102 %r = and <2 x i8> %phys, %virt 103 ret <2 x i8> %r 104} 105 106 107; The register is wide enough, but it does not satisfy alignment constraints: 108 109; ERR: error: couldn't allocate input reg for constraint '{s[1:2]}' 110define void @misaligned_sgpr_2xi32_in(<2 x i32> inreg %arg0) { 111 call void asm sideeffect "; use $0", "{s[1:2]}"(<2 x i32> %arg0) 112 ret void 113} 114 115; ERR: error: couldn't allocate input reg for constraint '{s[23:24]}' 116define void @misaligned_sgpr_2xi32_in_23(<2 x i32> inreg %arg0) { 117 call void asm sideeffect "; use $0", "{s[23:24]}"(<2 x i32> %arg0) 118 ret void 119} 120 121; ERR: error: couldn't allocate input reg for constraint '{s[1:4]}' 122define void @misaligned_sgpr_4xi32_in(<4 x i32> inreg %arg0) { 123 call void asm sideeffect "; use $0", "{s[1:4]}"(<4 x i32> %arg0) 124 ret void 125} 126 127; ERR: error: couldn't allocate input reg for constraint '{s[2:5]}' 128define void @misaligned_sgpr_4xi32_in_2(<4 x i32> inreg %arg0) { 129 call void asm sideeffect "; use $0", "{s[2:5]}"(<4 x i32> %arg0) 130 ret void 131} 132 133; ERR: error: couldn't allocate output register for constraint '{s[1:2]}' 134define <2 x i32> @misaligned_sgpr_2xi32_out() { 135 %asm = call <2 x i32> asm sideeffect "; def $0", "={s[1:2]}"() 136 ret <2 x i32> %asm 137} 138 139; ERR: error: couldn't allocate output register for constraint '{s[23:24]}' 140define <2 x i32> @misaligned_sgpr_2xi32_out_23() { 141 %asm = call <2 x i32> asm sideeffect "; def $0", "={s[23:24]}"() 142 ret <2 x i32> %asm 143} 144 145; ERR: error: couldn't allocate output register for constraint '{s[1:4]}' 146define <4 x i32> @misaligned_sgpr_4xi32_out() { 147 %asm = call <4 x i32> asm sideeffect "; def $0", "={s[1:4]}"() 148 ret <4 x i32> %asm 149} 150 151; ERR: error: couldn't allocate output register for constraint '{s[2:5]}' 152define <4 x i32> @misaligned_sgpr_4xi32_out_2() { 153 %asm = call <4 x i32> asm sideeffect "; def $0", "={s[2:5]}"() 154 ret <4 x i32> %asm 155} 156