[AMDGPU] Reject misaligned SGPR constraints for inline asm (#123590)

The indices of SGPR register pairs need to be 2-aligned and SGPR
quadruplets need to be 4-aligned. With this patch, we report an

[AMDGPU] Reject misaligned SGPR constraints for inline asm (#123590)

The indices of SGPR register pairs need to be 2-aligned and SGPR
quadruplets need to be 4-aligned. With this patch, we report an error
when inline asm register constraints specify a misaligned register
index, instead of silently dropping the specified index.

Fixes #123208

---------

Co-authored-by: Matt Arsenault <arsenm2@gmail.com>

show more ...

[AMDGPU] Check vector sizes for physical register constraints in inline asm (#109955)

For register constraints that require specific register ranges, the
width of the range should match the type of

[AMDGPU] Check vector sizes for physical register constraints in inline asm (#109955)

For register constraints that require specific register ranges, the
width of the range should match the type of the associated
parameter/return value. With this PR, we error out when that is not the
case. Previously, these cases would hit assertions or llvm_unreachables.

The handling of register constraints that require only a single register
remains more lenient to allow narrower non-vector types for the
associated IR values. For example, constraining an i16 or i8 value to a
32-bit register is still allowed.

Fixes #101190.

---------

Co-authored-by: Matt Arsenault <arsenm2@gmail.com>

show more ...