1 /* 2 * SPDX-License-Identifier: BSD-3-Clause 3 * Copyright(c) 2023 Napatech A/S 4 */ 5 6 #ifndef _HW_MOD_BACKEND_H_ 7 #define _HW_MOD_BACKEND_H_ 8 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include "ntlog.h" 13 14 #include "hw_mod_cat_v18.h" 15 #include "hw_mod_cat_v21.h" 16 #include "hw_mod_flm_v25.h" 17 #include "hw_mod_km_v7.h" 18 #include "hw_mod_qsl_v7.h" 19 #include "hw_mod_pdb_v9.h" 20 #include "hw_mod_slc_lr_v2.h" 21 #include "hw_mod_hsh_v5.h" 22 #include "hw_mod_tpe_v3.h" 23 24 #define MAX_PHYS_ADAPTERS 8 25 26 #define VER_MAJOR(ver) (((ver) >> 16) & 0xffff) 27 #define VER_MINOR(ver) ((ver) & 0xffff) 28 29 struct flow_api_backend_s; 30 struct common_func_s; 31 32 void *callocate_mod(struct common_func_s *mod, int sets, ...); 33 void zero_module_cache(struct common_func_s *mod); 34 35 #define ALL_ENTRIES -1000 36 #define ALL_BANK_ENTRIES -1001 37 38 #define INDEX_TOO_LARGE (-2) 39 #define INDEX_TOO_LARGE_LOG NT_LOG(INF, FILTER, "ERROR:%s: Index too large", __func__) 40 41 #define WORD_OFF_TOO_LARGE (-3) 42 #define WORD_OFF_TOO_LARGE_LOG NT_LOG(INF, FILTER, "ERROR:%s: Word offset too large", __func__) 43 44 #define UNSUP_FIELD (-5) 45 #define UNSUP_FIELD_LOG \ 46 NT_LOG(INF, FILTER, "ERROR:%s: Unsupported field in NIC module", __func__) 47 48 #define UNSUP_VER (-4) 49 #define UNSUP_VER_LOG \ 50 NT_LOG(INF, FILTER, "ERROR:%s: Unsupported NIC module: %s ver %i.%i", __func__, _MOD_, \ 51 VER_MAJOR(_VER_), VER_MINOR(_VER_)) 52 53 #define COUNT_ERROR (-4) 54 #define COUNT_ERROR_LOG(_RESOURCE_) \ 55 NT_LOG(INF, FILTER, \ 56 "ERROR:%s: Insufficient resource [ %s ] : NIC module: %s ver %i.%i", __func__, \ 57 #_RESOURCE_, _MOD_, VER_MAJOR(_VER_), VER_MINOR(_VER_)) \ 58 59 #define NOT_FOUND 0xffffffff 60 61 enum { 62 EXTRA_INDEXES 63 }; 64 65 #define GET(cached_val, val) ({ *(val) = *(cached_val); }) 66 67 #define SET(cached_val, val) ({ *(cached_val) = *(val); }) 68 69 #define GET_SET(cached_val, val) \ 70 do { \ 71 uint32_t *temp_val = (val); \ 72 typeof(cached_val) *temp_cached_val = &(cached_val); \ 73 if (get) \ 74 GET(temp_cached_val, temp_val); \ 75 else \ 76 SET(temp_cached_val, temp_val); \ 77 } while (0) 78 79 #define GET_SIGNED(cached_val, val) ({ *(val) = (uint32_t)(*(cached_val)); }) 80 81 #define SET_SIGNED(cached_val, val) ({ *(cached_val) = (int32_t)(*(val)); }) 82 83 #define GET_SET_SIGNED(cached_val, val) \ 84 do { \ 85 uint32_t *temp_val = (val); \ 86 typeof(cached_val) *temp_cached_val = &(cached_val); \ 87 if (get) \ 88 GET_SIGNED(temp_cached_val, temp_val); \ 89 else \ 90 SET_SIGNED(temp_cached_val, temp_val); \ 91 } while (0) 92 93 #define FIND_EQUAL_INDEX(be_module_reg, type, idx, start, nb_elements) \ 94 do { \ 95 typeof(be_module_reg) *temp_be_module = \ 96 (typeof(be_module_reg) *)be_module_reg; \ 97 typeof(idx) tmp_idx = (idx); \ 98 typeof(nb_elements) tmp_nb_elements = (nb_elements); \ 99 unsigned int start_idx = (unsigned int)(start); \ 100 *value = NOT_FOUND; \ 101 for (unsigned int i = start_idx; i < tmp_nb_elements; i++) { \ 102 if ((unsigned int)(tmp_idx) == i) \ 103 continue; \ 104 if (memcmp(&temp_be_module[tmp_idx], &temp_be_module[i], sizeof(type)) == \ 105 0) { \ 106 *value = i; \ 107 break; \ 108 } \ 109 } \ 110 } while (0) 111 112 #define DO_COMPARE_INDEXS(be_module_reg, type, idx, cmp_idx) \ 113 do { \ 114 typeof(be_module_reg) *temp_be_module = &(be_module_reg); \ 115 typeof(idx) tmp_idx = (idx); \ 116 typeof(cmp_idx) tmp_cmp_idx = (cmp_idx); \ 117 if ((unsigned int)(tmp_idx) != (unsigned int)(tmp_cmp_idx)) { \ 118 (void)memcmp(temp_be_module + tmp_idx, &temp_be_module[tmp_cmp_idx], \ 119 sizeof(type)); \ 120 } \ 121 } while (0) 122 123 static inline int is_non_zero(const void *addr, size_t n) 124 { 125 size_t i = 0; 126 const uint8_t *p = (const uint8_t *)addr; 127 128 for (i = 0; i < n; i++) 129 if (p[i] != 0) 130 return 1; 131 132 return 0; 133 } 134 135 /* Sideband info bit indicator */ 136 #define SWX_INFO (1 << 6) 137 138 enum km_flm_if_select_e { 139 KM_FLM_IF_FIRST = 0, 140 KM_FLM_IF_SECOND = 1 141 }; 142 143 #define FIELD_START_INDEX 100 144 145 #define COMMON_FUNC_INFO_S \ 146 int ver; \ 147 void *base; \ 148 unsigned int alloced_size; \ 149 int debug 150 151 enum frame_offs_e { 152 DYN_L2 = 1, 153 DYN_FIRST_VLAN = 2, 154 DYN_L3 = 4, 155 DYN_L4 = 7, 156 DYN_L4_PAYLOAD = 8, 157 DYN_TUN_L3 = 13, 158 DYN_TUN_L4 = 16, 159 DYN_TUN_L4_PAYLOAD = 17, 160 SB_VNI = SWX_INFO | 1, 161 SB_MAC_PORT = SWX_INFO | 2, 162 SB_KCC_ID = SWX_INFO | 3 163 }; 164 165 enum { 166 QW0_SEL_EXCLUDE = 0, 167 QW0_SEL_FIRST32 = 1, 168 QW0_SEL_FIRST64 = 3, 169 QW0_SEL_ALL128 = 4, 170 }; 171 172 enum { 173 QW4_SEL_EXCLUDE = 0, 174 QW4_SEL_FIRST32 = 1, 175 QW4_SEL_FIRST64 = 2, 176 QW4_SEL_ALL128 = 3, 177 }; 178 179 enum { 180 DW8_SEL_EXCLUDE = 0, 181 DW8_SEL_FIRST32 = 3, 182 }; 183 184 enum { 185 DW10_SEL_EXCLUDE = 0, 186 DW10_SEL_FIRST32 = 2, 187 }; 188 189 enum { 190 SWX_SEL_EXCLUDE = 0, 191 SWX_SEL_ALL32 = 1, 192 }; 193 194 enum { 195 PROT_OTHER = 0, 196 PROT_L2_ETH2 = 1, 197 }; 198 199 enum { 200 PROT_L3_IPV4 = 1, 201 PROT_L3_IPV6 = 2 202 }; 203 204 enum { 205 PROT_L4_TCP = 1, 206 PROT_L4_UDP = 2, 207 PROT_L4_SCTP = 3, 208 PROT_L4_ICMP = 4 209 }; 210 211 enum { 212 PROT_TUN_GTPV1U = 6, 213 }; 214 215 enum { 216 PROT_TUN_L3_OTHER = 0, 217 PROT_TUN_L3_IPV4 = 1, 218 PROT_TUN_L3_IPV6 = 2 219 }; 220 221 enum { 222 PROT_TUN_L4_OTHER = 0, 223 PROT_TUN_L4_TCP = 1, 224 PROT_TUN_L4_UDP = 2, 225 PROT_TUN_L4_SCTP = 3, 226 PROT_TUN_L4_ICMP = 4 227 }; 228 229 230 enum { 231 CPY_SELECT_DSCP_IPV4 = 0, 232 CPY_SELECT_DSCP_IPV6 = 1, 233 CPY_SELECT_RQI_QFI = 2, 234 CPY_SELECT_IPV4 = 3, 235 CPY_SELECT_PORT = 4, 236 CPY_SELECT_TEID = 5, 237 }; 238 239 struct common_func_s { 240 COMMON_FUNC_INFO_S; 241 }; 242 243 struct cat_func_s { 244 COMMON_FUNC_INFO_S; 245 uint32_t nb_cat_funcs; 246 uint32_t nb_flow_types; 247 uint32_t nb_pm_ext; 248 uint32_t nb_len; 249 uint32_t kcc_size; 250 uint32_t cts_num; 251 uint32_t kcc_banks; 252 uint32_t kcc_id_bit_size; 253 uint32_t kcc_records; 254 uint32_t km_if_count; 255 int32_t km_if_m0; 256 int32_t km_if_m1; 257 258 union { 259 struct hw_mod_cat_v18_s v18; 260 struct hw_mod_cat_v21_s v21; 261 }; 262 }; 263 enum hw_cat_e { 264 /* 265 * functions initial CAT v18 266 */ 267 /* 00 */ HW_CAT_CFN_SET_ALL_DEFAULTS = 0, 268 /* 01 */ HW_CAT_CFN_PRESET_ALL, 269 /* 02 */ HW_CAT_CFN_COMPARE, 270 /* 03 */ HW_CAT_CFN_FIND, 271 /* 04 */ HW_CAT_CFN_COPY_FROM, 272 /* 05 */ HW_CAT_COT_PRESET_ALL, 273 /* 06 */ HW_CAT_COT_COMPARE, 274 /* 07 */ HW_CAT_COT_FIND, 275 /* 08 */ HW_CAT_COT_COPY_FROM, 276 /* fields */ 277 /* 00 */ HW_CAT_CFN_ENABLE = FIELD_START_INDEX, 278 /* 01 */ HW_CAT_CFN_INV, 279 /* 02 */ HW_CAT_CFN_PTC_INV, 280 /* 03 */ HW_CAT_CFN_PTC_ISL, 281 /* 04 */ HW_CAT_CFN_PTC_CFP, 282 /* 05 */ HW_CAT_CFN_PTC_MAC, 283 /* 06 */ HW_CAT_CFN_PTC_L2, 284 /* 07 */ HW_CAT_CFN_PTC_VNTAG, 285 /* 08 */ HW_CAT_CFN_PTC_VLAN, 286 /* 09 */ HW_CAT_CFN_PTC_MPLS, 287 /* 10 */ HW_CAT_CFN_PTC_L3, 288 /* 11 */ HW_CAT_CFN_PTC_FRAG, 289 /* 12 */ HW_CAT_CFN_PTC_IP_PROT, 290 /* 13 */ HW_CAT_CFN_PTC_L4, 291 /* 14 */ HW_CAT_CFN_PTC_TUNNEL, 292 /* 15 */ HW_CAT_CFN_PTC_TNL_L2, 293 /* 16 */ HW_CAT_CFN_PTC_TNL_VLAN, 294 /* 17 */ HW_CAT_CFN_PTC_TNL_MPLS, 295 /* 18 */ HW_CAT_CFN_PTC_TNL_L3, 296 /* 19 */ HW_CAT_CFN_PTC_TNL_FRAG, 297 /* 20 */ HW_CAT_CFN_PTC_TNL_IP_PROT, 298 /* 21 */ HW_CAT_CFN_PTC_TNL_L4, 299 /* 22 */ HW_CAT_CFN_ERR_INV, 300 /* 23 */ HW_CAT_CFN_ERR_CV, 301 /* 24 */ HW_CAT_CFN_ERR_FCS, 302 /* 25 */ HW_CAT_CFN_ERR_TRUNC, 303 /* 26 */ HW_CAT_CFN_ERR_L3_CS, 304 /* 27 */ HW_CAT_CFN_ERR_L4_CS, 305 /* 28 */ HW_CAT_CFN_MAC_PORT, 306 /* 29 */ HW_CAT_CFN_PM_CMP, 307 /* 30 */ HW_CAT_CFN_PM_DCT, 308 /* 31 */ HW_CAT_CFN_PM_EXT_INV, 309 /* 32 */ HW_CAT_CFN_PM_CMB, 310 /* 33 */ HW_CAT_CFN_PM_AND_INV, 311 /* 34 */ HW_CAT_CFN_PM_OR_INV, 312 /* 35 */ HW_CAT_CFN_PM_INV, 313 /* 36 */ HW_CAT_CFN_LC, 314 /* 37 */ HW_CAT_CFN_LC_INV, 315 /* 38 */ HW_CAT_CFN_KM0_OR, 316 /* 39 */ HW_CAT_CFN_KM1_OR, 317 /* 40 */ HW_CAT_KCE_ENABLE_BM, 318 /* 41 */ HW_CAT_KCS_CATEGORY, 319 /* 42 */ HW_CAT_FTE_ENABLE_BM, 320 /* 43 */ HW_CAT_CTE_ENABLE_BM, 321 /* 44 */ HW_CAT_CTS_CAT_A, 322 /* 45 */ HW_CAT_CTS_CAT_B, 323 /* 46 */ HW_CAT_COT_COLOR, 324 /* 47 */ HW_CAT_COT_KM, 325 /* 48 */ HW_CAT_CCT_COLOR, 326 /* 49 */ HW_CAT_CCT_KM, 327 /* 50 */ HW_CAT_KCC_KEY, 328 /* 51 */ HW_CAT_KCC_CATEGORY, 329 /* 52 */ HW_CAT_KCC_ID, 330 /* 53 */ HW_CAT_EXO_DYN, 331 /* 54 */ HW_CAT_EXO_OFS, 332 /* 55 */ HW_CAT_RCK_DATA, 333 /* 56 */ HW_CAT_LEN_LOWER, 334 /* 57 */ HW_CAT_LEN_UPPER, 335 /* 58 */ HW_CAT_LEN_DYN1, 336 /* 59 */ HW_CAT_LEN_DYN2, 337 /* 60 */ HW_CAT_LEN_INV, 338 /* 61 */ HW_CAT_CFN_ERR_TNL_L3_CS, 339 /* 62 */ HW_CAT_CFN_ERR_TNL_L4_CS, 340 /* 63 */ HW_CAT_CFN_ERR_TTL_EXP, 341 /* 64 */ HW_CAT_CFN_ERR_TNL_TTL_EXP, 342 }; 343 344 bool hw_mod_cat_present(struct flow_api_backend_s *be); 345 int hw_mod_cat_alloc(struct flow_api_backend_s *be); 346 void hw_mod_cat_free(struct flow_api_backend_s *be); 347 int hw_mod_cat_reset(struct flow_api_backend_s *be); 348 int hw_mod_cat_cfn_flush(struct flow_api_backend_s *be, int start_idx, int count); 349 int hw_mod_cat_cfn_set(struct flow_api_backend_s *be, enum hw_cat_e field, int index, int word_off, 350 uint32_t value); 351 /* KCE/KCS/FTE KM */ 352 int hw_mod_cat_fte_km_flush(struct flow_api_backend_s *be, enum km_flm_if_select_e if_num, 353 int start_idx, int count); 354 int hw_mod_cat_fte_km_set(struct flow_api_backend_s *be, enum hw_cat_e field, 355 enum km_flm_if_select_e if_num, int index, uint32_t value); 356 int hw_mod_cat_fte_km_get(struct flow_api_backend_s *be, enum hw_cat_e field, 357 enum km_flm_if_select_e if_num, int index, uint32_t *value); 358 /* KCE/KCS/FTE FLM */ 359 int hw_mod_cat_fte_flm_flush(struct flow_api_backend_s *be, enum km_flm_if_select_e if_num, 360 int start_idx, int count); 361 int hw_mod_cat_fte_flm_set(struct flow_api_backend_s *be, enum hw_cat_e field, 362 enum km_flm_if_select_e if_num, int index, uint32_t value); 363 int hw_mod_cat_fte_flm_get(struct flow_api_backend_s *be, enum hw_cat_e field, 364 enum km_flm_if_select_e if_num, int index, uint32_t *value); 365 366 int hw_mod_cat_cte_flush(struct flow_api_backend_s *be, int start_idx, int count); 367 int hw_mod_cat_cte_set(struct flow_api_backend_s *be, enum hw_cat_e field, int index, 368 uint32_t value); 369 370 int hw_mod_cat_cts_flush(struct flow_api_backend_s *be, int start_idx, int count); 371 int hw_mod_cat_cts_set(struct flow_api_backend_s *be, enum hw_cat_e field, int index, 372 uint32_t value); 373 374 int hw_mod_cat_cot_flush(struct flow_api_backend_s *be, int start_idx, int count); 375 int hw_mod_cat_cot_set(struct flow_api_backend_s *be, enum hw_cat_e field, int index, 376 uint32_t value); 377 378 int hw_mod_cat_cct_flush(struct flow_api_backend_s *be, int start_idx, int count); 379 380 int hw_mod_cat_kcc_flush(struct flow_api_backend_s *be, int start_idx, int count); 381 382 int hw_mod_cat_exo_flush(struct flow_api_backend_s *be, int start_idx, int count); 383 int hw_mod_cat_rck_flush(struct flow_api_backend_s *be, int start_idx, int count); 384 int hw_mod_cat_len_flush(struct flow_api_backend_s *be, int start_idx, int count); 385 386 struct km_func_s { 387 COMMON_FUNC_INFO_S; 388 uint32_t nb_categories; 389 uint32_t nb_cam_banks; 390 uint32_t nb_cam_record_words; 391 uint32_t nb_cam_records; 392 uint32_t nb_tcam_banks; 393 uint32_t nb_tcam_bank_width; 394 /* not read from backend, but rather set using version */ 395 uint32_t nb_km_rcp_mask_a_word_size; 396 /* --- || --- */ 397 uint32_t nb_km_rcp_mask_b_word_size; 398 union { 399 struct hw_mod_km_v7_s v7; 400 }; 401 }; 402 enum hw_km_e { 403 /* functions */ 404 HW_KM_RCP_PRESET_ALL = 0, 405 HW_KM_CAM_PRESET_ALL, 406 /* to sync and reset hw with cache - force write all entries in a bank */ 407 HW_KM_TCAM_BANK_RESET, 408 /* fields */ 409 HW_KM_RCP_QW0_DYN = FIELD_START_INDEX, 410 HW_KM_RCP_QW0_OFS, 411 HW_KM_RCP_QW0_SEL_A, 412 HW_KM_RCP_QW0_SEL_B, 413 HW_KM_RCP_QW4_DYN, 414 HW_KM_RCP_QW4_OFS, 415 HW_KM_RCP_QW4_SEL_A, 416 HW_KM_RCP_QW4_SEL_B, 417 HW_KM_RCP_DW8_DYN, 418 HW_KM_RCP_DW8_OFS, 419 HW_KM_RCP_DW8_SEL_A, 420 HW_KM_RCP_DW8_SEL_B, 421 HW_KM_RCP_DW10_DYN, 422 HW_KM_RCP_DW10_OFS, 423 HW_KM_RCP_DW10_SEL_A, 424 HW_KM_RCP_DW10_SEL_B, 425 HW_KM_RCP_SWX_CCH, 426 HW_KM_RCP_SWX_SEL_A, 427 HW_KM_RCP_SWX_SEL_B, 428 HW_KM_RCP_MASK_A, 429 HW_KM_RCP_MASK_B, 430 HW_KM_RCP_DUAL, 431 HW_KM_RCP_PAIRED, 432 HW_KM_RCP_EL_A, 433 HW_KM_RCP_EL_B, 434 HW_KM_RCP_INFO_A, 435 HW_KM_RCP_INFO_B, 436 HW_KM_RCP_FTM_A, 437 HW_KM_RCP_FTM_B, 438 HW_KM_RCP_BANK_A, 439 HW_KM_RCP_BANK_B, 440 HW_KM_RCP_KL_A, 441 HW_KM_RCP_KL_B, 442 HW_KM_RCP_KEYWAY_A, 443 HW_KM_RCP_KEYWAY_B, 444 HW_KM_RCP_SYNERGY_MODE, 445 HW_KM_RCP_DW0_B_DYN, 446 HW_KM_RCP_DW0_B_OFS, 447 HW_KM_RCP_DW2_B_DYN, 448 HW_KM_RCP_DW2_B_OFS, 449 HW_KM_RCP_SW4_B_DYN, 450 HW_KM_RCP_SW4_B_OFS, 451 HW_KM_RCP_SW5_B_DYN, 452 HW_KM_RCP_SW5_B_OFS, 453 HW_KM_CAM_W0, 454 HW_KM_CAM_W1, 455 HW_KM_CAM_W2, 456 HW_KM_CAM_W3, 457 HW_KM_CAM_W4, 458 HW_KM_CAM_W5, 459 HW_KM_CAM_FT0, 460 HW_KM_CAM_FT1, 461 HW_KM_CAM_FT2, 462 HW_KM_CAM_FT3, 463 HW_KM_CAM_FT4, 464 HW_KM_CAM_FT5, 465 HW_KM_TCAM_T, 466 HW_KM_TCI_COLOR, 467 HW_KM_TCI_FT, 468 HW_KM_TCQ_BANK_MASK, 469 HW_KM_TCQ_QUAL 470 }; 471 bool hw_mod_km_present(struct flow_api_backend_s *be); 472 int hw_mod_km_alloc(struct flow_api_backend_s *be); 473 void hw_mod_km_free(struct flow_api_backend_s *be); 474 int hw_mod_km_reset(struct flow_api_backend_s *be); 475 int hw_mod_km_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 476 int hw_mod_km_rcp_set(struct flow_api_backend_s *be, enum hw_km_e field, int index, int word_off, 477 uint32_t value); 478 int hw_mod_km_rcp_get(struct flow_api_backend_s *be, enum hw_km_e field, int index, int word_off, 479 uint32_t *value); 480 int hw_mod_km_cam_flush(struct flow_api_backend_s *be, int start_bank, int start_record, 481 int count); 482 int hw_mod_km_cam_set(struct flow_api_backend_s *be, enum hw_km_e field, int bank, int record, 483 uint32_t value); 484 485 int hw_mod_km_tcam_flush(struct flow_api_backend_s *be, int start_bank, int count); 486 int hw_mod_km_tcam_set(struct flow_api_backend_s *be, enum hw_km_e field, int bank, int byte, 487 int byte_val, uint32_t *value_set); 488 int hw_mod_km_tcam_get(struct flow_api_backend_s *be, enum hw_km_e field, int bank, int byte, 489 int byte_val, uint32_t *value_set); 490 int hw_mod_km_tci_flush(struct flow_api_backend_s *be, int start_bank, int start_record, 491 int count); 492 int hw_mod_km_tci_set(struct flow_api_backend_s *be, enum hw_km_e field, int bank, int record, 493 uint32_t value); 494 int hw_mod_km_tcq_flush(struct flow_api_backend_s *be, int start_bank, int start_record, 495 int count); 496 497 struct flm_func_s { 498 COMMON_FUNC_INFO_S; 499 uint32_t nb_categories; 500 uint32_t nb_size_mb; 501 uint32_t nb_entry_size; 502 uint32_t nb_variant; 503 uint32_t nb_prios; 504 uint32_t nb_pst_profiles; 505 uint32_t nb_scrub_profiles; 506 uint32_t nb_rpp_clock_in_ps; 507 uint32_t nb_load_aps_max; 508 union { 509 struct hw_mod_flm_v25_s v25; 510 }; 511 }; 512 enum hw_flm_e { 513 /* functions */ 514 HW_FLM_CONTROL_PRESET_ALL = 0, 515 HW_FLM_RCP_PRESET_ALL, 516 HW_FLM_FLOW_LRN_DATA, 517 HW_FLM_FLOW_INF_STA_DATA, 518 /* Control fields */ 519 HW_FLM_CONTROL_ENABLE = FIELD_START_INDEX, 520 HW_FLM_CONTROL_INIT, 521 HW_FLM_CONTROL_LDS, 522 HW_FLM_CONTROL_LFS, 523 HW_FLM_CONTROL_LIS, 524 HW_FLM_CONTROL_UDS, 525 HW_FLM_CONTROL_UIS, 526 HW_FLM_CONTROL_RDS, 527 HW_FLM_CONTROL_RIS, 528 HW_FLM_CONTROL_PDS, 529 HW_FLM_CONTROL_PIS, 530 HW_FLM_CONTROL_CRCWR, 531 HW_FLM_CONTROL_CRCRD, 532 HW_FLM_CONTROL_RBL, 533 HW_FLM_CONTROL_EAB, 534 HW_FLM_CONTROL_SPLIT_SDRAM_USAGE, 535 HW_FLM_STATUS_CALIB_SUCCESS, 536 HW_FLM_STATUS_CALIB_FAIL, 537 HW_FLM_STATUS_INITDONE, 538 HW_FLM_STATUS_IDLE, 539 HW_FLM_STATUS_CRITICAL, 540 HW_FLM_STATUS_PANIC, 541 HW_FLM_STATUS_CRCERR, 542 HW_FLM_STATUS_EFT_BP, 543 HW_FLM_STATUS_CACHE_BUFFER_CRITICAL, 544 HW_FLM_LOAD_BIN, 545 HW_FLM_LOAD_LPS, 546 HW_FLM_LOAD_APS, 547 HW_FLM_PRIO_LIMIT0, 548 HW_FLM_PRIO_FT0, 549 HW_FLM_PRIO_LIMIT1, 550 HW_FLM_PRIO_FT1, 551 HW_FLM_PRIO_LIMIT2, 552 HW_FLM_PRIO_FT2, 553 HW_FLM_PRIO_LIMIT3, 554 HW_FLM_PRIO_FT3, 555 HW_FLM_PST_PRESET_ALL, 556 HW_FLM_PST_BP, 557 HW_FLM_PST_PP, 558 HW_FLM_PST_TP, 559 HW_FLM_RCP_LOOKUP, 560 HW_FLM_RCP_QW0_DYN, 561 HW_FLM_RCP_QW0_OFS, 562 HW_FLM_RCP_QW0_SEL, 563 HW_FLM_RCP_QW4_DYN, 564 HW_FLM_RCP_QW4_OFS, 565 HW_FLM_RCP_SW8_DYN, 566 HW_FLM_RCP_SW8_OFS, 567 HW_FLM_RCP_SW8_SEL, 568 HW_FLM_RCP_SW9_DYN, 569 HW_FLM_RCP_SW9_OFS, 570 HW_FLM_RCP_MASK, 571 HW_FLM_RCP_KID, 572 HW_FLM_RCP_OPN, 573 HW_FLM_RCP_IPN, 574 HW_FLM_RCP_BYT_DYN, 575 HW_FLM_RCP_BYT_OFS, 576 HW_FLM_RCP_TXPLM, 577 HW_FLM_RCP_AUTO_IPV4_MASK, 578 HW_FLM_BUF_CTRL_LRN_FREE, 579 HW_FLM_BUF_CTRL_INF_AVAIL, 580 HW_FLM_BUF_CTRL_STA_AVAIL, 581 HW_FLM_STAT_LRN_DONE, 582 HW_FLM_STAT_LRN_IGNORE, 583 HW_FLM_STAT_LRN_FAIL, 584 HW_FLM_STAT_UNL_DONE, 585 HW_FLM_STAT_UNL_IGNORE, 586 HW_FLM_STAT_REL_DONE, 587 HW_FLM_STAT_REL_IGNORE, 588 HW_FLM_STAT_PRB_DONE, 589 HW_FLM_STAT_PRB_IGNORE, 590 HW_FLM_STAT_AUL_DONE, 591 HW_FLM_STAT_AUL_IGNORE, 592 HW_FLM_STAT_AUL_FAIL, 593 HW_FLM_STAT_TUL_DONE, 594 HW_FLM_STAT_FLOWS, 595 HW_FLM_STAT_STA_DONE, /* module ver 0.20 */ 596 HW_FLM_STAT_INF_DONE, /* module ver 0.20 */ 597 HW_FLM_STAT_INF_SKIP, /* module ver 0.20 */ 598 HW_FLM_STAT_PCK_HIT, /* module ver 0.20 */ 599 HW_FLM_STAT_PCK_MISS, /* module ver 0.20 */ 600 HW_FLM_STAT_PCK_UNH, /* module ver 0.20 */ 601 HW_FLM_STAT_PCK_DIS, /* module ver 0.20 */ 602 HW_FLM_STAT_CSH_HIT, /* module ver 0.20 */ 603 HW_FLM_STAT_CSH_MISS, /* module ver 0.20 */ 604 HW_FLM_STAT_CSH_UNH, /* module ver 0.20 */ 605 HW_FLM_STAT_CUC_START, /* module ver 0.20 */ 606 HW_FLM_STAT_CUC_MOVE, /* module ver 0.20 */ 607 HW_FLM_SCAN_I, /* module ver 0.22 */ 608 HW_FLM_SCRUB_PRESET_ALL, 609 HW_FLM_SCRUB_T, /* module ver 0.22 */ 610 HW_FLM_SCRUB_R, /* module ver 0.24 */ 611 HW_FLM_SCRUB_DEL, /* module ver 0.24 */ 612 HW_FLM_SCRUB_INF, /* module ver 0.24 */ 613 }; 614 615 bool hw_mod_flm_present(struct flow_api_backend_s *be); 616 int hw_mod_flm_alloc(struct flow_api_backend_s *be); 617 void hw_mod_flm_free(struct flow_api_backend_s *be); 618 int hw_mod_flm_reset(struct flow_api_backend_s *be); 619 620 int hw_mod_flm_control_flush(struct flow_api_backend_s *be); 621 int hw_mod_flm_control_set(struct flow_api_backend_s *be, enum hw_flm_e field, uint32_t value); 622 623 int hw_mod_flm_scan_flush(struct flow_api_backend_s *be); 624 625 int hw_mod_flm_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 626 627 int hw_mod_flm_scrub_flush(struct flow_api_backend_s *be, int start_idx, int count); 628 629 struct hsh_func_s { 630 COMMON_FUNC_INFO_S; 631 uint32_t nb_rcp;/* number of HSH recipes supported by FPGA */ 632 /* indication if Toeplitz is supported by FPGA, i.e. 0 - unsupported, 1 - supported */ 633 uint32_t toeplitz; 634 union { 635 struct hw_mod_hsh_v5_s v5; 636 }; 637 }; 638 enum hw_hsh_e { 639 /* functions */ 640 HW_HSH_RCP_PRESET_ALL = 0, 641 HW_HSH_RCP_COMPARE, 642 HW_HSH_RCP_FIND, 643 /* fields */ 644 HW_HSH_RCP_LOAD_DIST_TYPE = FIELD_START_INDEX, 645 HW_HSH_RCP_MAC_PORT_MASK, 646 HW_HSH_RCP_SORT, 647 HW_HSH_RCP_QW0_PE, 648 HW_HSH_RCP_QW0_OFS, 649 HW_HSH_RCP_QW4_PE, 650 HW_HSH_RCP_QW4_OFS, 651 HW_HSH_RCP_W8_PE, 652 HW_HSH_RCP_W8_OFS, 653 HW_HSH_RCP_W8_SORT, 654 HW_HSH_RCP_W9_PE, 655 HW_HSH_RCP_W9_OFS, 656 HW_HSH_RCP_W9_SORT, 657 HW_HSH_RCP_W9_P, 658 HW_HSH_RCP_P_MASK, 659 HW_HSH_RCP_WORD_MASK, 660 HW_HSH_RCP_SEED, 661 HW_HSH_RCP_TNL_P, 662 HW_HSH_RCP_HSH_VALID, 663 HW_HSH_RCP_HSH_TYPE, 664 HW_HSH_RCP_TOEPLITZ, 665 HW_HSH_RCP_K, 666 HW_HSH_RCP_AUTO_IPV4_MASK 667 }; 668 bool hw_mod_hsh_present(struct flow_api_backend_s *be); 669 int hw_mod_hsh_alloc(struct flow_api_backend_s *be); 670 void hw_mod_hsh_free(struct flow_api_backend_s *be); 671 int hw_mod_hsh_reset(struct flow_api_backend_s *be); 672 int hw_mod_hsh_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 673 674 struct qsl_func_s { 675 COMMON_FUNC_INFO_S; 676 uint32_t nb_rcp_categories; 677 uint32_t nb_qst_entries; 678 union { 679 struct hw_mod_qsl_v7_s v7; 680 }; 681 }; 682 enum hw_qsl_e { 683 /* functions */ 684 HW_QSL_RCP_PRESET_ALL = 0, 685 HW_QSL_RCP_COMPARE, 686 HW_QSL_RCP_FIND, 687 HW_QSL_QST_PRESET_ALL, 688 /* fields */ 689 HW_QSL_RCP_DISCARD = FIELD_START_INDEX, 690 HW_QSL_RCP_DROP, 691 HW_QSL_RCP_TBL_LO, 692 HW_QSL_RCP_TBL_HI, 693 HW_QSL_RCP_TBL_IDX, 694 HW_QSL_RCP_TBL_MSK, 695 HW_QSL_RCP_LR, 696 HW_QSL_RCP_TSA, 697 HW_QSL_RCP_VLI, 698 HW_QSL_QST_QUEUE, 699 HW_QSL_QST_EN, /* Alias: HW_QSL_QST_QEN */ 700 HW_QSL_QST_TX_PORT, 701 HW_QSL_QST_LRE, 702 HW_QSL_QST_TCI, 703 HW_QSL_QST_VEN, 704 HW_QSL_QEN_EN, 705 HW_QSL_UNMQ_DEST_QUEUE, 706 HW_QSL_UNMQ_EN, 707 }; 708 bool hw_mod_qsl_present(struct flow_api_backend_s *be); 709 int hw_mod_qsl_alloc(struct flow_api_backend_s *be); 710 void hw_mod_qsl_free(struct flow_api_backend_s *be); 711 int hw_mod_qsl_reset(struct flow_api_backend_s *be); 712 int hw_mod_qsl_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 713 int hw_mod_qsl_rcp_set(struct flow_api_backend_s *be, enum hw_qsl_e field, uint32_t index, 714 uint32_t value); 715 int hw_mod_qsl_qst_flush(struct flow_api_backend_s *be, int start_idx, int count); 716 int hw_mod_qsl_qst_set(struct flow_api_backend_s *be, enum hw_qsl_e field, uint32_t index, 717 uint32_t value); 718 int hw_mod_qsl_qen_flush(struct flow_api_backend_s *be, int start_idx, int count); 719 int hw_mod_qsl_qen_set(struct flow_api_backend_s *be, enum hw_qsl_e field, uint32_t index, 720 uint32_t value); 721 int hw_mod_qsl_qen_get(struct flow_api_backend_s *be, enum hw_qsl_e field, uint32_t index, 722 uint32_t *value); 723 int hw_mod_qsl_unmq_flush(struct flow_api_backend_s *be, int start_idx, int count); 724 int hw_mod_qsl_unmq_set(struct flow_api_backend_s *be, enum hw_qsl_e field, uint32_t index, 725 uint32_t value); 726 727 struct slc_lr_func_s { 728 COMMON_FUNC_INFO_S; 729 union { 730 struct hw_mod_slc_lr_v2_s v2; 731 }; 732 }; 733 enum hw_slc_lr_e { 734 /* functions */ 735 HW_SLC_LR_RCP_PRESET_ALL = 0, 736 HW_SLC_LR_RCP_COMPARE, 737 HW_SLC_LR_RCP_FIND, 738 /* fields */ 739 HW_SLC_LR_RCP_HEAD_SLC_EN = FIELD_START_INDEX, 740 HW_SLC_LR_RCP_HEAD_DYN, 741 HW_SLC_LR_RCP_HEAD_OFS, 742 HW_SLC_LR_RCP_TAIL_SLC_EN, 743 HW_SLC_LR_RCP_TAIL_DYN, 744 HW_SLC_LR_RCP_TAIL_OFS, 745 HW_SLC_LR_RCP_PCAP 746 }; 747 bool hw_mod_slc_lr_present(struct flow_api_backend_s *be); 748 int hw_mod_slc_lr_alloc(struct flow_api_backend_s *be); 749 void hw_mod_slc_lr_free(struct flow_api_backend_s *be); 750 int hw_mod_slc_lr_reset(struct flow_api_backend_s *be); 751 int hw_mod_slc_lr_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 752 int hw_mod_slc_lr_rcp_set(struct flow_api_backend_s *be, enum hw_slc_lr_e field, uint32_t index, 753 uint32_t value); 754 755 struct pdb_func_s { 756 COMMON_FUNC_INFO_S; 757 uint32_t nb_pdb_rcp_categories; 758 759 union { 760 struct hw_mod_pdb_v9_s v9; 761 }; 762 }; 763 enum hw_pdb_e { 764 /* functions */ 765 HW_PDB_RCP_PRESET_ALL = 0, 766 HW_PDB_RCP_COMPARE, 767 HW_PDB_RCP_FIND, 768 /* fields */ 769 HW_PDB_RCP_DESCRIPTOR = FIELD_START_INDEX, 770 HW_PDB_RCP_DESC_LEN, 771 HW_PDB_RCP_TX_PORT, 772 HW_PDB_RCP_TX_IGNORE, 773 HW_PDB_RCP_TX_NOW, 774 HW_PDB_RCP_CRC_OVERWRITE, 775 HW_PDB_RCP_ALIGN, 776 HW_PDB_RCP_OFS0_DYN, 777 HW_PDB_RCP_OFS0_REL, 778 HW_PDB_RCP_OFS1_DYN, 779 HW_PDB_RCP_OFS1_REL, 780 HW_PDB_RCP_OFS2_DYN, 781 HW_PDB_RCP_OFS2_REL, 782 HW_PDB_RCP_IP_PROT_TNL, 783 HW_PDB_RCP_PPC_HSH, 784 HW_PDB_RCP_DUPLICATE_EN, 785 HW_PDB_RCP_DUPLICATE_BIT, 786 HW_PDB_RCP_PCAP_KEEP_FCS, 787 HW_PDB_CONFIG_TS_FORMAT, 788 HW_PDB_CONFIG_PORT_OFS, 789 }; 790 bool hw_mod_pdb_present(struct flow_api_backend_s *be); 791 int hw_mod_pdb_alloc(struct flow_api_backend_s *be); 792 void hw_mod_pdb_free(struct flow_api_backend_s *be); 793 int hw_mod_pdb_reset(struct flow_api_backend_s *be); 794 int hw_mod_pdb_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 795 int hw_mod_pdb_rcp_set(struct flow_api_backend_s *be, enum hw_pdb_e field, uint32_t index, 796 uint32_t value); 797 798 int hw_mod_pdb_config_flush(struct flow_api_backend_s *be); 799 800 struct tpe_func_s { 801 COMMON_FUNC_INFO_S; 802 uint32_t nb_rcp_categories; 803 uint32_t nb_ifr_categories; 804 uint32_t nb_cpy_writers; 805 uint32_t nb_rpl_depth; 806 uint32_t nb_rpl_ext_categories; 807 union { 808 struct hw_mod_tpe_v3_s v3; 809 }; 810 }; 811 enum hw_tpe_e { 812 /* functions */ 813 HW_TPE_PRESET_ALL = 0, 814 HW_TPE_FIND, 815 HW_TPE_COMPARE, 816 /* Control fields */ 817 HW_TPE_RPP_RCP_EXP = FIELD_START_INDEX, 818 HW_TPE_IFR_RCP_IPV4_EN, 819 HW_TPE_IFR_RCP_IPV4_DF_DROP, 820 HW_TPE_IFR_RCP_IPV6_EN, 821 HW_TPE_IFR_RCP_IPV6_DROP, 822 HW_TPE_IFR_RCP_MTU, 823 HW_TPE_INS_RCP_DYN, 824 HW_TPE_INS_RCP_OFS, 825 HW_TPE_INS_RCP_LEN, 826 HW_TPE_RPL_RCP_DYN, 827 HW_TPE_RPL_RCP_OFS, 828 HW_TPE_RPL_RCP_LEN, 829 HW_TPE_RPL_RCP_RPL_PTR, 830 HW_TPE_RPL_RCP_EXT_PRIO, 831 HW_TPE_RPL_RCP_ETH_TYPE_WR, 832 HW_TPE_RPL_EXT_RPL_PTR, 833 HW_TPE_RPL_EXT_META_RPL_LEN, /* SW only */ 834 HW_TPE_RPL_RPL_VALUE, 835 HW_TPE_CPY_RCP_READER_SELECT, 836 HW_TPE_CPY_RCP_DYN, 837 HW_TPE_CPY_RCP_OFS, 838 HW_TPE_CPY_RCP_LEN, 839 HW_TPE_HFU_RCP_LEN_A_WR, 840 HW_TPE_HFU_RCP_LEN_A_OUTER_L4_LEN, 841 HW_TPE_HFU_RCP_LEN_A_POS_DYN, 842 HW_TPE_HFU_RCP_LEN_A_POS_OFS, 843 HW_TPE_HFU_RCP_LEN_A_ADD_DYN, 844 HW_TPE_HFU_RCP_LEN_A_ADD_OFS, 845 HW_TPE_HFU_RCP_LEN_A_SUB_DYN, 846 HW_TPE_HFU_RCP_LEN_B_WR, 847 HW_TPE_HFU_RCP_LEN_B_POS_DYN, 848 HW_TPE_HFU_RCP_LEN_B_POS_OFS, 849 HW_TPE_HFU_RCP_LEN_B_ADD_DYN, 850 HW_TPE_HFU_RCP_LEN_B_ADD_OFS, 851 HW_TPE_HFU_RCP_LEN_B_SUB_DYN, 852 HW_TPE_HFU_RCP_LEN_C_WR, 853 HW_TPE_HFU_RCP_LEN_C_POS_DYN, 854 HW_TPE_HFU_RCP_LEN_C_POS_OFS, 855 HW_TPE_HFU_RCP_LEN_C_ADD_DYN, 856 HW_TPE_HFU_RCP_LEN_C_ADD_OFS, 857 HW_TPE_HFU_RCP_LEN_C_SUB_DYN, 858 HW_TPE_HFU_RCP_TTL_WR, 859 HW_TPE_HFU_RCP_TTL_POS_DYN, 860 HW_TPE_HFU_RCP_TTL_POS_OFS, 861 HW_TPE_CSU_RCP_OUTER_L3_CMD, 862 HW_TPE_CSU_RCP_OUTER_L4_CMD, 863 HW_TPE_CSU_RCP_INNER_L3_CMD, 864 HW_TPE_CSU_RCP_INNER_L4_CMD, 865 }; 866 bool hw_mod_tpe_present(struct flow_api_backend_s *be); 867 int hw_mod_tpe_alloc(struct flow_api_backend_s *be); 868 void hw_mod_tpe_free(struct flow_api_backend_s *be); 869 int hw_mod_tpe_reset(struct flow_api_backend_s *be); 870 871 int hw_mod_tpe_rpp_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 872 873 int hw_mod_tpe_rpp_ifr_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 874 875 int hw_mod_tpe_ifr_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 876 877 int hw_mod_tpe_ins_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 878 879 int hw_mod_tpe_rpl_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 880 881 int hw_mod_tpe_rpl_ext_flush(struct flow_api_backend_s *be, int start_idx, int count); 882 883 int hw_mod_tpe_rpl_rpl_flush(struct flow_api_backend_s *be, int start_idx, int count); 884 885 int hw_mod_tpe_cpy_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 886 887 int hw_mod_tpe_hfu_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 888 889 int hw_mod_tpe_csu_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 890 891 enum debug_mode_e { 892 FLOW_BACKEND_DEBUG_MODE_NONE = 0x0000, 893 FLOW_BACKEND_DEBUG_MODE_WRITE = 0x0001 894 }; 895 896 struct flow_api_backend_ops { 897 int version; 898 int (*set_debug_mode)(void *dev, enum debug_mode_e mode); 899 int (*get_nb_phy_port)(void *dev); 900 int (*get_nb_rx_port)(void *dev); 901 int (*get_ltx_avail)(void *dev); 902 int (*get_nb_cat_funcs)(void *dev); 903 int (*get_nb_categories)(void *dev); 904 int (*get_nb_cat_km_if_cnt)(void *dev); 905 int (*get_nb_cat_km_if_m0)(void *dev); 906 int (*get_nb_cat_km_if_m1)(void *dev); 907 908 int (*get_nb_queues)(void *dev); 909 int (*get_nb_km_flow_types)(void *dev); 910 int (*get_nb_pm_ext)(void *dev); 911 int (*get_nb_len)(void *dev); 912 int (*get_kcc_size)(void *dev); 913 int (*get_kcc_banks)(void *dev); 914 int (*get_nb_km_categories)(void *dev); 915 int (*get_nb_km_cam_banks)(void *dev); 916 int (*get_nb_km_cam_record_words)(void *dev); 917 int (*get_nb_km_cam_records)(void *dev); 918 int (*get_nb_km_tcam_banks)(void *dev); 919 int (*get_nb_km_tcam_bank_width)(void *dev); 920 int (*get_nb_flm_categories)(void *dev); 921 int (*get_nb_flm_size_mb)(void *dev); 922 int (*get_nb_flm_entry_size)(void *dev); 923 int (*get_nb_flm_variant)(void *dev); 924 int (*get_nb_flm_prios)(void *dev); 925 int (*get_nb_flm_pst_profiles)(void *dev); 926 int (*get_nb_flm_scrub_profiles)(void *dev); 927 int (*get_nb_flm_load_aps_max)(void *dev); 928 int (*get_nb_qsl_categories)(void *dev); 929 int (*get_nb_qsl_qst_entries)(void *dev); 930 int (*get_nb_pdb_categories)(void *dev); 931 int (*get_nb_roa_categories)(void *dev); 932 int (*get_nb_tpe_categories)(void *dev); 933 int (*get_nb_tx_cpy_writers)(void *dev); 934 int (*get_nb_tx_cpy_mask_mem)(void *dev); 935 int (*get_nb_tx_rpl_depth)(void *dev); 936 int (*get_nb_tx_rpl_ext_categories)(void *dev); 937 int (*get_nb_tpe_ifr_categories)(void *dev); 938 int (*get_nb_rpp_per_ps)(void *dev); 939 int (*get_nb_hsh_categories)(void *dev); 940 int (*get_nb_hsh_toeplitz)(void *dev); 941 942 int (*alloc_rx_queue)(void *dev, int queue_id); 943 int (*free_rx_queue)(void *dev, int hw_queue); 944 945 /* CAT */ 946 bool (*get_cat_present)(void *dev); 947 uint32_t (*get_cat_version)(void *dev); 948 int (*cat_cfn_flush)(void *dev, const struct cat_func_s *cat, int cat_func, int cnt); 949 int (*cat_kce_flush)(void *dev, const struct cat_func_s *cat, int km_if_idx, int index, 950 int cnt); 951 int (*cat_kcs_flush)(void *dev, const struct cat_func_s *cat, int km_if_idx, int cat_func, 952 int cnt); 953 int (*cat_fte_flush)(void *dev, const struct cat_func_s *cat, int km_if_idx, int index, 954 int cnt); 955 int (*cat_cte_flush)(void *dev, const struct cat_func_s *cat, int cat_func, int cnt); 956 int (*cat_cts_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt); 957 int (*cat_cot_flush)(void *dev, const struct cat_func_s *cat, int cat_func, int cnt); 958 int (*cat_cct_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt); 959 int (*cat_exo_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt); 960 int (*cat_rck_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt); 961 int (*cat_len_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt); 962 int (*cat_kcc_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt); 963 964 /* KM */ 965 bool (*get_km_present)(void *dev); 966 uint32_t (*get_km_version)(void *dev); 967 int (*km_rcp_flush)(void *dev, const struct km_func_s *km, int category, int cnt); 968 int (*km_cam_flush)(void *dev, const struct km_func_s *km, int bank, int record, int cnt); 969 int (*km_tcam_flush)(void *dev, const struct km_func_s *km, int bank, int byte, int value, 970 int cnt); 971 int (*km_tci_flush)(void *dev, const struct km_func_s *km, int bank, int record, int cnt); 972 int (*km_tcq_flush)(void *dev, const struct km_func_s *km, int bank, int record, int cnt); 973 974 /* FLM */ 975 bool (*get_flm_present)(void *dev); 976 uint32_t (*get_flm_version)(void *dev); 977 int (*flm_control_flush)(void *dev, const struct flm_func_s *flm); 978 int (*flm_status_flush)(void *dev, const struct flm_func_s *flm); 979 int (*flm_status_update)(void *dev, const struct flm_func_s *flm); 980 int (*flm_scan_flush)(void *dev, const struct flm_func_s *flm); 981 int (*flm_load_bin_flush)(void *dev, const struct flm_func_s *flm); 982 int (*flm_prio_flush)(void *dev, const struct flm_func_s *flm); 983 int (*flm_pst_flush)(void *dev, const struct flm_func_s *flm, int index, int cnt); 984 int (*flm_rcp_flush)(void *dev, const struct flm_func_s *flm, int index, int cnt); 985 int (*flm_scrub_flush)(void *dev, const struct flm_func_s *flm, int index, int cnt); 986 int (*flm_buf_ctrl_update)(void *dev, const struct flm_func_s *flm); 987 int (*flm_stat_update)(void *dev, const struct flm_func_s *flm); 988 int (*flm_lrn_data_flush)(void *be_dev, const struct flm_func_s *flm, 989 const uint32_t *lrn_data, uint32_t records, 990 uint32_t *handled_records, uint32_t words_per_record, 991 uint32_t *inf_word_cnt, uint32_t *sta_word_cnt); 992 int (*flm_inf_sta_data_update)(void *be_dev, const struct flm_func_s *flm, 993 uint32_t *inf_data, uint32_t inf_size, 994 uint32_t *inf_word_cnt, uint32_t *sta_data, 995 uint32_t sta_size, uint32_t *sta_word_cnt); 996 997 /* HSH */ 998 bool (*get_hsh_present)(void *dev); 999 uint32_t (*get_hsh_version)(void *dev); 1000 int (*hsh_rcp_flush)(void *dev, const struct hsh_func_s *hsh, int category, int cnt); 1001 1002 /* QSL */ 1003 bool (*get_qsl_present)(void *dev); 1004 uint32_t (*get_qsl_version)(void *dev); 1005 int (*qsl_rcp_flush)(void *dev, const struct qsl_func_s *qsl, int category, int cnt); 1006 int (*qsl_qst_flush)(void *dev, const struct qsl_func_s *qsl, int entry, int cnt); 1007 int (*qsl_qen_flush)(void *dev, const struct qsl_func_s *qsl, int entry, int cnt); 1008 int (*qsl_unmq_flush)(void *dev, const struct qsl_func_s *qsl, int entry, int cnt); 1009 1010 /* SLC LR */ 1011 bool (*get_slc_lr_present)(void *dev); 1012 uint32_t (*get_slc_lr_version)(void *dev); 1013 int (*slc_lr_rcp_flush)(void *dev, const struct slc_lr_func_s *slc_lr, int category, 1014 int cnt); 1015 1016 /* PDB */ 1017 bool (*get_pdb_present)(void *dev); 1018 uint32_t (*get_pdb_version)(void *dev); 1019 int (*pdb_rcp_flush)(void *dev, const struct pdb_func_s *pdb, int category, int cnt); 1020 int (*pdb_config_flush)(void *dev, const struct pdb_func_s *pdb); 1021 1022 /* TPE */ 1023 bool (*get_tpe_present)(void *dev); 1024 uint32_t (*get_tpe_version)(void *dev); 1025 int (*tpe_rpp_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 1026 int (*tpe_rpp_ifr_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 1027 int (*tpe_ifr_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 1028 int (*tpe_ins_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 1029 int (*tpe_rpl_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 1030 int (*tpe_rpl_ext_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 1031 int (*tpe_rpl_rpl_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 1032 int (*tpe_cpy_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 1033 int (*tpe_hfu_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 1034 int (*tpe_csu_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 1035 }; 1036 1037 struct flow_api_backend_s { 1038 void *be_dev; 1039 const struct flow_api_backend_ops *iface; 1040 1041 /* flow filter FPGA modules */ 1042 struct cat_func_s cat; 1043 struct km_func_s km; 1044 struct flm_func_s flm; 1045 struct hsh_func_s hsh; 1046 struct qsl_func_s qsl; 1047 struct slc_lr_func_s slc_lr; 1048 struct pdb_func_s pdb; 1049 struct tpe_func_s tpe; 1050 1051 /* NIC attributes */ 1052 unsigned int num_phy_ports; 1053 unsigned int num_rx_ports; 1054 1055 /* flow filter resource capacities */ 1056 unsigned int max_categories; 1057 unsigned int max_queues; 1058 }; 1059 1060 int flow_api_backend_init(struct flow_api_backend_s *dev, const struct flow_api_backend_ops *iface, 1061 void *be_dev); 1062 int flow_api_backend_done(struct flow_api_backend_s *dev); 1063 1064 #endif /* _HW_MOD_BACKEND_H_ */ 1065