1 /* 2 * SPDX-License-Identifier: BSD-3-Clause 3 * Copyright(c) 2023 Napatech A/S 4 */ 5 6 #ifndef _HW_MOD_BACKEND_H_ 7 #define _HW_MOD_BACKEND_H_ 8 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include "ntlog.h" 13 14 #include "hw_mod_cat_v18.h" 15 #include "hw_mod_cat_v21.h" 16 #include "hw_mod_flm_v25.h" 17 #include "hw_mod_km_v7.h" 18 #include "hw_mod_qsl_v7.h" 19 #include "hw_mod_pdb_v9.h" 20 #include "hw_mod_slc_lr_v2.h" 21 #include "hw_mod_hsh_v5.h" 22 #include "hw_mod_tpe_v3.h" 23 24 #define MAX_PHYS_ADAPTERS 8 25 26 #define VER_MAJOR(ver) (((ver) >> 16) & 0xffff) 27 #define VER_MINOR(ver) ((ver) & 0xffff) 28 29 struct flow_api_backend_s; 30 struct common_func_s; 31 32 void *callocate_mod(struct common_func_s *mod, int sets, ...); 33 void zero_module_cache(struct common_func_s *mod); 34 35 #define ALL_ENTRIES -1000 36 #define ALL_BANK_ENTRIES -1001 37 38 #define INDEX_TOO_LARGE (-2) 39 #define INDEX_TOO_LARGE_LOG NT_LOG(INF, FILTER, "ERROR:%s: Index too large", __func__) 40 41 #define WORD_OFF_TOO_LARGE (-3) 42 #define WORD_OFF_TOO_LARGE_LOG NT_LOG(INF, FILTER, "ERROR:%s: Word offset too large", __func__) 43 44 #define UNSUP_FIELD (-5) 45 #define UNSUP_FIELD_LOG \ 46 NT_LOG(INF, FILTER, "ERROR:%s: Unsupported field in NIC module", __func__) 47 48 #define UNSUP_VER (-4) 49 #define UNSUP_VER_LOG \ 50 NT_LOG(INF, FILTER, "ERROR:%s: Unsupported NIC module: %s ver %i.%i", __func__, _MOD_, \ 51 VER_MAJOR(_VER_), VER_MINOR(_VER_)) 52 53 #define COUNT_ERROR (-4) 54 #define COUNT_ERROR_LOG(_RESOURCE_) \ 55 NT_LOG(INF, FILTER, \ 56 "ERROR:%s: Insufficient resource [ %s ] : NIC module: %s ver %i.%i", __func__, \ 57 #_RESOURCE_, _MOD_, VER_MAJOR(_VER_), VER_MINOR(_VER_)) \ 58 59 #define NOT_FOUND 0xffffffff 60 61 enum { 62 EXTRA_INDEXES 63 }; 64 65 #define GET(cached_val, val) ({ *(val) = *(cached_val); }) 66 67 #define SET(cached_val, val) ({ *(cached_val) = *(val); }) 68 69 #define GET_SET(cached_val, val) \ 70 do { \ 71 uint32_t *temp_val = (val); \ 72 typeof(cached_val) *temp_cached_val = &(cached_val); \ 73 if (get) \ 74 GET(temp_cached_val, temp_val); \ 75 else \ 76 SET(temp_cached_val, temp_val); \ 77 } while (0) 78 79 #define GET_SIGNED(cached_val, val) ({ *(val) = (uint32_t)(*(cached_val)); }) 80 81 #define SET_SIGNED(cached_val, val) ({ *(cached_val) = (int32_t)(*(val)); }) 82 83 #define GET_SET_SIGNED(cached_val, val) \ 84 do { \ 85 uint32_t *temp_val = (val); \ 86 typeof(cached_val) *temp_cached_val = &(cached_val); \ 87 if (get) \ 88 GET_SIGNED(temp_cached_val, temp_val); \ 89 else \ 90 SET_SIGNED(temp_cached_val, temp_val); \ 91 } while (0) 92 93 #define FIND_EQUAL_INDEX(be_module_reg, type, idx, start, nb_elements) \ 94 do { \ 95 typeof(be_module_reg) *temp_be_module = \ 96 (typeof(be_module_reg) *)be_module_reg; \ 97 typeof(idx) tmp_idx = (idx); \ 98 typeof(nb_elements) tmp_nb_elements = (nb_elements); \ 99 unsigned int start_idx = (unsigned int)(start); \ 100 *value = NOT_FOUND; \ 101 for (unsigned int i = start_idx; i < tmp_nb_elements; i++) { \ 102 if ((unsigned int)(tmp_idx) == i) \ 103 continue; \ 104 if (memcmp(&temp_be_module[tmp_idx], &temp_be_module[i], sizeof(type)) == \ 105 0) { \ 106 *value = i; \ 107 break; \ 108 } \ 109 } \ 110 } while (0) 111 112 #define DO_COMPARE_INDEXS(be_module_reg, type, idx, cmp_idx) \ 113 do { \ 114 typeof(be_module_reg) *temp_be_module = &(be_module_reg); \ 115 typeof(idx) tmp_idx = (idx); \ 116 typeof(cmp_idx) tmp_cmp_idx = (cmp_idx); \ 117 if ((unsigned int)(tmp_idx) != (unsigned int)(tmp_cmp_idx)) { \ 118 (void)memcmp(temp_be_module + tmp_idx, &temp_be_module[tmp_cmp_idx], \ 119 sizeof(type)); \ 120 } \ 121 } while (0) 122 123 enum km_flm_if_select_e { 124 KM_FLM_IF_FIRST = 0, 125 KM_FLM_IF_SECOND = 1 126 }; 127 128 #define FIELD_START_INDEX 100 129 130 #define COMMON_FUNC_INFO_S \ 131 int ver; \ 132 void *base; \ 133 unsigned int alloced_size; \ 134 int debug 135 136 struct common_func_s { 137 COMMON_FUNC_INFO_S; 138 }; 139 140 struct cat_func_s { 141 COMMON_FUNC_INFO_S; 142 uint32_t nb_cat_funcs; 143 uint32_t nb_flow_types; 144 uint32_t nb_pm_ext; 145 uint32_t nb_len; 146 uint32_t kcc_size; 147 uint32_t cts_num; 148 uint32_t kcc_banks; 149 uint32_t kcc_id_bit_size; 150 uint32_t kcc_records; 151 uint32_t km_if_count; 152 int32_t km_if_m0; 153 int32_t km_if_m1; 154 155 union { 156 struct hw_mod_cat_v18_s v18; 157 struct hw_mod_cat_v21_s v21; 158 }; 159 }; 160 enum hw_cat_e { 161 /* 162 * functions initial CAT v18 163 */ 164 /* 00 */ HW_CAT_CFN_SET_ALL_DEFAULTS = 0, 165 /* 01 */ HW_CAT_CFN_PRESET_ALL, 166 /* 02 */ HW_CAT_CFN_COMPARE, 167 /* 03 */ HW_CAT_CFN_FIND, 168 /* 04 */ HW_CAT_CFN_COPY_FROM, 169 /* 05 */ HW_CAT_COT_PRESET_ALL, 170 /* 06 */ HW_CAT_COT_COMPARE, 171 /* 07 */ HW_CAT_COT_FIND, 172 /* 08 */ HW_CAT_COT_COPY_FROM, 173 /* fields */ 174 /* 00 */ HW_CAT_CFN_ENABLE = FIELD_START_INDEX, 175 /* 01 */ HW_CAT_CFN_INV, 176 /* 02 */ HW_CAT_CFN_PTC_INV, 177 /* 03 */ HW_CAT_CFN_PTC_ISL, 178 /* 04 */ HW_CAT_CFN_PTC_CFP, 179 /* 05 */ HW_CAT_CFN_PTC_MAC, 180 /* 06 */ HW_CAT_CFN_PTC_L2, 181 /* 07 */ HW_CAT_CFN_PTC_VNTAG, 182 /* 08 */ HW_CAT_CFN_PTC_VLAN, 183 /* 09 */ HW_CAT_CFN_PTC_MPLS, 184 /* 10 */ HW_CAT_CFN_PTC_L3, 185 /* 11 */ HW_CAT_CFN_PTC_FRAG, 186 /* 12 */ HW_CAT_CFN_PTC_IP_PROT, 187 /* 13 */ HW_CAT_CFN_PTC_L4, 188 /* 14 */ HW_CAT_CFN_PTC_TUNNEL, 189 /* 15 */ HW_CAT_CFN_PTC_TNL_L2, 190 /* 16 */ HW_CAT_CFN_PTC_TNL_VLAN, 191 /* 17 */ HW_CAT_CFN_PTC_TNL_MPLS, 192 /* 18 */ HW_CAT_CFN_PTC_TNL_L3, 193 /* 19 */ HW_CAT_CFN_PTC_TNL_FRAG, 194 /* 20 */ HW_CAT_CFN_PTC_TNL_IP_PROT, 195 /* 21 */ HW_CAT_CFN_PTC_TNL_L4, 196 /* 22 */ HW_CAT_CFN_ERR_INV, 197 /* 23 */ HW_CAT_CFN_ERR_CV, 198 /* 24 */ HW_CAT_CFN_ERR_FCS, 199 /* 25 */ HW_CAT_CFN_ERR_TRUNC, 200 /* 26 */ HW_CAT_CFN_ERR_L3_CS, 201 /* 27 */ HW_CAT_CFN_ERR_L4_CS, 202 /* 28 */ HW_CAT_CFN_MAC_PORT, 203 /* 29 */ HW_CAT_CFN_PM_CMP, 204 /* 30 */ HW_CAT_CFN_PM_DCT, 205 /* 31 */ HW_CAT_CFN_PM_EXT_INV, 206 /* 32 */ HW_CAT_CFN_PM_CMB, 207 /* 33 */ HW_CAT_CFN_PM_AND_INV, 208 /* 34 */ HW_CAT_CFN_PM_OR_INV, 209 /* 35 */ HW_CAT_CFN_PM_INV, 210 /* 36 */ HW_CAT_CFN_LC, 211 /* 37 */ HW_CAT_CFN_LC_INV, 212 /* 38 */ HW_CAT_CFN_KM0_OR, 213 /* 39 */ HW_CAT_CFN_KM1_OR, 214 /* 40 */ HW_CAT_KCE_ENABLE_BM, 215 /* 41 */ HW_CAT_KCS_CATEGORY, 216 /* 42 */ HW_CAT_FTE_ENABLE_BM, 217 /* 43 */ HW_CAT_CTE_ENABLE_BM, 218 /* 44 */ HW_CAT_CTS_CAT_A, 219 /* 45 */ HW_CAT_CTS_CAT_B, 220 /* 46 */ HW_CAT_COT_COLOR, 221 /* 47 */ HW_CAT_COT_KM, 222 /* 48 */ HW_CAT_CCT_COLOR, 223 /* 49 */ HW_CAT_CCT_KM, 224 /* 50 */ HW_CAT_KCC_KEY, 225 /* 51 */ HW_CAT_KCC_CATEGORY, 226 /* 52 */ HW_CAT_KCC_ID, 227 /* 53 */ HW_CAT_EXO_DYN, 228 /* 54 */ HW_CAT_EXO_OFS, 229 /* 55 */ HW_CAT_RCK_DATA, 230 /* 56 */ HW_CAT_LEN_LOWER, 231 /* 57 */ HW_CAT_LEN_UPPER, 232 /* 58 */ HW_CAT_LEN_DYN1, 233 /* 59 */ HW_CAT_LEN_DYN2, 234 /* 60 */ HW_CAT_LEN_INV, 235 /* 61 */ HW_CAT_CFN_ERR_TNL_L3_CS, 236 /* 62 */ HW_CAT_CFN_ERR_TNL_L4_CS, 237 /* 63 */ HW_CAT_CFN_ERR_TTL_EXP, 238 /* 64 */ HW_CAT_CFN_ERR_TNL_TTL_EXP, 239 }; 240 241 bool hw_mod_cat_present(struct flow_api_backend_s *be); 242 int hw_mod_cat_alloc(struct flow_api_backend_s *be); 243 void hw_mod_cat_free(struct flow_api_backend_s *be); 244 int hw_mod_cat_reset(struct flow_api_backend_s *be); 245 int hw_mod_cat_cfn_flush(struct flow_api_backend_s *be, int start_idx, int count); 246 int hw_mod_cat_cfn_set(struct flow_api_backend_s *be, enum hw_cat_e field, int index, int word_off, 247 uint32_t value); 248 249 int hw_mod_cat_cte_flush(struct flow_api_backend_s *be, int start_idx, int count); 250 int hw_mod_cat_cts_flush(struct flow_api_backend_s *be, int start_idx, int count); 251 int hw_mod_cat_cot_flush(struct flow_api_backend_s *be, int start_idx, int count); 252 int hw_mod_cat_cct_flush(struct flow_api_backend_s *be, int start_idx, int count); 253 int hw_mod_cat_kcc_flush(struct flow_api_backend_s *be, int start_idx, int count); 254 255 int hw_mod_cat_exo_flush(struct flow_api_backend_s *be, int start_idx, int count); 256 int hw_mod_cat_rck_flush(struct flow_api_backend_s *be, int start_idx, int count); 257 int hw_mod_cat_len_flush(struct flow_api_backend_s *be, int start_idx, int count); 258 259 struct km_func_s { 260 COMMON_FUNC_INFO_S; 261 uint32_t nb_categories; 262 uint32_t nb_cam_banks; 263 uint32_t nb_cam_record_words; 264 uint32_t nb_cam_records; 265 uint32_t nb_tcam_banks; 266 uint32_t nb_tcam_bank_width; 267 /* not read from backend, but rather set using version */ 268 uint32_t nb_km_rcp_mask_a_word_size; 269 /* --- || --- */ 270 uint32_t nb_km_rcp_mask_b_word_size; 271 union { 272 struct hw_mod_km_v7_s v7; 273 }; 274 }; 275 enum hw_km_e { 276 /* functions */ 277 HW_KM_RCP_PRESET_ALL = 0, 278 HW_KM_CAM_PRESET_ALL, 279 /* to sync and reset hw with cache - force write all entries in a bank */ 280 HW_KM_TCAM_BANK_RESET, 281 /* fields */ 282 HW_KM_RCP_QW0_DYN = FIELD_START_INDEX, 283 HW_KM_RCP_QW0_OFS, 284 HW_KM_RCP_QW0_SEL_A, 285 HW_KM_RCP_QW0_SEL_B, 286 HW_KM_RCP_QW4_DYN, 287 HW_KM_RCP_QW4_OFS, 288 HW_KM_RCP_QW4_SEL_A, 289 HW_KM_RCP_QW4_SEL_B, 290 HW_KM_RCP_DW8_DYN, 291 HW_KM_RCP_DW8_OFS, 292 HW_KM_RCP_DW8_SEL_A, 293 HW_KM_RCP_DW8_SEL_B, 294 HW_KM_RCP_DW10_DYN, 295 HW_KM_RCP_DW10_OFS, 296 HW_KM_RCP_DW10_SEL_A, 297 HW_KM_RCP_DW10_SEL_B, 298 HW_KM_RCP_SWX_CCH, 299 HW_KM_RCP_SWX_SEL_A, 300 HW_KM_RCP_SWX_SEL_B, 301 HW_KM_RCP_MASK_A, 302 HW_KM_RCP_MASK_B, 303 HW_KM_RCP_DUAL, 304 HW_KM_RCP_PAIRED, 305 HW_KM_RCP_EL_A, 306 HW_KM_RCP_EL_B, 307 HW_KM_RCP_INFO_A, 308 HW_KM_RCP_INFO_B, 309 HW_KM_RCP_FTM_A, 310 HW_KM_RCP_FTM_B, 311 HW_KM_RCP_BANK_A, 312 HW_KM_RCP_BANK_B, 313 HW_KM_RCP_KL_A, 314 HW_KM_RCP_KL_B, 315 HW_KM_RCP_KEYWAY_A, 316 HW_KM_RCP_KEYWAY_B, 317 HW_KM_RCP_SYNERGY_MODE, 318 HW_KM_RCP_DW0_B_DYN, 319 HW_KM_RCP_DW0_B_OFS, 320 HW_KM_RCP_DW2_B_DYN, 321 HW_KM_RCP_DW2_B_OFS, 322 HW_KM_RCP_SW4_B_DYN, 323 HW_KM_RCP_SW4_B_OFS, 324 HW_KM_RCP_SW5_B_DYN, 325 HW_KM_RCP_SW5_B_OFS, 326 HW_KM_CAM_W0, 327 HW_KM_CAM_W1, 328 HW_KM_CAM_W2, 329 HW_KM_CAM_W3, 330 HW_KM_CAM_W4, 331 HW_KM_CAM_W5, 332 HW_KM_CAM_FT0, 333 HW_KM_CAM_FT1, 334 HW_KM_CAM_FT2, 335 HW_KM_CAM_FT3, 336 HW_KM_CAM_FT4, 337 HW_KM_CAM_FT5, 338 HW_KM_TCAM_T, 339 HW_KM_TCI_COLOR, 340 HW_KM_TCI_FT, 341 HW_KM_TCQ_BANK_MASK, 342 HW_KM_TCQ_QUAL 343 }; 344 bool hw_mod_km_present(struct flow_api_backend_s *be); 345 int hw_mod_km_alloc(struct flow_api_backend_s *be); 346 void hw_mod_km_free(struct flow_api_backend_s *be); 347 int hw_mod_km_reset(struct flow_api_backend_s *be); 348 int hw_mod_km_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 349 int hw_mod_km_cam_flush(struct flow_api_backend_s *be, int start_bank, int start_record, 350 int count); 351 int hw_mod_km_tcam_flush(struct flow_api_backend_s *be, int start_bank, int count); 352 int hw_mod_km_tcam_set(struct flow_api_backend_s *be, enum hw_km_e field, int bank, int byte, 353 int byte_val, uint32_t *value_set); 354 int hw_mod_km_tci_flush(struct flow_api_backend_s *be, int start_bank, int start_record, 355 int count); 356 int hw_mod_km_tcq_flush(struct flow_api_backend_s *be, int start_bank, int start_record, 357 int count); 358 359 struct flm_func_s { 360 COMMON_FUNC_INFO_S; 361 uint32_t nb_categories; 362 uint32_t nb_size_mb; 363 uint32_t nb_entry_size; 364 uint32_t nb_variant; 365 uint32_t nb_prios; 366 uint32_t nb_pst_profiles; 367 uint32_t nb_scrub_profiles; 368 uint32_t nb_rpp_clock_in_ps; 369 uint32_t nb_load_aps_max; 370 union { 371 struct hw_mod_flm_v25_s v25; 372 }; 373 }; 374 enum hw_flm_e { 375 /* functions */ 376 HW_FLM_CONTROL_PRESET_ALL = 0, 377 HW_FLM_RCP_PRESET_ALL, 378 HW_FLM_FLOW_LRN_DATA, 379 HW_FLM_FLOW_INF_STA_DATA, 380 /* Control fields */ 381 HW_FLM_CONTROL_ENABLE = FIELD_START_INDEX, 382 HW_FLM_CONTROL_INIT, 383 HW_FLM_CONTROL_LDS, 384 HW_FLM_CONTROL_LFS, 385 HW_FLM_CONTROL_LIS, 386 HW_FLM_CONTROL_UDS, 387 HW_FLM_CONTROL_UIS, 388 HW_FLM_CONTROL_RDS, 389 HW_FLM_CONTROL_RIS, 390 HW_FLM_CONTROL_PDS, 391 HW_FLM_CONTROL_PIS, 392 HW_FLM_CONTROL_CRCWR, 393 HW_FLM_CONTROL_CRCRD, 394 HW_FLM_CONTROL_RBL, 395 HW_FLM_CONTROL_EAB, 396 HW_FLM_CONTROL_SPLIT_SDRAM_USAGE, 397 HW_FLM_STATUS_CALIB_SUCCESS, 398 HW_FLM_STATUS_CALIB_FAIL, 399 HW_FLM_STATUS_INITDONE, 400 HW_FLM_STATUS_IDLE, 401 HW_FLM_STATUS_CRITICAL, 402 HW_FLM_STATUS_PANIC, 403 HW_FLM_STATUS_CRCERR, 404 HW_FLM_STATUS_EFT_BP, 405 HW_FLM_STATUS_CACHE_BUFFER_CRITICAL, 406 HW_FLM_LOAD_BIN, 407 HW_FLM_LOAD_LPS, 408 HW_FLM_LOAD_APS, 409 HW_FLM_PRIO_LIMIT0, 410 HW_FLM_PRIO_FT0, 411 HW_FLM_PRIO_LIMIT1, 412 HW_FLM_PRIO_FT1, 413 HW_FLM_PRIO_LIMIT2, 414 HW_FLM_PRIO_FT2, 415 HW_FLM_PRIO_LIMIT3, 416 HW_FLM_PRIO_FT3, 417 HW_FLM_PST_PRESET_ALL, 418 HW_FLM_PST_BP, 419 HW_FLM_PST_PP, 420 HW_FLM_PST_TP, 421 HW_FLM_RCP_LOOKUP, 422 HW_FLM_RCP_QW0_DYN, 423 HW_FLM_RCP_QW0_OFS, 424 HW_FLM_RCP_QW0_SEL, 425 HW_FLM_RCP_QW4_DYN, 426 HW_FLM_RCP_QW4_OFS, 427 HW_FLM_RCP_SW8_DYN, 428 HW_FLM_RCP_SW8_OFS, 429 HW_FLM_RCP_SW8_SEL, 430 HW_FLM_RCP_SW9_DYN, 431 HW_FLM_RCP_SW9_OFS, 432 HW_FLM_RCP_MASK, 433 HW_FLM_RCP_KID, 434 HW_FLM_RCP_OPN, 435 HW_FLM_RCP_IPN, 436 HW_FLM_RCP_BYT_DYN, 437 HW_FLM_RCP_BYT_OFS, 438 HW_FLM_RCP_TXPLM, 439 HW_FLM_RCP_AUTO_IPV4_MASK, 440 HW_FLM_BUF_CTRL_LRN_FREE, 441 HW_FLM_BUF_CTRL_INF_AVAIL, 442 HW_FLM_BUF_CTRL_STA_AVAIL, 443 HW_FLM_STAT_LRN_DONE, 444 HW_FLM_STAT_LRN_IGNORE, 445 HW_FLM_STAT_LRN_FAIL, 446 HW_FLM_STAT_UNL_DONE, 447 HW_FLM_STAT_UNL_IGNORE, 448 HW_FLM_STAT_REL_DONE, 449 HW_FLM_STAT_REL_IGNORE, 450 HW_FLM_STAT_PRB_DONE, 451 HW_FLM_STAT_PRB_IGNORE, 452 HW_FLM_STAT_AUL_DONE, 453 HW_FLM_STAT_AUL_IGNORE, 454 HW_FLM_STAT_AUL_FAIL, 455 HW_FLM_STAT_TUL_DONE, 456 HW_FLM_STAT_FLOWS, 457 HW_FLM_STAT_STA_DONE, /* module ver 0.20 */ 458 HW_FLM_STAT_INF_DONE, /* module ver 0.20 */ 459 HW_FLM_STAT_INF_SKIP, /* module ver 0.20 */ 460 HW_FLM_STAT_PCK_HIT, /* module ver 0.20 */ 461 HW_FLM_STAT_PCK_MISS, /* module ver 0.20 */ 462 HW_FLM_STAT_PCK_UNH, /* module ver 0.20 */ 463 HW_FLM_STAT_PCK_DIS, /* module ver 0.20 */ 464 HW_FLM_STAT_CSH_HIT, /* module ver 0.20 */ 465 HW_FLM_STAT_CSH_MISS, /* module ver 0.20 */ 466 HW_FLM_STAT_CSH_UNH, /* module ver 0.20 */ 467 HW_FLM_STAT_CUC_START, /* module ver 0.20 */ 468 HW_FLM_STAT_CUC_MOVE, /* module ver 0.20 */ 469 HW_FLM_SCAN_I, /* module ver 0.22 */ 470 HW_FLM_SCRUB_PRESET_ALL, 471 HW_FLM_SCRUB_T, /* module ver 0.22 */ 472 HW_FLM_SCRUB_R, /* module ver 0.24 */ 473 HW_FLM_SCRUB_DEL, /* module ver 0.24 */ 474 HW_FLM_SCRUB_INF, /* module ver 0.24 */ 475 }; 476 477 bool hw_mod_flm_present(struct flow_api_backend_s *be); 478 int hw_mod_flm_alloc(struct flow_api_backend_s *be); 479 void hw_mod_flm_free(struct flow_api_backend_s *be); 480 int hw_mod_flm_reset(struct flow_api_backend_s *be); 481 482 int hw_mod_flm_control_flush(struct flow_api_backend_s *be); 483 int hw_mod_flm_control_set(struct flow_api_backend_s *be, enum hw_flm_e field, uint32_t value); 484 485 int hw_mod_flm_scan_flush(struct flow_api_backend_s *be); 486 487 int hw_mod_flm_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 488 489 int hw_mod_flm_scrub_flush(struct flow_api_backend_s *be, int start_idx, int count); 490 491 struct hsh_func_s { 492 COMMON_FUNC_INFO_S; 493 uint32_t nb_rcp;/* number of HSH recipes supported by FPGA */ 494 /* indication if Toeplitz is supported by FPGA, i.e. 0 - unsupported, 1 - supported */ 495 uint32_t toeplitz; 496 union { 497 struct hw_mod_hsh_v5_s v5; 498 }; 499 }; 500 enum hw_hsh_e { 501 /* functions */ 502 HW_HSH_RCP_PRESET_ALL = 0, 503 HW_HSH_RCP_COMPARE, 504 HW_HSH_RCP_FIND, 505 /* fields */ 506 HW_HSH_RCP_LOAD_DIST_TYPE = FIELD_START_INDEX, 507 HW_HSH_RCP_MAC_PORT_MASK, 508 HW_HSH_RCP_SORT, 509 HW_HSH_RCP_QW0_PE, 510 HW_HSH_RCP_QW0_OFS, 511 HW_HSH_RCP_QW4_PE, 512 HW_HSH_RCP_QW4_OFS, 513 HW_HSH_RCP_W8_PE, 514 HW_HSH_RCP_W8_OFS, 515 HW_HSH_RCP_W8_SORT, 516 HW_HSH_RCP_W9_PE, 517 HW_HSH_RCP_W9_OFS, 518 HW_HSH_RCP_W9_SORT, 519 HW_HSH_RCP_W9_P, 520 HW_HSH_RCP_P_MASK, 521 HW_HSH_RCP_WORD_MASK, 522 HW_HSH_RCP_SEED, 523 HW_HSH_RCP_TNL_P, 524 HW_HSH_RCP_HSH_VALID, 525 HW_HSH_RCP_HSH_TYPE, 526 HW_HSH_RCP_TOEPLITZ, 527 HW_HSH_RCP_K, 528 HW_HSH_RCP_AUTO_IPV4_MASK 529 }; 530 bool hw_mod_hsh_present(struct flow_api_backend_s *be); 531 int hw_mod_hsh_alloc(struct flow_api_backend_s *be); 532 void hw_mod_hsh_free(struct flow_api_backend_s *be); 533 int hw_mod_hsh_reset(struct flow_api_backend_s *be); 534 int hw_mod_hsh_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 535 536 struct qsl_func_s { 537 COMMON_FUNC_INFO_S; 538 uint32_t nb_rcp_categories; 539 uint32_t nb_qst_entries; 540 union { 541 struct hw_mod_qsl_v7_s v7; 542 }; 543 }; 544 enum hw_qsl_e { 545 /* functions */ 546 HW_QSL_RCP_PRESET_ALL = 0, 547 HW_QSL_RCP_COMPARE, 548 HW_QSL_RCP_FIND, 549 HW_QSL_QST_PRESET_ALL, 550 /* fields */ 551 HW_QSL_RCP_DISCARD = FIELD_START_INDEX, 552 HW_QSL_RCP_DROP, 553 HW_QSL_RCP_TBL_LO, 554 HW_QSL_RCP_TBL_HI, 555 HW_QSL_RCP_TBL_IDX, 556 HW_QSL_RCP_TBL_MSK, 557 HW_QSL_RCP_LR, 558 HW_QSL_RCP_TSA, 559 HW_QSL_RCP_VLI, 560 HW_QSL_QST_QUEUE, 561 HW_QSL_QST_EN, /* Alias: HW_QSL_QST_QEN */ 562 HW_QSL_QST_TX_PORT, 563 HW_QSL_QST_LRE, 564 HW_QSL_QST_TCI, 565 HW_QSL_QST_VEN, 566 HW_QSL_QEN_EN, 567 HW_QSL_UNMQ_DEST_QUEUE, 568 HW_QSL_UNMQ_EN, 569 }; 570 bool hw_mod_qsl_present(struct flow_api_backend_s *be); 571 int hw_mod_qsl_alloc(struct flow_api_backend_s *be); 572 void hw_mod_qsl_free(struct flow_api_backend_s *be); 573 int hw_mod_qsl_reset(struct flow_api_backend_s *be); 574 int hw_mod_qsl_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 575 int hw_mod_qsl_qst_flush(struct flow_api_backend_s *be, int start_idx, int count); 576 int hw_mod_qsl_qen_flush(struct flow_api_backend_s *be, int start_idx, int count); 577 int hw_mod_qsl_unmq_flush(struct flow_api_backend_s *be, int start_idx, int count); 578 int hw_mod_qsl_unmq_set(struct flow_api_backend_s *be, enum hw_qsl_e field, uint32_t index, 579 uint32_t value); 580 581 struct slc_lr_func_s { 582 COMMON_FUNC_INFO_S; 583 union { 584 struct hw_mod_slc_lr_v2_s v2; 585 }; 586 }; 587 enum hw_slc_lr_e { 588 /* functions */ 589 HW_SLC_LR_RCP_PRESET_ALL = 0, 590 HW_SLC_LR_RCP_COMPARE, 591 HW_SLC_LR_RCP_FIND, 592 /* fields */ 593 HW_SLC_LR_RCP_HEAD_SLC_EN = FIELD_START_INDEX, 594 HW_SLC_LR_RCP_HEAD_DYN, 595 HW_SLC_LR_RCP_HEAD_OFS, 596 HW_SLC_LR_RCP_TAIL_SLC_EN, 597 HW_SLC_LR_RCP_TAIL_DYN, 598 HW_SLC_LR_RCP_TAIL_OFS, 599 HW_SLC_LR_RCP_PCAP 600 }; 601 bool hw_mod_slc_lr_present(struct flow_api_backend_s *be); 602 int hw_mod_slc_lr_alloc(struct flow_api_backend_s *be); 603 void hw_mod_slc_lr_free(struct flow_api_backend_s *be); 604 int hw_mod_slc_lr_reset(struct flow_api_backend_s *be); 605 int hw_mod_slc_lr_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 606 607 struct pdb_func_s { 608 COMMON_FUNC_INFO_S; 609 uint32_t nb_pdb_rcp_categories; 610 611 union { 612 struct hw_mod_pdb_v9_s v9; 613 }; 614 }; 615 enum hw_pdb_e { 616 /* functions */ 617 HW_PDB_RCP_PRESET_ALL = 0, 618 HW_PDB_RCP_COMPARE, 619 HW_PDB_RCP_FIND, 620 /* fields */ 621 HW_PDB_RCP_DESCRIPTOR = FIELD_START_INDEX, 622 HW_PDB_RCP_DESC_LEN, 623 HW_PDB_RCP_TX_PORT, 624 HW_PDB_RCP_TX_IGNORE, 625 HW_PDB_RCP_TX_NOW, 626 HW_PDB_RCP_CRC_OVERWRITE, 627 HW_PDB_RCP_ALIGN, 628 HW_PDB_RCP_OFS0_DYN, 629 HW_PDB_RCP_OFS0_REL, 630 HW_PDB_RCP_OFS1_DYN, 631 HW_PDB_RCP_OFS1_REL, 632 HW_PDB_RCP_OFS2_DYN, 633 HW_PDB_RCP_OFS2_REL, 634 HW_PDB_RCP_IP_PROT_TNL, 635 HW_PDB_RCP_PPC_HSH, 636 HW_PDB_RCP_DUPLICATE_EN, 637 HW_PDB_RCP_DUPLICATE_BIT, 638 HW_PDB_RCP_PCAP_KEEP_FCS, 639 HW_PDB_CONFIG_TS_FORMAT, 640 HW_PDB_CONFIG_PORT_OFS, 641 }; 642 bool hw_mod_pdb_present(struct flow_api_backend_s *be); 643 int hw_mod_pdb_alloc(struct flow_api_backend_s *be); 644 void hw_mod_pdb_free(struct flow_api_backend_s *be); 645 int hw_mod_pdb_reset(struct flow_api_backend_s *be); 646 int hw_mod_pdb_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 647 int hw_mod_pdb_config_flush(struct flow_api_backend_s *be); 648 649 struct tpe_func_s { 650 COMMON_FUNC_INFO_S; 651 uint32_t nb_rcp_categories; 652 uint32_t nb_ifr_categories; 653 uint32_t nb_cpy_writers; 654 uint32_t nb_rpl_depth; 655 uint32_t nb_rpl_ext_categories; 656 union { 657 struct hw_mod_tpe_v3_s v3; 658 }; 659 }; 660 enum hw_tpe_e { 661 /* functions */ 662 HW_TPE_PRESET_ALL = 0, 663 HW_TPE_FIND, 664 HW_TPE_COMPARE, 665 /* Control fields */ 666 HW_TPE_RPP_RCP_EXP = FIELD_START_INDEX, 667 HW_TPE_IFR_RCP_IPV4_EN, 668 HW_TPE_IFR_RCP_IPV4_DF_DROP, 669 HW_TPE_IFR_RCP_IPV6_EN, 670 HW_TPE_IFR_RCP_IPV6_DROP, 671 HW_TPE_IFR_RCP_MTU, 672 HW_TPE_INS_RCP_DYN, 673 HW_TPE_INS_RCP_OFS, 674 HW_TPE_INS_RCP_LEN, 675 HW_TPE_RPL_RCP_DYN, 676 HW_TPE_RPL_RCP_OFS, 677 HW_TPE_RPL_RCP_LEN, 678 HW_TPE_RPL_RCP_RPL_PTR, 679 HW_TPE_RPL_RCP_EXT_PRIO, 680 HW_TPE_RPL_RCP_ETH_TYPE_WR, 681 HW_TPE_RPL_EXT_RPL_PTR, 682 HW_TPE_RPL_EXT_META_RPL_LEN, /* SW only */ 683 HW_TPE_RPL_RPL_VALUE, 684 HW_TPE_CPY_RCP_READER_SELECT, 685 HW_TPE_CPY_RCP_DYN, 686 HW_TPE_CPY_RCP_OFS, 687 HW_TPE_CPY_RCP_LEN, 688 HW_TPE_HFU_RCP_LEN_A_WR, 689 HW_TPE_HFU_RCP_LEN_A_OUTER_L4_LEN, 690 HW_TPE_HFU_RCP_LEN_A_POS_DYN, 691 HW_TPE_HFU_RCP_LEN_A_POS_OFS, 692 HW_TPE_HFU_RCP_LEN_A_ADD_DYN, 693 HW_TPE_HFU_RCP_LEN_A_ADD_OFS, 694 HW_TPE_HFU_RCP_LEN_A_SUB_DYN, 695 HW_TPE_HFU_RCP_LEN_B_WR, 696 HW_TPE_HFU_RCP_LEN_B_POS_DYN, 697 HW_TPE_HFU_RCP_LEN_B_POS_OFS, 698 HW_TPE_HFU_RCP_LEN_B_ADD_DYN, 699 HW_TPE_HFU_RCP_LEN_B_ADD_OFS, 700 HW_TPE_HFU_RCP_LEN_B_SUB_DYN, 701 HW_TPE_HFU_RCP_LEN_C_WR, 702 HW_TPE_HFU_RCP_LEN_C_POS_DYN, 703 HW_TPE_HFU_RCP_LEN_C_POS_OFS, 704 HW_TPE_HFU_RCP_LEN_C_ADD_DYN, 705 HW_TPE_HFU_RCP_LEN_C_ADD_OFS, 706 HW_TPE_HFU_RCP_LEN_C_SUB_DYN, 707 HW_TPE_HFU_RCP_TTL_WR, 708 HW_TPE_HFU_RCP_TTL_POS_DYN, 709 HW_TPE_HFU_RCP_TTL_POS_OFS, 710 HW_TPE_CSU_RCP_OUTER_L3_CMD, 711 HW_TPE_CSU_RCP_OUTER_L4_CMD, 712 HW_TPE_CSU_RCP_INNER_L3_CMD, 713 HW_TPE_CSU_RCP_INNER_L4_CMD, 714 }; 715 bool hw_mod_tpe_present(struct flow_api_backend_s *be); 716 int hw_mod_tpe_alloc(struct flow_api_backend_s *be); 717 void hw_mod_tpe_free(struct flow_api_backend_s *be); 718 int hw_mod_tpe_reset(struct flow_api_backend_s *be); 719 720 int hw_mod_tpe_rpp_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 721 722 int hw_mod_tpe_rpp_ifr_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 723 724 int hw_mod_tpe_ifr_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 725 726 int hw_mod_tpe_ins_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 727 728 int hw_mod_tpe_rpl_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 729 730 int hw_mod_tpe_rpl_ext_flush(struct flow_api_backend_s *be, int start_idx, int count); 731 732 int hw_mod_tpe_rpl_rpl_flush(struct flow_api_backend_s *be, int start_idx, int count); 733 734 int hw_mod_tpe_cpy_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 735 736 int hw_mod_tpe_hfu_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 737 738 int hw_mod_tpe_csu_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 739 740 enum debug_mode_e { 741 FLOW_BACKEND_DEBUG_MODE_NONE = 0x0000, 742 FLOW_BACKEND_DEBUG_MODE_WRITE = 0x0001 743 }; 744 745 struct flow_api_backend_ops { 746 int version; 747 int (*set_debug_mode)(void *dev, enum debug_mode_e mode); 748 int (*get_nb_phy_port)(void *dev); 749 int (*get_nb_rx_port)(void *dev); 750 int (*get_ltx_avail)(void *dev); 751 int (*get_nb_cat_funcs)(void *dev); 752 int (*get_nb_categories)(void *dev); 753 int (*get_nb_cat_km_if_cnt)(void *dev); 754 int (*get_nb_cat_km_if_m0)(void *dev); 755 int (*get_nb_cat_km_if_m1)(void *dev); 756 757 int (*get_nb_queues)(void *dev); 758 int (*get_nb_km_flow_types)(void *dev); 759 int (*get_nb_pm_ext)(void *dev); 760 int (*get_nb_len)(void *dev); 761 int (*get_kcc_size)(void *dev); 762 int (*get_kcc_banks)(void *dev); 763 int (*get_nb_km_categories)(void *dev); 764 int (*get_nb_km_cam_banks)(void *dev); 765 int (*get_nb_km_cam_record_words)(void *dev); 766 int (*get_nb_km_cam_records)(void *dev); 767 int (*get_nb_km_tcam_banks)(void *dev); 768 int (*get_nb_km_tcam_bank_width)(void *dev); 769 int (*get_nb_flm_categories)(void *dev); 770 int (*get_nb_flm_size_mb)(void *dev); 771 int (*get_nb_flm_entry_size)(void *dev); 772 int (*get_nb_flm_variant)(void *dev); 773 int (*get_nb_flm_prios)(void *dev); 774 int (*get_nb_flm_pst_profiles)(void *dev); 775 int (*get_nb_flm_scrub_profiles)(void *dev); 776 int (*get_nb_flm_load_aps_max)(void *dev); 777 int (*get_nb_qsl_categories)(void *dev); 778 int (*get_nb_qsl_qst_entries)(void *dev); 779 int (*get_nb_pdb_categories)(void *dev); 780 int (*get_nb_roa_categories)(void *dev); 781 int (*get_nb_tpe_categories)(void *dev); 782 int (*get_nb_tx_cpy_writers)(void *dev); 783 int (*get_nb_tx_cpy_mask_mem)(void *dev); 784 int (*get_nb_tx_rpl_depth)(void *dev); 785 int (*get_nb_tx_rpl_ext_categories)(void *dev); 786 int (*get_nb_tpe_ifr_categories)(void *dev); 787 int (*get_nb_rpp_per_ps)(void *dev); 788 int (*get_nb_hsh_categories)(void *dev); 789 int (*get_nb_hsh_toeplitz)(void *dev); 790 791 int (*alloc_rx_queue)(void *dev, int queue_id); 792 int (*free_rx_queue)(void *dev, int hw_queue); 793 794 /* CAT */ 795 bool (*get_cat_present)(void *dev); 796 uint32_t (*get_cat_version)(void *dev); 797 int (*cat_cfn_flush)(void *dev, const struct cat_func_s *cat, int cat_func, int cnt); 798 int (*cat_kce_flush)(void *dev, const struct cat_func_s *cat, int km_if_idx, int index, 799 int cnt); 800 int (*cat_kcs_flush)(void *dev, const struct cat_func_s *cat, int km_if_idx, int cat_func, 801 int cnt); 802 int (*cat_fte_flush)(void *dev, const struct cat_func_s *cat, int km_if_idx, int index, 803 int cnt); 804 int (*cat_cte_flush)(void *dev, const struct cat_func_s *cat, int cat_func, int cnt); 805 int (*cat_cts_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt); 806 int (*cat_cot_flush)(void *dev, const struct cat_func_s *cat, int cat_func, int cnt); 807 int (*cat_cct_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt); 808 int (*cat_exo_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt); 809 int (*cat_rck_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt); 810 int (*cat_len_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt); 811 int (*cat_kcc_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt); 812 813 /* KM */ 814 bool (*get_km_present)(void *dev); 815 uint32_t (*get_km_version)(void *dev); 816 int (*km_rcp_flush)(void *dev, const struct km_func_s *km, int category, int cnt); 817 int (*km_cam_flush)(void *dev, const struct km_func_s *km, int bank, int record, int cnt); 818 int (*km_tcam_flush)(void *dev, const struct km_func_s *km, int bank, int byte, int value, 819 int cnt); 820 int (*km_tci_flush)(void *dev, const struct km_func_s *km, int bank, int record, int cnt); 821 int (*km_tcq_flush)(void *dev, const struct km_func_s *km, int bank, int record, int cnt); 822 823 /* FLM */ 824 bool (*get_flm_present)(void *dev); 825 uint32_t (*get_flm_version)(void *dev); 826 int (*flm_control_flush)(void *dev, const struct flm_func_s *flm); 827 int (*flm_status_flush)(void *dev, const struct flm_func_s *flm); 828 int (*flm_status_update)(void *dev, const struct flm_func_s *flm); 829 int (*flm_scan_flush)(void *dev, const struct flm_func_s *flm); 830 int (*flm_load_bin_flush)(void *dev, const struct flm_func_s *flm); 831 int (*flm_prio_flush)(void *dev, const struct flm_func_s *flm); 832 int (*flm_pst_flush)(void *dev, const struct flm_func_s *flm, int index, int cnt); 833 int (*flm_rcp_flush)(void *dev, const struct flm_func_s *flm, int index, int cnt); 834 int (*flm_scrub_flush)(void *dev, const struct flm_func_s *flm, int index, int cnt); 835 int (*flm_buf_ctrl_update)(void *dev, const struct flm_func_s *flm); 836 int (*flm_stat_update)(void *dev, const struct flm_func_s *flm); 837 int (*flm_lrn_data_flush)(void *be_dev, const struct flm_func_s *flm, 838 const uint32_t *lrn_data, uint32_t records, 839 uint32_t *handled_records, uint32_t words_per_record, 840 uint32_t *inf_word_cnt, uint32_t *sta_word_cnt); 841 int (*flm_inf_sta_data_update)(void *be_dev, const struct flm_func_s *flm, 842 uint32_t *inf_data, uint32_t inf_size, 843 uint32_t *inf_word_cnt, uint32_t *sta_data, 844 uint32_t sta_size, uint32_t *sta_word_cnt); 845 846 /* HSH */ 847 bool (*get_hsh_present)(void *dev); 848 uint32_t (*get_hsh_version)(void *dev); 849 int (*hsh_rcp_flush)(void *dev, const struct hsh_func_s *hsh, int category, int cnt); 850 851 /* QSL */ 852 bool (*get_qsl_present)(void *dev); 853 uint32_t (*get_qsl_version)(void *dev); 854 int (*qsl_rcp_flush)(void *dev, const struct qsl_func_s *qsl, int category, int cnt); 855 int (*qsl_qst_flush)(void *dev, const struct qsl_func_s *qsl, int entry, int cnt); 856 int (*qsl_qen_flush)(void *dev, const struct qsl_func_s *qsl, int entry, int cnt); 857 int (*qsl_unmq_flush)(void *dev, const struct qsl_func_s *qsl, int entry, int cnt); 858 859 /* SLC LR */ 860 bool (*get_slc_lr_present)(void *dev); 861 uint32_t (*get_slc_lr_version)(void *dev); 862 int (*slc_lr_rcp_flush)(void *dev, const struct slc_lr_func_s *slc_lr, int category, 863 int cnt); 864 865 /* PDB */ 866 bool (*get_pdb_present)(void *dev); 867 uint32_t (*get_pdb_version)(void *dev); 868 int (*pdb_rcp_flush)(void *dev, const struct pdb_func_s *pdb, int category, int cnt); 869 int (*pdb_config_flush)(void *dev, const struct pdb_func_s *pdb); 870 871 /* TPE */ 872 bool (*get_tpe_present)(void *dev); 873 uint32_t (*get_tpe_version)(void *dev); 874 int (*tpe_rpp_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 875 int (*tpe_rpp_ifr_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 876 int (*tpe_ifr_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 877 int (*tpe_ins_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 878 int (*tpe_rpl_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 879 int (*tpe_rpl_ext_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 880 int (*tpe_rpl_rpl_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 881 int (*tpe_cpy_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 882 int (*tpe_hfu_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 883 int (*tpe_csu_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 884 }; 885 886 struct flow_api_backend_s { 887 void *be_dev; 888 const struct flow_api_backend_ops *iface; 889 890 /* flow filter FPGA modules */ 891 struct cat_func_s cat; 892 struct km_func_s km; 893 struct flm_func_s flm; 894 struct hsh_func_s hsh; 895 struct qsl_func_s qsl; 896 struct slc_lr_func_s slc_lr; 897 struct pdb_func_s pdb; 898 struct tpe_func_s tpe; 899 900 /* NIC attributes */ 901 unsigned int num_phy_ports; 902 unsigned int num_rx_ports; 903 904 /* flow filter resource capacities */ 905 unsigned int max_categories; 906 unsigned int max_queues; 907 }; 908 909 int flow_api_backend_init(struct flow_api_backend_s *dev, const struct flow_api_backend_ops *iface, 910 void *be_dev); 911 int flow_api_backend_done(struct flow_api_backend_s *dev); 912 913 #endif /* _HW_MOD_BACKEND_H_ */ 914