1 /* 2 * SPDX-License-Identifier: BSD-3-Clause 3 * Copyright(c) 2023 Napatech A/S 4 */ 5 6 #ifndef _HW_MOD_BACKEND_H_ 7 #define _HW_MOD_BACKEND_H_ 8 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include "ntlog.h" 13 14 #include "hw_mod_cat_v18.h" 15 #include "hw_mod_cat_v21.h" 16 #include "hw_mod_flm_v25.h" 17 #include "hw_mod_km_v7.h" 18 #include "hw_mod_qsl_v7.h" 19 #include "hw_mod_pdb_v9.h" 20 #include "hw_mod_slc_lr_v2.h" 21 #include "hw_mod_hsh_v5.h" 22 #include "hw_mod_tpe_v3.h" 23 24 #define MAX_PHYS_ADAPTERS 8 25 26 #define VER_MAJOR(ver) (((ver) >> 16) & 0xffff) 27 #define VER_MINOR(ver) ((ver) & 0xffff) 28 29 struct flow_api_backend_s; 30 struct common_func_s; 31 32 void *callocate_mod(struct common_func_s *mod, int sets, ...); 33 void zero_module_cache(struct common_func_s *mod); 34 35 #define ALL_ENTRIES -1000 36 #define ALL_BANK_ENTRIES -1001 37 38 #define INDEX_TOO_LARGE (-2) 39 #define INDEX_TOO_LARGE_LOG NT_LOG(INF, FILTER, "ERROR:%s: Index too large", __func__) 40 41 #define WORD_OFF_TOO_LARGE (-3) 42 #define WORD_OFF_TOO_LARGE_LOG NT_LOG(INF, FILTER, "ERROR:%s: Word offset too large", __func__) 43 44 #define UNSUP_FIELD (-5) 45 #define UNSUP_FIELD_LOG \ 46 NT_LOG(INF, FILTER, "ERROR:%s: Unsupported field in NIC module", __func__) 47 48 #define UNSUP_VER (-4) 49 #define UNSUP_VER_LOG \ 50 NT_LOG(INF, FILTER, "ERROR:%s: Unsupported NIC module: %s ver %i.%i", __func__, _MOD_, \ 51 VER_MAJOR(_VER_), VER_MINOR(_VER_)) 52 53 #define COUNT_ERROR (-4) 54 #define COUNT_ERROR_LOG(_RESOURCE_) \ 55 NT_LOG(INF, FILTER, \ 56 "ERROR:%s: Insufficient resource [ %s ] : NIC module: %s ver %i.%i", __func__, \ 57 #_RESOURCE_, _MOD_, VER_MAJOR(_VER_), VER_MINOR(_VER_)) \ 58 59 #define NOT_FOUND 0xffffffff 60 61 enum { 62 EXTRA_INDEXES 63 }; 64 65 #define GET(cached_val, val) ({ *(val) = *(cached_val); }) 66 67 #define SET(cached_val, val) ({ *(cached_val) = *(val); }) 68 69 #define GET_SET(cached_val, val) \ 70 do { \ 71 uint32_t *temp_val = (val); \ 72 typeof(cached_val) *temp_cached_val = &(cached_val); \ 73 if (get) \ 74 GET(temp_cached_val, temp_val); \ 75 else \ 76 SET(temp_cached_val, temp_val); \ 77 } while (0) 78 79 #define GET_SIGNED(cached_val, val) ({ *(val) = (uint32_t)(*(cached_val)); }) 80 81 #define SET_SIGNED(cached_val, val) ({ *(cached_val) = (int32_t)(*(val)); }) 82 83 #define GET_SET_SIGNED(cached_val, val) \ 84 do { \ 85 uint32_t *temp_val = (val); \ 86 typeof(cached_val) *temp_cached_val = &(cached_val); \ 87 if (get) \ 88 GET_SIGNED(temp_cached_val, temp_val); \ 89 else \ 90 SET_SIGNED(temp_cached_val, temp_val); \ 91 } while (0) 92 93 #define FIND_EQUAL_INDEX(be_module_reg, type, idx, start, nb_elements) \ 94 do { \ 95 typeof(be_module_reg) *temp_be_module = \ 96 (typeof(be_module_reg) *)be_module_reg; \ 97 typeof(idx) tmp_idx = (idx); \ 98 typeof(nb_elements) tmp_nb_elements = (nb_elements); \ 99 unsigned int start_idx = (unsigned int)(start); \ 100 *value = NOT_FOUND; \ 101 for (unsigned int i = start_idx; i < tmp_nb_elements; i++) { \ 102 if ((unsigned int)(tmp_idx) == i) \ 103 continue; \ 104 if (memcmp(&temp_be_module[tmp_idx], &temp_be_module[i], sizeof(type)) == \ 105 0) { \ 106 *value = i; \ 107 break; \ 108 } \ 109 } \ 110 } while (0) 111 112 #define DO_COMPARE_INDEXS(be_module_reg, type, idx, cmp_idx) \ 113 do { \ 114 typeof(be_module_reg) *temp_be_module = &(be_module_reg); \ 115 typeof(idx) tmp_idx = (idx); \ 116 typeof(cmp_idx) tmp_cmp_idx = (cmp_idx); \ 117 if ((unsigned int)(tmp_idx) != (unsigned int)(tmp_cmp_idx)) { \ 118 (void)memcmp(temp_be_module + tmp_idx, &temp_be_module[tmp_cmp_idx], \ 119 sizeof(type)); \ 120 } \ 121 } while (0) 122 123 static inline int is_non_zero(const void *addr, size_t n) 124 { 125 size_t i = 0; 126 const uint8_t *p = (const uint8_t *)addr; 127 128 for (i = 0; i < n; i++) 129 if (p[i] != 0) 130 return 1; 131 132 return 0; 133 } 134 135 /* Sideband info bit indicator */ 136 #define SWX_INFO (1 << 6) 137 138 enum km_flm_if_select_e { 139 KM_FLM_IF_FIRST = 0, 140 KM_FLM_IF_SECOND = 1 141 }; 142 143 #define FIELD_START_INDEX 100 144 145 #define COMMON_FUNC_INFO_S \ 146 int ver; \ 147 void *base; \ 148 unsigned int alloced_size; \ 149 int debug 150 151 enum frame_offs_e { 152 DYN_SOF = 0, 153 DYN_L2 = 1, 154 DYN_FIRST_VLAN = 2, 155 DYN_MPLS = 3, 156 DYN_L3 = 4, 157 DYN_ID_IPV4_6 = 5, 158 DYN_FINAL_IP_DST = 6, 159 DYN_L4 = 7, 160 DYN_L4_PAYLOAD = 8, 161 DYN_TUN_PAYLOAD = 9, 162 DYN_TUN_L2 = 10, 163 DYN_TUN_VLAN = 11, 164 DYN_TUN_MPLS = 12, 165 DYN_TUN_L3 = 13, 166 DYN_TUN_ID_IPV4_6 = 14, 167 DYN_TUN_FINAL_IP_DST = 15, 168 DYN_TUN_L4 = 16, 169 DYN_TUN_L4_PAYLOAD = 17, 170 DYN_EOF = 18, 171 DYN_L3_PAYLOAD_END = 19, 172 DYN_TUN_L3_PAYLOAD_END = 20, 173 SB_VNI = SWX_INFO | 1, 174 SB_MAC_PORT = SWX_INFO | 2, 175 SB_KCC_ID = SWX_INFO | 3 176 }; 177 178 enum { 179 QW0_SEL_EXCLUDE = 0, 180 QW0_SEL_FIRST32 = 1, 181 QW0_SEL_FIRST64 = 3, 182 QW0_SEL_ALL128 = 4, 183 }; 184 185 enum { 186 QW4_SEL_EXCLUDE = 0, 187 QW4_SEL_FIRST32 = 1, 188 QW4_SEL_FIRST64 = 2, 189 QW4_SEL_ALL128 = 3, 190 }; 191 192 enum { 193 DW8_SEL_EXCLUDE = 0, 194 DW8_SEL_FIRST32 = 3, 195 }; 196 197 enum { 198 DW10_SEL_EXCLUDE = 0, 199 DW10_SEL_FIRST32 = 2, 200 }; 201 202 enum { 203 SWX_SEL_EXCLUDE = 0, 204 SWX_SEL_ALL32 = 1, 205 }; 206 207 enum { 208 PROT_OTHER = 0, 209 PROT_L2_ETH2 = 1, 210 }; 211 212 enum { 213 PROT_L3_IPV4 = 1, 214 PROT_L3_IPV6 = 2 215 }; 216 217 enum { 218 PROT_L4_TCP = 1, 219 PROT_L4_UDP = 2, 220 PROT_L4_SCTP = 3, 221 PROT_L4_ICMP = 4 222 }; 223 224 enum { 225 PROT_TUN_GTPV1U = 6, 226 }; 227 228 enum { 229 PROT_TUN_L3_OTHER = 0, 230 PROT_TUN_L3_IPV4 = 1, 231 PROT_TUN_L3_IPV6 = 2 232 }; 233 234 enum { 235 PROT_TUN_L4_OTHER = 0, 236 PROT_TUN_L4_TCP = 1, 237 PROT_TUN_L4_UDP = 2, 238 PROT_TUN_L4_SCTP = 3, 239 PROT_TUN_L4_ICMP = 4 240 }; 241 242 243 enum { 244 HASH_HASH_NONE = 0, 245 HASH_5TUPLE = 8, 246 }; 247 248 enum { 249 CPY_SELECT_DSCP_IPV4 = 0, 250 CPY_SELECT_DSCP_IPV6 = 1, 251 CPY_SELECT_RQI_QFI = 2, 252 CPY_SELECT_IPV4 = 3, 253 CPY_SELECT_PORT = 4, 254 CPY_SELECT_TEID = 5, 255 }; 256 257 struct common_func_s { 258 COMMON_FUNC_INFO_S; 259 }; 260 261 struct cat_func_s { 262 COMMON_FUNC_INFO_S; 263 uint32_t nb_cat_funcs; 264 uint32_t nb_flow_types; 265 uint32_t nb_pm_ext; 266 uint32_t nb_len; 267 uint32_t kcc_size; 268 uint32_t cts_num; 269 uint32_t kcc_banks; 270 uint32_t kcc_id_bit_size; 271 uint32_t kcc_records; 272 uint32_t km_if_count; 273 int32_t km_if_m0; 274 int32_t km_if_m1; 275 276 union { 277 struct hw_mod_cat_v18_s v18; 278 struct hw_mod_cat_v21_s v21; 279 }; 280 }; 281 enum hw_cat_e { 282 /* 283 * functions initial CAT v18 284 */ 285 /* 00 */ HW_CAT_CFN_SET_ALL_DEFAULTS = 0, 286 /* 01 */ HW_CAT_CFN_PRESET_ALL, 287 /* 02 */ HW_CAT_CFN_COMPARE, 288 /* 03 */ HW_CAT_CFN_FIND, 289 /* 04 */ HW_CAT_CFN_COPY_FROM, 290 /* 05 */ HW_CAT_COT_PRESET_ALL, 291 /* 06 */ HW_CAT_COT_COMPARE, 292 /* 07 */ HW_CAT_COT_FIND, 293 /* 08 */ HW_CAT_COT_COPY_FROM, 294 /* fields */ 295 /* 00 */ HW_CAT_CFN_ENABLE = FIELD_START_INDEX, 296 /* 01 */ HW_CAT_CFN_INV, 297 /* 02 */ HW_CAT_CFN_PTC_INV, 298 /* 03 */ HW_CAT_CFN_PTC_ISL, 299 /* 04 */ HW_CAT_CFN_PTC_CFP, 300 /* 05 */ HW_CAT_CFN_PTC_MAC, 301 /* 06 */ HW_CAT_CFN_PTC_L2, 302 /* 07 */ HW_CAT_CFN_PTC_VNTAG, 303 /* 08 */ HW_CAT_CFN_PTC_VLAN, 304 /* 09 */ HW_CAT_CFN_PTC_MPLS, 305 /* 10 */ HW_CAT_CFN_PTC_L3, 306 /* 11 */ HW_CAT_CFN_PTC_FRAG, 307 /* 12 */ HW_CAT_CFN_PTC_IP_PROT, 308 /* 13 */ HW_CAT_CFN_PTC_L4, 309 /* 14 */ HW_CAT_CFN_PTC_TUNNEL, 310 /* 15 */ HW_CAT_CFN_PTC_TNL_L2, 311 /* 16 */ HW_CAT_CFN_PTC_TNL_VLAN, 312 /* 17 */ HW_CAT_CFN_PTC_TNL_MPLS, 313 /* 18 */ HW_CAT_CFN_PTC_TNL_L3, 314 /* 19 */ HW_CAT_CFN_PTC_TNL_FRAG, 315 /* 20 */ HW_CAT_CFN_PTC_TNL_IP_PROT, 316 /* 21 */ HW_CAT_CFN_PTC_TNL_L4, 317 /* 22 */ HW_CAT_CFN_ERR_INV, 318 /* 23 */ HW_CAT_CFN_ERR_CV, 319 /* 24 */ HW_CAT_CFN_ERR_FCS, 320 /* 25 */ HW_CAT_CFN_ERR_TRUNC, 321 /* 26 */ HW_CAT_CFN_ERR_L3_CS, 322 /* 27 */ HW_CAT_CFN_ERR_L4_CS, 323 /* 28 */ HW_CAT_CFN_MAC_PORT, 324 /* 29 */ HW_CAT_CFN_PM_CMP, 325 /* 30 */ HW_CAT_CFN_PM_DCT, 326 /* 31 */ HW_CAT_CFN_PM_EXT_INV, 327 /* 32 */ HW_CAT_CFN_PM_CMB, 328 /* 33 */ HW_CAT_CFN_PM_AND_INV, 329 /* 34 */ HW_CAT_CFN_PM_OR_INV, 330 /* 35 */ HW_CAT_CFN_PM_INV, 331 /* 36 */ HW_CAT_CFN_LC, 332 /* 37 */ HW_CAT_CFN_LC_INV, 333 /* 38 */ HW_CAT_CFN_KM0_OR, 334 /* 39 */ HW_CAT_CFN_KM1_OR, 335 /* 40 */ HW_CAT_KCE_ENABLE_BM, 336 /* 41 */ HW_CAT_KCS_CATEGORY, 337 /* 42 */ HW_CAT_FTE_ENABLE_BM, 338 /* 43 */ HW_CAT_CTE_ENABLE_BM, 339 /* 44 */ HW_CAT_CTS_CAT_A, 340 /* 45 */ HW_CAT_CTS_CAT_B, 341 /* 46 */ HW_CAT_COT_COLOR, 342 /* 47 */ HW_CAT_COT_KM, 343 /* 48 */ HW_CAT_CCT_COLOR, 344 /* 49 */ HW_CAT_CCT_KM, 345 /* 50 */ HW_CAT_KCC_KEY, 346 /* 51 */ HW_CAT_KCC_CATEGORY, 347 /* 52 */ HW_CAT_KCC_ID, 348 /* 53 */ HW_CAT_EXO_DYN, 349 /* 54 */ HW_CAT_EXO_OFS, 350 /* 55 */ HW_CAT_RCK_DATA, 351 /* 56 */ HW_CAT_LEN_LOWER, 352 /* 57 */ HW_CAT_LEN_UPPER, 353 /* 58 */ HW_CAT_LEN_DYN1, 354 /* 59 */ HW_CAT_LEN_DYN2, 355 /* 60 */ HW_CAT_LEN_INV, 356 /* 61 */ HW_CAT_CFN_ERR_TNL_L3_CS, 357 /* 62 */ HW_CAT_CFN_ERR_TNL_L4_CS, 358 /* 63 */ HW_CAT_CFN_ERR_TTL_EXP, 359 /* 64 */ HW_CAT_CFN_ERR_TNL_TTL_EXP, 360 }; 361 362 bool hw_mod_cat_present(struct flow_api_backend_s *be); 363 int hw_mod_cat_alloc(struct flow_api_backend_s *be); 364 void hw_mod_cat_free(struct flow_api_backend_s *be); 365 int hw_mod_cat_reset(struct flow_api_backend_s *be); 366 int hw_mod_cat_cfn_flush(struct flow_api_backend_s *be, int start_idx, int count); 367 int hw_mod_cat_cfn_set(struct flow_api_backend_s *be, enum hw_cat_e field, int index, int word_off, 368 uint32_t value); 369 /* KCE/KCS/FTE KM */ 370 int hw_mod_cat_fte_km_flush(struct flow_api_backend_s *be, enum km_flm_if_select_e if_num, 371 int start_idx, int count); 372 int hw_mod_cat_fte_km_set(struct flow_api_backend_s *be, enum hw_cat_e field, 373 enum km_flm_if_select_e if_num, int index, uint32_t value); 374 int hw_mod_cat_fte_km_get(struct flow_api_backend_s *be, enum hw_cat_e field, 375 enum km_flm_if_select_e if_num, int index, uint32_t *value); 376 /* KCE/KCS/FTE FLM */ 377 int hw_mod_cat_fte_flm_flush(struct flow_api_backend_s *be, enum km_flm_if_select_e if_num, 378 int start_idx, int count); 379 int hw_mod_cat_fte_flm_set(struct flow_api_backend_s *be, enum hw_cat_e field, 380 enum km_flm_if_select_e if_num, int index, uint32_t value); 381 int hw_mod_cat_fte_flm_get(struct flow_api_backend_s *be, enum hw_cat_e field, 382 enum km_flm_if_select_e if_num, int index, uint32_t *value); 383 384 int hw_mod_cat_cte_flush(struct flow_api_backend_s *be, int start_idx, int count); 385 int hw_mod_cat_cte_set(struct flow_api_backend_s *be, enum hw_cat_e field, int index, 386 uint32_t value); 387 388 int hw_mod_cat_cts_flush(struct flow_api_backend_s *be, int start_idx, int count); 389 int hw_mod_cat_cts_set(struct flow_api_backend_s *be, enum hw_cat_e field, int index, 390 uint32_t value); 391 392 int hw_mod_cat_cot_flush(struct flow_api_backend_s *be, int start_idx, int count); 393 int hw_mod_cat_cot_set(struct flow_api_backend_s *be, enum hw_cat_e field, int index, 394 uint32_t value); 395 396 int hw_mod_cat_cct_flush(struct flow_api_backend_s *be, int start_idx, int count); 397 398 int hw_mod_cat_kcc_flush(struct flow_api_backend_s *be, int start_idx, int count); 399 400 int hw_mod_cat_exo_flush(struct flow_api_backend_s *be, int start_idx, int count); 401 int hw_mod_cat_rck_flush(struct flow_api_backend_s *be, int start_idx, int count); 402 int hw_mod_cat_len_flush(struct flow_api_backend_s *be, int start_idx, int count); 403 404 struct km_func_s { 405 COMMON_FUNC_INFO_S; 406 uint32_t nb_categories; 407 uint32_t nb_cam_banks; 408 uint32_t nb_cam_record_words; 409 uint32_t nb_cam_records; 410 uint32_t nb_tcam_banks; 411 uint32_t nb_tcam_bank_width; 412 /* not read from backend, but rather set using version */ 413 uint32_t nb_km_rcp_mask_a_word_size; 414 /* --- || --- */ 415 uint32_t nb_km_rcp_mask_b_word_size; 416 union { 417 struct hw_mod_km_v7_s v7; 418 }; 419 }; 420 enum hw_km_e { 421 /* functions */ 422 HW_KM_RCP_PRESET_ALL = 0, 423 HW_KM_CAM_PRESET_ALL, 424 /* to sync and reset hw with cache - force write all entries in a bank */ 425 HW_KM_TCAM_BANK_RESET, 426 /* fields */ 427 HW_KM_RCP_QW0_DYN = FIELD_START_INDEX, 428 HW_KM_RCP_QW0_OFS, 429 HW_KM_RCP_QW0_SEL_A, 430 HW_KM_RCP_QW0_SEL_B, 431 HW_KM_RCP_QW4_DYN, 432 HW_KM_RCP_QW4_OFS, 433 HW_KM_RCP_QW4_SEL_A, 434 HW_KM_RCP_QW4_SEL_B, 435 HW_KM_RCP_DW8_DYN, 436 HW_KM_RCP_DW8_OFS, 437 HW_KM_RCP_DW8_SEL_A, 438 HW_KM_RCP_DW8_SEL_B, 439 HW_KM_RCP_DW10_DYN, 440 HW_KM_RCP_DW10_OFS, 441 HW_KM_RCP_DW10_SEL_A, 442 HW_KM_RCP_DW10_SEL_B, 443 HW_KM_RCP_SWX_CCH, 444 HW_KM_RCP_SWX_SEL_A, 445 HW_KM_RCP_SWX_SEL_B, 446 HW_KM_RCP_MASK_A, 447 HW_KM_RCP_MASK_B, 448 HW_KM_RCP_DUAL, 449 HW_KM_RCP_PAIRED, 450 HW_KM_RCP_EL_A, 451 HW_KM_RCP_EL_B, 452 HW_KM_RCP_INFO_A, 453 HW_KM_RCP_INFO_B, 454 HW_KM_RCP_FTM_A, 455 HW_KM_RCP_FTM_B, 456 HW_KM_RCP_BANK_A, 457 HW_KM_RCP_BANK_B, 458 HW_KM_RCP_KL_A, 459 HW_KM_RCP_KL_B, 460 HW_KM_RCP_KEYWAY_A, 461 HW_KM_RCP_KEYWAY_B, 462 HW_KM_RCP_SYNERGY_MODE, 463 HW_KM_RCP_DW0_B_DYN, 464 HW_KM_RCP_DW0_B_OFS, 465 HW_KM_RCP_DW2_B_DYN, 466 HW_KM_RCP_DW2_B_OFS, 467 HW_KM_RCP_SW4_B_DYN, 468 HW_KM_RCP_SW4_B_OFS, 469 HW_KM_RCP_SW5_B_DYN, 470 HW_KM_RCP_SW5_B_OFS, 471 HW_KM_CAM_W0, 472 HW_KM_CAM_W1, 473 HW_KM_CAM_W2, 474 HW_KM_CAM_W3, 475 HW_KM_CAM_W4, 476 HW_KM_CAM_W5, 477 HW_KM_CAM_FT0, 478 HW_KM_CAM_FT1, 479 HW_KM_CAM_FT2, 480 HW_KM_CAM_FT3, 481 HW_KM_CAM_FT4, 482 HW_KM_CAM_FT5, 483 HW_KM_TCAM_T, 484 HW_KM_TCI_COLOR, 485 HW_KM_TCI_FT, 486 HW_KM_TCQ_BANK_MASK, 487 HW_KM_TCQ_QUAL 488 }; 489 bool hw_mod_km_present(struct flow_api_backend_s *be); 490 int hw_mod_km_alloc(struct flow_api_backend_s *be); 491 void hw_mod_km_free(struct flow_api_backend_s *be); 492 int hw_mod_km_reset(struct flow_api_backend_s *be); 493 int hw_mod_km_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 494 int hw_mod_km_rcp_set(struct flow_api_backend_s *be, enum hw_km_e field, int index, int word_off, 495 uint32_t value); 496 int hw_mod_km_rcp_get(struct flow_api_backend_s *be, enum hw_km_e field, int index, int word_off, 497 uint32_t *value); 498 int hw_mod_km_cam_flush(struct flow_api_backend_s *be, int start_bank, int start_record, 499 int count); 500 int hw_mod_km_cam_set(struct flow_api_backend_s *be, enum hw_km_e field, int bank, int record, 501 uint32_t value); 502 503 int hw_mod_km_tcam_flush(struct flow_api_backend_s *be, int start_bank, int count); 504 int hw_mod_km_tcam_set(struct flow_api_backend_s *be, enum hw_km_e field, int bank, int byte, 505 int byte_val, uint32_t *value_set); 506 int hw_mod_km_tcam_get(struct flow_api_backend_s *be, enum hw_km_e field, int bank, int byte, 507 int byte_val, uint32_t *value_set); 508 int hw_mod_km_tci_flush(struct flow_api_backend_s *be, int start_bank, int start_record, 509 int count); 510 int hw_mod_km_tci_set(struct flow_api_backend_s *be, enum hw_km_e field, int bank, int record, 511 uint32_t value); 512 int hw_mod_km_tcq_flush(struct flow_api_backend_s *be, int start_bank, int start_record, 513 int count); 514 515 struct flm_func_s { 516 COMMON_FUNC_INFO_S; 517 uint32_t nb_categories; 518 uint32_t nb_size_mb; 519 uint32_t nb_entry_size; 520 uint32_t nb_variant; 521 uint32_t nb_prios; 522 uint32_t nb_pst_profiles; 523 uint32_t nb_scrub_profiles; 524 uint32_t nb_rpp_clock_in_ps; 525 uint32_t nb_load_aps_max; 526 union { 527 struct hw_mod_flm_v25_s v25; 528 }; 529 }; 530 enum hw_flm_e { 531 /* functions */ 532 HW_FLM_CONTROL_PRESET_ALL = 0, 533 HW_FLM_RCP_PRESET_ALL, 534 HW_FLM_FLOW_LRN_DATA, 535 HW_FLM_FLOW_INF_STA_DATA, 536 /* Control fields */ 537 HW_FLM_CONTROL_ENABLE = FIELD_START_INDEX, 538 HW_FLM_CONTROL_INIT, 539 HW_FLM_CONTROL_LDS, 540 HW_FLM_CONTROL_LFS, 541 HW_FLM_CONTROL_LIS, 542 HW_FLM_CONTROL_UDS, 543 HW_FLM_CONTROL_UIS, 544 HW_FLM_CONTROL_RDS, 545 HW_FLM_CONTROL_RIS, 546 HW_FLM_CONTROL_PDS, 547 HW_FLM_CONTROL_PIS, 548 HW_FLM_CONTROL_CRCWR, 549 HW_FLM_CONTROL_CRCRD, 550 HW_FLM_CONTROL_RBL, 551 HW_FLM_CONTROL_EAB, 552 HW_FLM_CONTROL_SPLIT_SDRAM_USAGE, 553 HW_FLM_STATUS_CALIB_SUCCESS, 554 HW_FLM_STATUS_CALIB_FAIL, 555 HW_FLM_STATUS_INITDONE, 556 HW_FLM_STATUS_IDLE, 557 HW_FLM_STATUS_CRITICAL, 558 HW_FLM_STATUS_PANIC, 559 HW_FLM_STATUS_CRCERR, 560 HW_FLM_STATUS_EFT_BP, 561 HW_FLM_STATUS_CACHE_BUFFER_CRITICAL, 562 HW_FLM_LOAD_BIN, 563 HW_FLM_LOAD_LPS, 564 HW_FLM_LOAD_APS, 565 HW_FLM_PRIO_LIMIT0, 566 HW_FLM_PRIO_FT0, 567 HW_FLM_PRIO_LIMIT1, 568 HW_FLM_PRIO_FT1, 569 HW_FLM_PRIO_LIMIT2, 570 HW_FLM_PRIO_FT2, 571 HW_FLM_PRIO_LIMIT3, 572 HW_FLM_PRIO_FT3, 573 HW_FLM_PST_PRESET_ALL, 574 HW_FLM_PST_BP, 575 HW_FLM_PST_PP, 576 HW_FLM_PST_TP, 577 HW_FLM_RCP_LOOKUP, 578 HW_FLM_RCP_QW0_DYN, 579 HW_FLM_RCP_QW0_OFS, 580 HW_FLM_RCP_QW0_SEL, 581 HW_FLM_RCP_QW4_DYN, 582 HW_FLM_RCP_QW4_OFS, 583 HW_FLM_RCP_SW8_DYN, 584 HW_FLM_RCP_SW8_OFS, 585 HW_FLM_RCP_SW8_SEL, 586 HW_FLM_RCP_SW9_DYN, 587 HW_FLM_RCP_SW9_OFS, 588 HW_FLM_RCP_MASK, 589 HW_FLM_RCP_KID, 590 HW_FLM_RCP_OPN, 591 HW_FLM_RCP_IPN, 592 HW_FLM_RCP_BYT_DYN, 593 HW_FLM_RCP_BYT_OFS, 594 HW_FLM_RCP_TXPLM, 595 HW_FLM_RCP_AUTO_IPV4_MASK, 596 HW_FLM_BUF_CTRL_LRN_FREE, 597 HW_FLM_BUF_CTRL_INF_AVAIL, 598 HW_FLM_BUF_CTRL_STA_AVAIL, 599 HW_FLM_STAT_LRN_DONE, 600 HW_FLM_STAT_LRN_IGNORE, 601 HW_FLM_STAT_LRN_FAIL, 602 HW_FLM_STAT_UNL_DONE, 603 HW_FLM_STAT_UNL_IGNORE, 604 HW_FLM_STAT_REL_DONE, 605 HW_FLM_STAT_REL_IGNORE, 606 HW_FLM_STAT_PRB_DONE, 607 HW_FLM_STAT_PRB_IGNORE, 608 HW_FLM_STAT_AUL_DONE, 609 HW_FLM_STAT_AUL_IGNORE, 610 HW_FLM_STAT_AUL_FAIL, 611 HW_FLM_STAT_TUL_DONE, 612 HW_FLM_STAT_FLOWS, 613 HW_FLM_STAT_STA_DONE, /* module ver 0.20 */ 614 HW_FLM_STAT_INF_DONE, /* module ver 0.20 */ 615 HW_FLM_STAT_INF_SKIP, /* module ver 0.20 */ 616 HW_FLM_STAT_PCK_HIT, /* module ver 0.20 */ 617 HW_FLM_STAT_PCK_MISS, /* module ver 0.20 */ 618 HW_FLM_STAT_PCK_UNH, /* module ver 0.20 */ 619 HW_FLM_STAT_PCK_DIS, /* module ver 0.20 */ 620 HW_FLM_STAT_CSH_HIT, /* module ver 0.20 */ 621 HW_FLM_STAT_CSH_MISS, /* module ver 0.20 */ 622 HW_FLM_STAT_CSH_UNH, /* module ver 0.20 */ 623 HW_FLM_STAT_CUC_START, /* module ver 0.20 */ 624 HW_FLM_STAT_CUC_MOVE, /* module ver 0.20 */ 625 HW_FLM_SCAN_I, /* module ver 0.22 */ 626 HW_FLM_SCRUB_PRESET_ALL, 627 HW_FLM_SCRUB_T, /* module ver 0.22 */ 628 HW_FLM_SCRUB_R, /* module ver 0.24 */ 629 HW_FLM_SCRUB_DEL, /* module ver 0.24 */ 630 HW_FLM_SCRUB_INF, /* module ver 0.24 */ 631 }; 632 633 bool hw_mod_flm_present(struct flow_api_backend_s *be); 634 int hw_mod_flm_alloc(struct flow_api_backend_s *be); 635 void hw_mod_flm_free(struct flow_api_backend_s *be); 636 int hw_mod_flm_reset(struct flow_api_backend_s *be); 637 638 int hw_mod_flm_control_flush(struct flow_api_backend_s *be); 639 int hw_mod_flm_control_set(struct flow_api_backend_s *be, enum hw_flm_e field, uint32_t value); 640 641 int hw_mod_flm_scan_flush(struct flow_api_backend_s *be); 642 643 int hw_mod_flm_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 644 645 int hw_mod_flm_scrub_flush(struct flow_api_backend_s *be, int start_idx, int count); 646 647 struct hsh_func_s { 648 COMMON_FUNC_INFO_S; 649 uint32_t nb_rcp;/* number of HSH recipes supported by FPGA */ 650 /* indication if Toeplitz is supported by FPGA, i.e. 0 - unsupported, 1 - supported */ 651 uint32_t toeplitz; 652 union { 653 struct hw_mod_hsh_v5_s v5; 654 }; 655 }; 656 enum hw_hsh_e { 657 /* functions */ 658 HW_HSH_RCP_PRESET_ALL = 0, 659 HW_HSH_RCP_COMPARE, 660 HW_HSH_RCP_FIND, 661 /* fields */ 662 HW_HSH_RCP_LOAD_DIST_TYPE = FIELD_START_INDEX, 663 HW_HSH_RCP_MAC_PORT_MASK, 664 HW_HSH_RCP_SORT, 665 HW_HSH_RCP_QW0_PE, 666 HW_HSH_RCP_QW0_OFS, 667 HW_HSH_RCP_QW4_PE, 668 HW_HSH_RCP_QW4_OFS, 669 HW_HSH_RCP_W8_PE, 670 HW_HSH_RCP_W8_OFS, 671 HW_HSH_RCP_W8_SORT, 672 HW_HSH_RCP_W9_PE, 673 HW_HSH_RCP_W9_OFS, 674 HW_HSH_RCP_W9_SORT, 675 HW_HSH_RCP_W9_P, 676 HW_HSH_RCP_P_MASK, 677 HW_HSH_RCP_WORD_MASK, 678 HW_HSH_RCP_SEED, 679 HW_HSH_RCP_TNL_P, 680 HW_HSH_RCP_HSH_VALID, 681 HW_HSH_RCP_HSH_TYPE, 682 HW_HSH_RCP_TOEPLITZ, 683 HW_HSH_RCP_K, 684 HW_HSH_RCP_AUTO_IPV4_MASK 685 }; 686 bool hw_mod_hsh_present(struct flow_api_backend_s *be); 687 int hw_mod_hsh_alloc(struct flow_api_backend_s *be); 688 void hw_mod_hsh_free(struct flow_api_backend_s *be); 689 int hw_mod_hsh_reset(struct flow_api_backend_s *be); 690 int hw_mod_hsh_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 691 int hw_mod_hsh_rcp_set(struct flow_api_backend_s *be, enum hw_hsh_e field, uint32_t index, 692 uint32_t word_off, uint32_t value); 693 694 struct qsl_func_s { 695 COMMON_FUNC_INFO_S; 696 uint32_t nb_rcp_categories; 697 uint32_t nb_qst_entries; 698 union { 699 struct hw_mod_qsl_v7_s v7; 700 }; 701 }; 702 enum hw_qsl_e { 703 /* functions */ 704 HW_QSL_RCP_PRESET_ALL = 0, 705 HW_QSL_RCP_COMPARE, 706 HW_QSL_RCP_FIND, 707 HW_QSL_QST_PRESET_ALL, 708 /* fields */ 709 HW_QSL_RCP_DISCARD = FIELD_START_INDEX, 710 HW_QSL_RCP_DROP, 711 HW_QSL_RCP_TBL_LO, 712 HW_QSL_RCP_TBL_HI, 713 HW_QSL_RCP_TBL_IDX, 714 HW_QSL_RCP_TBL_MSK, 715 HW_QSL_RCP_LR, 716 HW_QSL_RCP_TSA, 717 HW_QSL_RCP_VLI, 718 HW_QSL_QST_QUEUE, 719 HW_QSL_QST_EN, /* Alias: HW_QSL_QST_QEN */ 720 HW_QSL_QST_TX_PORT, 721 HW_QSL_QST_LRE, 722 HW_QSL_QST_TCI, 723 HW_QSL_QST_VEN, 724 HW_QSL_QEN_EN, 725 HW_QSL_UNMQ_DEST_QUEUE, 726 HW_QSL_UNMQ_EN, 727 }; 728 bool hw_mod_qsl_present(struct flow_api_backend_s *be); 729 int hw_mod_qsl_alloc(struct flow_api_backend_s *be); 730 void hw_mod_qsl_free(struct flow_api_backend_s *be); 731 int hw_mod_qsl_reset(struct flow_api_backend_s *be); 732 int hw_mod_qsl_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 733 int hw_mod_qsl_rcp_set(struct flow_api_backend_s *be, enum hw_qsl_e field, uint32_t index, 734 uint32_t value); 735 int hw_mod_qsl_qst_flush(struct flow_api_backend_s *be, int start_idx, int count); 736 int hw_mod_qsl_qst_set(struct flow_api_backend_s *be, enum hw_qsl_e field, uint32_t index, 737 uint32_t value); 738 int hw_mod_qsl_qen_flush(struct flow_api_backend_s *be, int start_idx, int count); 739 int hw_mod_qsl_qen_set(struct flow_api_backend_s *be, enum hw_qsl_e field, uint32_t index, 740 uint32_t value); 741 int hw_mod_qsl_qen_get(struct flow_api_backend_s *be, enum hw_qsl_e field, uint32_t index, 742 uint32_t *value); 743 int hw_mod_qsl_unmq_flush(struct flow_api_backend_s *be, int start_idx, int count); 744 int hw_mod_qsl_unmq_set(struct flow_api_backend_s *be, enum hw_qsl_e field, uint32_t index, 745 uint32_t value); 746 747 struct slc_lr_func_s { 748 COMMON_FUNC_INFO_S; 749 union { 750 struct hw_mod_slc_lr_v2_s v2; 751 }; 752 }; 753 enum hw_slc_lr_e { 754 /* functions */ 755 HW_SLC_LR_RCP_PRESET_ALL = 0, 756 HW_SLC_LR_RCP_COMPARE, 757 HW_SLC_LR_RCP_FIND, 758 /* fields */ 759 HW_SLC_LR_RCP_HEAD_SLC_EN = FIELD_START_INDEX, 760 HW_SLC_LR_RCP_HEAD_DYN, 761 HW_SLC_LR_RCP_HEAD_OFS, 762 HW_SLC_LR_RCP_TAIL_SLC_EN, 763 HW_SLC_LR_RCP_TAIL_DYN, 764 HW_SLC_LR_RCP_TAIL_OFS, 765 HW_SLC_LR_RCP_PCAP 766 }; 767 bool hw_mod_slc_lr_present(struct flow_api_backend_s *be); 768 int hw_mod_slc_lr_alloc(struct flow_api_backend_s *be); 769 void hw_mod_slc_lr_free(struct flow_api_backend_s *be); 770 int hw_mod_slc_lr_reset(struct flow_api_backend_s *be); 771 int hw_mod_slc_lr_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 772 int hw_mod_slc_lr_rcp_set(struct flow_api_backend_s *be, enum hw_slc_lr_e field, uint32_t index, 773 uint32_t value); 774 775 struct pdb_func_s { 776 COMMON_FUNC_INFO_S; 777 uint32_t nb_pdb_rcp_categories; 778 779 union { 780 struct hw_mod_pdb_v9_s v9; 781 }; 782 }; 783 enum hw_pdb_e { 784 /* functions */ 785 HW_PDB_RCP_PRESET_ALL = 0, 786 HW_PDB_RCP_COMPARE, 787 HW_PDB_RCP_FIND, 788 /* fields */ 789 HW_PDB_RCP_DESCRIPTOR = FIELD_START_INDEX, 790 HW_PDB_RCP_DESC_LEN, 791 HW_PDB_RCP_TX_PORT, 792 HW_PDB_RCP_TX_IGNORE, 793 HW_PDB_RCP_TX_NOW, 794 HW_PDB_RCP_CRC_OVERWRITE, 795 HW_PDB_RCP_ALIGN, 796 HW_PDB_RCP_OFS0_DYN, 797 HW_PDB_RCP_OFS0_REL, 798 HW_PDB_RCP_OFS1_DYN, 799 HW_PDB_RCP_OFS1_REL, 800 HW_PDB_RCP_OFS2_DYN, 801 HW_PDB_RCP_OFS2_REL, 802 HW_PDB_RCP_IP_PROT_TNL, 803 HW_PDB_RCP_PPC_HSH, 804 HW_PDB_RCP_DUPLICATE_EN, 805 HW_PDB_RCP_DUPLICATE_BIT, 806 HW_PDB_RCP_PCAP_KEEP_FCS, 807 HW_PDB_CONFIG_TS_FORMAT, 808 HW_PDB_CONFIG_PORT_OFS, 809 }; 810 bool hw_mod_pdb_present(struct flow_api_backend_s *be); 811 int hw_mod_pdb_alloc(struct flow_api_backend_s *be); 812 void hw_mod_pdb_free(struct flow_api_backend_s *be); 813 int hw_mod_pdb_reset(struct flow_api_backend_s *be); 814 int hw_mod_pdb_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 815 int hw_mod_pdb_rcp_set(struct flow_api_backend_s *be, enum hw_pdb_e field, uint32_t index, 816 uint32_t value); 817 818 int hw_mod_pdb_config_flush(struct flow_api_backend_s *be); 819 820 struct tpe_func_s { 821 COMMON_FUNC_INFO_S; 822 uint32_t nb_rcp_categories; 823 uint32_t nb_ifr_categories; 824 uint32_t nb_cpy_writers; 825 uint32_t nb_rpl_depth; 826 uint32_t nb_rpl_ext_categories; 827 union { 828 struct hw_mod_tpe_v3_s v3; 829 }; 830 }; 831 enum hw_tpe_e { 832 /* functions */ 833 HW_TPE_PRESET_ALL = 0, 834 HW_TPE_FIND, 835 HW_TPE_COMPARE, 836 /* Control fields */ 837 HW_TPE_RPP_RCP_EXP = FIELD_START_INDEX, 838 HW_TPE_IFR_RCP_IPV4_EN, 839 HW_TPE_IFR_RCP_IPV4_DF_DROP, 840 HW_TPE_IFR_RCP_IPV6_EN, 841 HW_TPE_IFR_RCP_IPV6_DROP, 842 HW_TPE_IFR_RCP_MTU, 843 HW_TPE_INS_RCP_DYN, 844 HW_TPE_INS_RCP_OFS, 845 HW_TPE_INS_RCP_LEN, 846 HW_TPE_RPL_RCP_DYN, 847 HW_TPE_RPL_RCP_OFS, 848 HW_TPE_RPL_RCP_LEN, 849 HW_TPE_RPL_RCP_RPL_PTR, 850 HW_TPE_RPL_RCP_EXT_PRIO, 851 HW_TPE_RPL_RCP_ETH_TYPE_WR, 852 HW_TPE_RPL_EXT_RPL_PTR, 853 HW_TPE_RPL_EXT_META_RPL_LEN, /* SW only */ 854 HW_TPE_RPL_RPL_VALUE, 855 HW_TPE_CPY_RCP_READER_SELECT, 856 HW_TPE_CPY_RCP_DYN, 857 HW_TPE_CPY_RCP_OFS, 858 HW_TPE_CPY_RCP_LEN, 859 HW_TPE_HFU_RCP_LEN_A_WR, 860 HW_TPE_HFU_RCP_LEN_A_OUTER_L4_LEN, 861 HW_TPE_HFU_RCP_LEN_A_POS_DYN, 862 HW_TPE_HFU_RCP_LEN_A_POS_OFS, 863 HW_TPE_HFU_RCP_LEN_A_ADD_DYN, 864 HW_TPE_HFU_RCP_LEN_A_ADD_OFS, 865 HW_TPE_HFU_RCP_LEN_A_SUB_DYN, 866 HW_TPE_HFU_RCP_LEN_B_WR, 867 HW_TPE_HFU_RCP_LEN_B_POS_DYN, 868 HW_TPE_HFU_RCP_LEN_B_POS_OFS, 869 HW_TPE_HFU_RCP_LEN_B_ADD_DYN, 870 HW_TPE_HFU_RCP_LEN_B_ADD_OFS, 871 HW_TPE_HFU_RCP_LEN_B_SUB_DYN, 872 HW_TPE_HFU_RCP_LEN_C_WR, 873 HW_TPE_HFU_RCP_LEN_C_POS_DYN, 874 HW_TPE_HFU_RCP_LEN_C_POS_OFS, 875 HW_TPE_HFU_RCP_LEN_C_ADD_DYN, 876 HW_TPE_HFU_RCP_LEN_C_ADD_OFS, 877 HW_TPE_HFU_RCP_LEN_C_SUB_DYN, 878 HW_TPE_HFU_RCP_TTL_WR, 879 HW_TPE_HFU_RCP_TTL_POS_DYN, 880 HW_TPE_HFU_RCP_TTL_POS_OFS, 881 HW_TPE_CSU_RCP_OUTER_L3_CMD, 882 HW_TPE_CSU_RCP_OUTER_L4_CMD, 883 HW_TPE_CSU_RCP_INNER_L3_CMD, 884 HW_TPE_CSU_RCP_INNER_L4_CMD, 885 }; 886 bool hw_mod_tpe_present(struct flow_api_backend_s *be); 887 int hw_mod_tpe_alloc(struct flow_api_backend_s *be); 888 void hw_mod_tpe_free(struct flow_api_backend_s *be); 889 int hw_mod_tpe_reset(struct flow_api_backend_s *be); 890 891 int hw_mod_tpe_rpp_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 892 int hw_mod_tpe_rpp_rcp_set(struct flow_api_backend_s *be, enum hw_tpe_e field, int index, 893 uint32_t value); 894 895 int hw_mod_tpe_rpp_ifr_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 896 897 int hw_mod_tpe_ifr_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 898 899 int hw_mod_tpe_ins_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 900 int hw_mod_tpe_ins_rcp_set(struct flow_api_backend_s *be, enum hw_tpe_e field, int index, 901 uint32_t value); 902 903 int hw_mod_tpe_rpl_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 904 int hw_mod_tpe_rpl_rcp_set(struct flow_api_backend_s *be, enum hw_tpe_e field, int index, 905 uint32_t value); 906 907 int hw_mod_tpe_rpl_ext_flush(struct flow_api_backend_s *be, int start_idx, int count); 908 int hw_mod_tpe_rpl_ext_set(struct flow_api_backend_s *be, enum hw_tpe_e field, int index, 909 uint32_t value); 910 911 int hw_mod_tpe_rpl_rpl_flush(struct flow_api_backend_s *be, int start_idx, int count); 912 int hw_mod_tpe_rpl_rpl_set(struct flow_api_backend_s *be, enum hw_tpe_e field, int index, 913 uint32_t *value); 914 915 int hw_mod_tpe_cpy_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 916 int hw_mod_tpe_cpy_rcp_set(struct flow_api_backend_s *be, enum hw_tpe_e field, int index, 917 uint32_t value); 918 919 int hw_mod_tpe_hfu_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 920 int hw_mod_tpe_hfu_rcp_set(struct flow_api_backend_s *be, enum hw_tpe_e field, int index, 921 uint32_t value); 922 923 int hw_mod_tpe_csu_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); 924 int hw_mod_tpe_csu_rcp_set(struct flow_api_backend_s *be, enum hw_tpe_e field, int index, 925 uint32_t value); 926 927 enum debug_mode_e { 928 FLOW_BACKEND_DEBUG_MODE_NONE = 0x0000, 929 FLOW_BACKEND_DEBUG_MODE_WRITE = 0x0001 930 }; 931 932 struct flow_api_backend_ops { 933 int version; 934 int (*set_debug_mode)(void *dev, enum debug_mode_e mode); 935 int (*get_nb_phy_port)(void *dev); 936 int (*get_nb_rx_port)(void *dev); 937 int (*get_ltx_avail)(void *dev); 938 int (*get_nb_cat_funcs)(void *dev); 939 int (*get_nb_categories)(void *dev); 940 int (*get_nb_cat_km_if_cnt)(void *dev); 941 int (*get_nb_cat_km_if_m0)(void *dev); 942 int (*get_nb_cat_km_if_m1)(void *dev); 943 944 int (*get_nb_queues)(void *dev); 945 int (*get_nb_km_flow_types)(void *dev); 946 int (*get_nb_pm_ext)(void *dev); 947 int (*get_nb_len)(void *dev); 948 int (*get_kcc_size)(void *dev); 949 int (*get_kcc_banks)(void *dev); 950 int (*get_nb_km_categories)(void *dev); 951 int (*get_nb_km_cam_banks)(void *dev); 952 int (*get_nb_km_cam_record_words)(void *dev); 953 int (*get_nb_km_cam_records)(void *dev); 954 int (*get_nb_km_tcam_banks)(void *dev); 955 int (*get_nb_km_tcam_bank_width)(void *dev); 956 int (*get_nb_flm_categories)(void *dev); 957 int (*get_nb_flm_size_mb)(void *dev); 958 int (*get_nb_flm_entry_size)(void *dev); 959 int (*get_nb_flm_variant)(void *dev); 960 int (*get_nb_flm_prios)(void *dev); 961 int (*get_nb_flm_pst_profiles)(void *dev); 962 int (*get_nb_flm_scrub_profiles)(void *dev); 963 int (*get_nb_flm_load_aps_max)(void *dev); 964 int (*get_nb_qsl_categories)(void *dev); 965 int (*get_nb_qsl_qst_entries)(void *dev); 966 int (*get_nb_pdb_categories)(void *dev); 967 int (*get_nb_roa_categories)(void *dev); 968 int (*get_nb_tpe_categories)(void *dev); 969 int (*get_nb_tx_cpy_writers)(void *dev); 970 int (*get_nb_tx_cpy_mask_mem)(void *dev); 971 int (*get_nb_tx_rpl_depth)(void *dev); 972 int (*get_nb_tx_rpl_ext_categories)(void *dev); 973 int (*get_nb_tpe_ifr_categories)(void *dev); 974 int (*get_nb_rpp_per_ps)(void *dev); 975 int (*get_nb_hsh_categories)(void *dev); 976 int (*get_nb_hsh_toeplitz)(void *dev); 977 978 int (*alloc_rx_queue)(void *dev, int queue_id); 979 int (*free_rx_queue)(void *dev, int hw_queue); 980 981 /* CAT */ 982 bool (*get_cat_present)(void *dev); 983 uint32_t (*get_cat_version)(void *dev); 984 int (*cat_cfn_flush)(void *dev, const struct cat_func_s *cat, int cat_func, int cnt); 985 int (*cat_kce_flush)(void *dev, const struct cat_func_s *cat, int km_if_idx, int index, 986 int cnt); 987 int (*cat_kcs_flush)(void *dev, const struct cat_func_s *cat, int km_if_idx, int cat_func, 988 int cnt); 989 int (*cat_fte_flush)(void *dev, const struct cat_func_s *cat, int km_if_idx, int index, 990 int cnt); 991 int (*cat_cte_flush)(void *dev, const struct cat_func_s *cat, int cat_func, int cnt); 992 int (*cat_cts_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt); 993 int (*cat_cot_flush)(void *dev, const struct cat_func_s *cat, int cat_func, int cnt); 994 int (*cat_cct_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt); 995 int (*cat_exo_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt); 996 int (*cat_rck_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt); 997 int (*cat_len_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt); 998 int (*cat_kcc_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt); 999 1000 /* KM */ 1001 bool (*get_km_present)(void *dev); 1002 uint32_t (*get_km_version)(void *dev); 1003 int (*km_rcp_flush)(void *dev, const struct km_func_s *km, int category, int cnt); 1004 int (*km_cam_flush)(void *dev, const struct km_func_s *km, int bank, int record, int cnt); 1005 int (*km_tcam_flush)(void *dev, const struct km_func_s *km, int bank, int byte, int value, 1006 int cnt); 1007 int (*km_tci_flush)(void *dev, const struct km_func_s *km, int bank, int record, int cnt); 1008 int (*km_tcq_flush)(void *dev, const struct km_func_s *km, int bank, int record, int cnt); 1009 1010 /* FLM */ 1011 bool (*get_flm_present)(void *dev); 1012 uint32_t (*get_flm_version)(void *dev); 1013 int (*flm_control_flush)(void *dev, const struct flm_func_s *flm); 1014 int (*flm_status_flush)(void *dev, const struct flm_func_s *flm); 1015 int (*flm_status_update)(void *dev, const struct flm_func_s *flm); 1016 int (*flm_scan_flush)(void *dev, const struct flm_func_s *flm); 1017 int (*flm_load_bin_flush)(void *dev, const struct flm_func_s *flm); 1018 int (*flm_prio_flush)(void *dev, const struct flm_func_s *flm); 1019 int (*flm_pst_flush)(void *dev, const struct flm_func_s *flm, int index, int cnt); 1020 int (*flm_rcp_flush)(void *dev, const struct flm_func_s *flm, int index, int cnt); 1021 int (*flm_scrub_flush)(void *dev, const struct flm_func_s *flm, int index, int cnt); 1022 int (*flm_buf_ctrl_update)(void *dev, const struct flm_func_s *flm); 1023 int (*flm_stat_update)(void *dev, const struct flm_func_s *flm); 1024 int (*flm_lrn_data_flush)(void *be_dev, const struct flm_func_s *flm, 1025 const uint32_t *lrn_data, uint32_t records, 1026 uint32_t *handled_records, uint32_t words_per_record, 1027 uint32_t *inf_word_cnt, uint32_t *sta_word_cnt); 1028 int (*flm_inf_sta_data_update)(void *be_dev, const struct flm_func_s *flm, 1029 uint32_t *inf_data, uint32_t inf_size, 1030 uint32_t *inf_word_cnt, uint32_t *sta_data, 1031 uint32_t sta_size, uint32_t *sta_word_cnt); 1032 1033 /* HSH */ 1034 bool (*get_hsh_present)(void *dev); 1035 uint32_t (*get_hsh_version)(void *dev); 1036 int (*hsh_rcp_flush)(void *dev, const struct hsh_func_s *hsh, int category, int cnt); 1037 1038 /* QSL */ 1039 bool (*get_qsl_present)(void *dev); 1040 uint32_t (*get_qsl_version)(void *dev); 1041 int (*qsl_rcp_flush)(void *dev, const struct qsl_func_s *qsl, int category, int cnt); 1042 int (*qsl_qst_flush)(void *dev, const struct qsl_func_s *qsl, int entry, int cnt); 1043 int (*qsl_qen_flush)(void *dev, const struct qsl_func_s *qsl, int entry, int cnt); 1044 int (*qsl_unmq_flush)(void *dev, const struct qsl_func_s *qsl, int entry, int cnt); 1045 1046 /* SLC LR */ 1047 bool (*get_slc_lr_present)(void *dev); 1048 uint32_t (*get_slc_lr_version)(void *dev); 1049 int (*slc_lr_rcp_flush)(void *dev, const struct slc_lr_func_s *slc_lr, int category, 1050 int cnt); 1051 1052 /* PDB */ 1053 bool (*get_pdb_present)(void *dev); 1054 uint32_t (*get_pdb_version)(void *dev); 1055 int (*pdb_rcp_flush)(void *dev, const struct pdb_func_s *pdb, int category, int cnt); 1056 int (*pdb_config_flush)(void *dev, const struct pdb_func_s *pdb); 1057 1058 /* TPE */ 1059 bool (*get_tpe_present)(void *dev); 1060 uint32_t (*get_tpe_version)(void *dev); 1061 int (*tpe_rpp_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 1062 int (*tpe_rpp_ifr_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 1063 int (*tpe_ifr_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 1064 int (*tpe_ins_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 1065 int (*tpe_rpl_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 1066 int (*tpe_rpl_ext_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 1067 int (*tpe_rpl_rpl_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 1068 int (*tpe_cpy_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 1069 int (*tpe_hfu_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 1070 int (*tpe_csu_rcp_flush)(void *dev, const struct tpe_func_s *tpe, int index, int cnt); 1071 }; 1072 1073 struct flow_api_backend_s { 1074 void *be_dev; 1075 const struct flow_api_backend_ops *iface; 1076 1077 /* flow filter FPGA modules */ 1078 struct cat_func_s cat; 1079 struct km_func_s km; 1080 struct flm_func_s flm; 1081 struct hsh_func_s hsh; 1082 struct qsl_func_s qsl; 1083 struct slc_lr_func_s slc_lr; 1084 struct pdb_func_s pdb; 1085 struct tpe_func_s tpe; 1086 1087 /* NIC attributes */ 1088 unsigned int num_phy_ports; 1089 unsigned int num_rx_ports; 1090 1091 /* flow filter resource capacities */ 1092 unsigned int max_categories; 1093 unsigned int max_queues; 1094 }; 1095 1096 int flow_api_backend_init(struct flow_api_backend_s *dev, const struct flow_api_backend_ops *iface, 1097 void *be_dev); 1098 int flow_api_backend_done(struct flow_api_backend_s *dev); 1099 1100 #endif /* _HW_MOD_BACKEND_H_ */ 1101