1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -passes=instcombine -S | FileCheck %s 3 4define i1 @test2(i1 %X, i1 %Y) { 5; CHECK-LABEL: @test2( 6; CHECK-NEXT: [[A:%.*]] = and i1 [[X:%.*]], [[Y:%.*]] 7; CHECK-NEXT: ret i1 [[A]] 8; 9 %a = and i1 %X, %Y 10 %b = and i1 %a, %X 11 ret i1 %b 12} 13 14define i1 @test2_logical(i1 %X, i1 %Y) { 15; CHECK-LABEL: @test2_logical( 16; CHECK-NEXT: [[A:%.*]] = select i1 [[X:%.*]], i1 [[Y:%.*]], i1 false 17; CHECK-NEXT: ret i1 [[A]] 18; 19 %a = select i1 %X, i1 %Y, i1 false 20 %b = select i1 %a, i1 %X, i1 false 21 ret i1 %b 22} 23 24define i32 @test3(i32 %X, i32 %Y) { 25; CHECK-LABEL: @test3( 26; CHECK-NEXT: [[A:%.*]] = and i32 [[X:%.*]], [[Y:%.*]] 27; CHECK-NEXT: ret i32 [[A]] 28; 29 %a = and i32 %X, %Y 30 %b = and i32 %Y, %a 31 ret i32 %b 32} 33 34define i1 @test7(i32 %i, i1 %b) { 35; CHECK-LABEL: @test7( 36; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[I:%.*]], 0 37; CHECK-NEXT: [[AND2:%.*]] = and i1 [[TMP1]], [[B:%.*]] 38; CHECK-NEXT: ret i1 [[AND2]] 39; 40 %cmp1 = icmp slt i32 %i, 1 41 %cmp2 = icmp sgt i32 %i, -1 42 %and1 = and i1 %cmp1, %b 43 %and2 = and i1 %and1, %cmp2 44 ret i1 %and2 45} 46 47define i1 @test7_logical(i32 %i, i1 %b) { 48; CHECK-LABEL: @test7_logical( 49; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[I:%.*]], 0 50; CHECK-NEXT: [[AND2:%.*]] = select i1 [[TMP1]], i1 [[B:%.*]], i1 false 51; CHECK-NEXT: ret i1 [[AND2]] 52; 53 %cmp1 = icmp slt i32 %i, 1 54 %cmp2 = icmp sgt i32 %i, -1 55 %and1 = select i1 %cmp1, i1 %b, i1 false 56 %and2 = select i1 %and1, i1 %cmp2, i1 false 57 ret i1 %and2 58} 59 60define i1 @test8(i32 %i) { 61; CHECK-LABEL: @test8( 62; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[I:%.*]], -1 63; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[TMP1]], 13 64; CHECK-NEXT: ret i1 [[COND]] 65; 66 %cmp1 = icmp ne i32 %i, 0 67 %cmp2 = icmp ult i32 %i, 14 68 %cond = and i1 %cmp1, %cmp2 69 ret i1 %cond 70} 71 72define i1 @test8_logical(i32 %i) { 73; CHECK-LABEL: @test8_logical( 74; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[I:%.*]], -1 75; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[TMP1]], 13 76; CHECK-NEXT: ret i1 [[COND]] 77; 78 %cmp1 = icmp ne i32 %i, 0 79 %cmp2 = icmp ult i32 %i, 14 80 %cond = select i1 %cmp1, i1 %cmp2, i1 false 81 ret i1 %cond 82} 83 84define <2 x i1> @test8vec(<2 x i32> %i) { 85; CHECK-LABEL: @test8vec( 86; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[I:%.*]], splat (i32 -1) 87; CHECK-NEXT: [[COND:%.*]] = icmp ult <2 x i32> [[TMP1]], splat (i32 13) 88; CHECK-NEXT: ret <2 x i1> [[COND]] 89; 90 %cmp1 = icmp ne <2 x i32> %i, zeroinitializer 91 %cmp2 = icmp ult <2 x i32> %i, <i32 14, i32 14> 92 %cond = and <2 x i1> %cmp1, %cmp2 93 ret <2 x i1> %cond 94} 95 96; combine -x & 1 into x & 1 97define i64 @test9(i64 %x) { 98; CHECK-LABEL: @test9( 99; CHECK-NEXT: [[AND:%.*]] = and i64 [[X:%.*]], 1 100; CHECK-NEXT: ret i64 [[AND]] 101; 102 %sub = sub nsw i64 0, %x 103 %and = and i64 %sub, 1 104 ret i64 %and 105} 106 107; combine -x & 1 into x & 1 108define <2 x i64> @test9vec(<2 x i64> %x) { 109; CHECK-LABEL: @test9vec( 110; CHECK-NEXT: [[AND:%.*]] = and <2 x i64> [[X:%.*]], splat (i64 1) 111; CHECK-NEXT: ret <2 x i64> [[AND]] 112; 113 %sub = sub nsw <2 x i64> <i64 0, i64 0>, %x 114 %and = and <2 x i64> %sub, <i64 1, i64 1> 115 ret <2 x i64> %and 116} 117 118define i64 @test10(i64 %x) { 119; CHECK-LABEL: @test10( 120; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[X:%.*]], -2 121; CHECK-NEXT: [[ADD:%.*]] = sub i64 0, [[TMP1]] 122; CHECK-NEXT: ret i64 [[ADD]] 123; 124 %sub = sub nsw i64 0, %x 125 %and = and i64 %sub, 1 126 %add = add i64 %sub, %and 127 ret i64 %add 128} 129 130; (1 << x) & 1 --> zext(x == 0) 131 132define i8 @and1_shl1_is_cmp_eq_0(i8 %x) { 133; CHECK-LABEL: @and1_shl1_is_cmp_eq_0( 134; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[X:%.*]], 0 135; CHECK-NEXT: [[AND:%.*]] = zext i1 [[TMP1]] to i8 136; CHECK-NEXT: ret i8 [[AND]] 137; 138 %sh = shl i8 1, %x 139 %and = and i8 %sh, 1 140 ret i8 %and 141} 142 143; Don't do it if the shift has another use. 144 145define i8 @and1_shl1_is_cmp_eq_0_multiuse(i8 %x) { 146; CHECK-LABEL: @and1_shl1_is_cmp_eq_0_multiuse( 147; CHECK-NEXT: [[SH:%.*]] = shl nuw i8 1, [[X:%.*]] 148; CHECK-NEXT: [[AND:%.*]] = and i8 [[SH]], 1 149; CHECK-NEXT: [[ADD:%.*]] = add nuw i8 [[SH]], [[AND]] 150; CHECK-NEXT: ret i8 [[ADD]] 151; 152 %sh = shl i8 1, %x 153 %and = and i8 %sh, 1 154 %add = add i8 %sh, %and 155 ret i8 %add 156} 157 158; (1 << x) & 1 --> zext(x == 0) 159 160define <2 x i8> @and1_shl1_is_cmp_eq_0_vec(<2 x i8> %x) { 161; CHECK-LABEL: @and1_shl1_is_cmp_eq_0_vec( 162; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i8> [[X:%.*]], zeroinitializer 163; CHECK-NEXT: [[AND:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i8> 164; CHECK-NEXT: ret <2 x i8> [[AND]] 165; 166 %sh = shl <2 x i8> <i8 1, i8 1>, %x 167 %and = and <2 x i8> %sh, <i8 1, i8 1> 168 ret <2 x i8> %and 169} 170 171define <2 x i8> @and1_shl1_is_cmp_eq_0_vec_poison(<2 x i8> %x) { 172; CHECK-LABEL: @and1_shl1_is_cmp_eq_0_vec_poison( 173; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i8> [[X:%.*]], zeroinitializer 174; CHECK-NEXT: [[AND:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i8> 175; CHECK-NEXT: ret <2 x i8> [[AND]] 176; 177 %sh = shl <2 x i8> <i8 1, i8 poison>, %x 178 %and = and <2 x i8> %sh, <i8 1, i8 poison> 179 ret <2 x i8> %and 180} 181 182; The mask is unnecessary. 183 184define i8 @and1_lshr1_is_cmp_eq_0(i8 %x) { 185; CHECK-LABEL: @and1_lshr1_is_cmp_eq_0( 186; CHECK-NEXT: [[SH:%.*]] = lshr i8 1, [[X:%.*]] 187; CHECK-NEXT: ret i8 [[SH]] 188; 189 %sh = lshr i8 1, %x 190 %and = and i8 %sh, 1 191 ret i8 %and 192} 193 194define i8 @and1_lshr1_is_cmp_eq_0_multiuse(i8 %x) { 195; CHECK-LABEL: @and1_lshr1_is_cmp_eq_0_multiuse( 196; CHECK-NEXT: [[SH:%.*]] = lshr i8 1, [[X:%.*]] 197; CHECK-NEXT: [[ADD:%.*]] = shl nuw nsw i8 [[SH]], 1 198; CHECK-NEXT: ret i8 [[ADD]] 199; 200 %sh = lshr i8 1, %x 201 %and = and i8 %sh, 1 202 %add = add i8 %sh, %and 203 ret i8 %add 204} 205 206; The mask is unnecessary. 207 208define <2 x i8> @and1_lshr1_is_cmp_eq_0_vec(<2 x i8> %x) { 209; CHECK-LABEL: @and1_lshr1_is_cmp_eq_0_vec( 210; CHECK-NEXT: [[SH:%.*]] = lshr <2 x i8> splat (i8 1), [[X:%.*]] 211; CHECK-NEXT: ret <2 x i8> [[SH]] 212; 213 %sh = lshr <2 x i8> <i8 1, i8 1>, %x 214 %and = and <2 x i8> %sh, <i8 1, i8 1> 215 ret <2 x i8> %and 216} 217 218define <2 x i8> @and1_lshr1_is_cmp_eq_0_vec_poison(<2 x i8> %x) { 219; CHECK-LABEL: @and1_lshr1_is_cmp_eq_0_vec_poison( 220; CHECK-NEXT: [[AND:%.*]] = lshr <2 x i8> <i8 1, i8 poison>, [[X:%.*]] 221; CHECK-NEXT: ret <2 x i8> [[AND]] 222; 223 %sh = lshr <2 x i8> <i8 1, i8 poison>, %x 224 %and = and <2 x i8> %sh, <i8 1, i8 poison> 225 ret <2 x i8> %and 226} 227 228; The add in this test is unnecessary because the LSBs of the LHS are 0 and the 'and' only consumes bits from those LSBs. It doesn't matter what happens to the upper bits. 229define i32 @test11(i32 %a, i32 %b) { 230; CHECK-LABEL: @test11( 231; CHECK-NEXT: [[X:%.*]] = shl i32 [[A:%.*]], 8 232; CHECK-NEXT: [[Z:%.*]] = and i32 [[B:%.*]], 128 233; CHECK-NEXT: [[W:%.*]] = mul i32 [[Z]], [[X]] 234; CHECK-NEXT: ret i32 [[W]] 235; 236 %x = shl i32 %a, 8 237 %y = add i32 %x, %b 238 %z = and i32 %y, 128 239 %w = mul i32 %z, %x ; to keep the shift from being removed 240 ret i32 %w 241} 242 243; The add in this test is unnecessary because the LSBs of the RHS are 0 and the 'and' only consumes bits from those LSBs. It doesn't matter what happens to the upper bits. 244define i32 @test12(i32 %a, i32 %b) { 245; CHECK-LABEL: @test12( 246; CHECK-NEXT: [[X:%.*]] = shl i32 [[A:%.*]], 8 247; CHECK-NEXT: [[Z:%.*]] = and i32 [[B:%.*]], 128 248; CHECK-NEXT: [[W:%.*]] = mul i32 [[Z]], [[X]] 249; CHECK-NEXT: ret i32 [[W]] 250; 251 %x = shl i32 %a, 8 252 %y = add i32 %b, %x 253 %z = and i32 %y, 128 254 %w = mul i32 %z, %x ; to keep the shift from being removed 255 ret i32 %w 256} 257 258; The sub in this test is unnecessary because the LSBs of the RHS are 0 and the 'and' only consumes bits from those LSBs. It doesn't matter what happens to the upper bits. 259define i32 @test13(i32 %a, i32 %b) { 260; CHECK-LABEL: @test13( 261; CHECK-NEXT: [[X:%.*]] = shl i32 [[A:%.*]], 8 262; CHECK-NEXT: [[Z:%.*]] = and i32 [[B:%.*]], 128 263; CHECK-NEXT: [[W:%.*]] = mul i32 [[Z]], [[X]] 264; CHECK-NEXT: ret i32 [[W]] 265; 266 %x = shl i32 %a, 8 267 %y = sub i32 %b, %x 268 %z = and i32 %y, 128 269 %w = mul i32 %z, %x ; to keep the shift from being removed 270 ret i32 %w 271} 272 273; The sub in this test cannot be removed because we need to keep the negation of %b. TODO: But we should be able to replace the LHS of it with a 0. 274define i32 @test14(i32 %a, i32 %b) { 275; CHECK-LABEL: @test14( 276; CHECK-NEXT: [[X:%.*]] = shl i32 [[A:%.*]], 8 277; CHECK-NEXT: [[Y:%.*]] = sub i32 0, [[B:%.*]] 278; CHECK-NEXT: [[Z:%.*]] = and i32 [[Y]], 128 279; CHECK-NEXT: [[W:%.*]] = mul i32 [[Z]], [[X]] 280; CHECK-NEXT: ret i32 [[W]] 281; 282 %x = shl i32 %a, 8 283 %y = sub i32 %x, %b 284 %z = and i32 %y, 128 285 %w = mul i32 %z, %x ; to keep the shift from being removed 286 ret i32 %w 287} 288