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Revision tags: llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4 |
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38fffa63 |
| 06-Nov-2024 |
Paul Walker <paul.walker@arm.com> |
[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)
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Revision tags: llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5 |
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d9a5aa8e |
| 17-Apr-2024 |
Nikita Popov <npopov@redhat.com> |
[PatternMatch] Do not accept undef elements in m_AllOnes() and friends (#88217)
Change all the cstval_pred_ty based PatternMatch helpers (things like
m_AllOnes and m_Zero) to only allow poison elem
[PatternMatch] Do not accept undef elements in m_AllOnes() and friends (#88217)
Change all the cstval_pred_ty based PatternMatch helpers (things like
m_AllOnes and m_Zero) to only allow poison elements inside vector
splats, not undef elements.
Historically, we used to represent non-demanded elements in vectors
using undef. Nowadays, we use poison instead. As such, I believe that
support for undef in vector splats is no longer useful.
At the same time, while poison splat elements are pretty much always
safe to ignore, this is not generally the case for undef elements. We
have existing miscompiles in our tests due to this (see the
masked-merge-*.ll tests changed here) and it's easy to miss such cases
in the future, now that we write tests using poison instead of undef
elements.
I think overall, keeping support for undef elements no longer makes
sense, and we should drop it. Once this is done consistently, I think we
may also consider allowing poison in m_APInt by default, as doing that
change is much less risky than doing the same with undef.
This change involves a substantial amount of test changes. For most
tests, I've just replaced undef with poison, as I don't think there is
value in retaining both. For some tests (where the distinction between
undef and poison is important), I've duplicated tests.
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Revision tags: llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2 |
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2caaec65 |
| 06-Apr-2023 |
Nikita Popov <npopov@redhat.com> |
[InstCombine] Regenerate all test checks (NFC)
Due to an improvement to name preservation, a lot of InstCombine tests now show spurious diffs when regenerated.
Rather than regenerating individual f
[InstCombine] Regenerate all test checks (NFC)
Due to an improvement to name preservation, a lot of InstCombine tests now show spurious diffs when regenerated.
Rather than regenerating individual files when they get touched, mass-regenerate all UTC-based InstCombine tests. I have then reset a number of files showing suspicious diffs where the UTC output has clearly been manually adjusted. I apologize if I missed anything in the mass of changes.
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Revision tags: llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7 |
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d4493dd1 |
| 15-Dec-2022 |
Sanjay Patel <spatel@rotateright.com> |
[InstCombine] add nuw to any (1<<x)
https://alive2.llvm.org/ce/z/9EjDKE
This was mentioned as a missing fold in D139598.
It can unlock follow-on folds in some cases. This verifies one of the chang
[InstCombine] add nuw to any (1<<x)
https://alive2.llvm.org/ce/z/9EjDKE
This was mentioned as a missing fold in D139598.
It can unlock follow-on folds in some cases. This verifies one of the changed tests: https://alive2.llvm.org/ce/z/B_btDM
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Revision tags: llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4 |
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c0e06c74 |
| 24-May-2022 |
Nikita Popov <npopov@redhat.com> |
[InstCombine] Handle logical and/or in recursive and/or of icmps fold
The and/or of icmps fold is also applied in reassociated form. However, this currently only happens for bitwise and of bitwise a
[InstCombine] Handle logical and/or in recursive and/or of icmps fold
The and/or of icmps fold is also applied in reassociated form. However, this currently only happens for bitwise and of bitwise and, but not for bitwise and of logical and (or other combinations, but this is the one being addressed here).
We can do this for bitwise+logical combinations as well, but need to be a bit careful about which of the resulting ands are logical: https://alive2.llvm.org/ce/z/WYSjGh https://alive2.llvm.org/ce/z/guxYnz https://alive2.llvm.org/ce/z/S5SYxY https://alive2.llvm.org/ce/z/2rAWeW
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Revision tags: llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1 |
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acdc419c |
| 04-Feb-2022 |
Bjorn Pettersson <bjorn.a.pettersson@ericsson.com> |
[test] Use -passes=instcombine instead of -instcombine in lots of tests. NFC
Another step moving away from the deprecated syntax of specifying pass pipeline in opt.
Differential Revision: https://r
[test] Use -passes=instcombine instead of -instcombine in lots of tests. NFC
Another step moving away from the deprecated syntax of specifying pass pipeline in opt.
Differential Revision: https://reviews.llvm.org/D119081
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Revision tags: llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2, llvmorg-13.0.1-rc1 |
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861adaf2 |
| 10-Nov-2021 |
Nikita Popov <nikita.ppv@gmail.com> |
[InstCombine] Support splat vectors in some and of icmp folds
Replace m_ConstantInt() with m_APInt() to support splat vectors in addition to scalar integers.
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fa4e9e64 |
| 10-Nov-2021 |
Nikita Popov <nikita.ppv@gmail.com> |
[InstCombine] Add vector variants to merge-icmps.ll (NFC)
And regenerate test checks.
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Revision tags: llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3, llvmorg-13.0.0-rc2, llvmorg-13.0.0-rc1, llvmorg-14-init, llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3, llvmorg-12.0.1-rc2, llvmorg-12.0.1-rc1 |
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8a156d1c |
| 02-May-2021 |
Juneyoung Lee <aqjune@gmail.com> |
[InstCombine] Fully disable select to and/or i1 folding
This is a patch that disables the poison-unsafe select -> and/or i1 folding.
It has been blocking D72396 and also has been the source of a fe
[InstCombine] Fully disable select to and/or i1 folding
This is a patch that disables the poison-unsafe select -> and/or i1 folding.
It has been blocking D72396 and also has been the source of a few miscompilations described in llvm.org/pr49688 . D99674 conditionally blocked this folding and successfully fixed the latter one. The former one was still blocked, and this patch addresses it.
Note that a few test functions that has `_logical` suffix are now deoptimized. These are created by @nikic to check the impact of disabling this optimization by copying existing original functions and replacing and/or with select.
I can see that most of these are poison-unsafe; they can be revived by introducing freeze instruction. I left comments at fcmp + select optimizations (or-fcmp.ll, and-fcmp.ll) because I think they are good targets for freeze fix.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D101191
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Revision tags: llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4, llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2 |
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0be0a123 |
| 09-Feb-2021 |
Sanjay Patel <spatel@rotateright.com> |
[ValueTracking] improve analysis for "C << X" and "C >> X"
This is based on the example/comments in: https://llvm.org/PR48984
I tried just lifting the restriction in computeKnownBitsFromShiftOperat
[ValueTracking] improve analysis for "C << X" and "C >> X"
This is based on the example/comments in: https://llvm.org/PR48984
I tried just lifting the restriction in computeKnownBitsFromShiftOperator() as suggested in the bug report, but that doesn't catch all of the cases shown here. I didn't step through to see exactly why that happened. But it seems like a reasonable compromise to cheaply check the special-case of shifting a constant.
There's a slight regression on a cmp transform as noted, but this is likely the more important/common pattern, so we can fix that icmp pattern later if needed.
Differential Revision: https://reviews.llvm.org/D95959
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Revision tags: llvmorg-11.1.0, llvmorg-11.1.0-rc3, llvmorg-12.0.0-rc1, llvmorg-13-init, llvmorg-11.1.0-rc2 |
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fb063c93 |
| 12-Jan-2021 |
Nikita Popov <nikita.ppv@gmail.com> |
[InstCombine] Duplicate tests for logical and/or (NFC)
This replicates existing and/or tests to also test variants using select. This should help us get a more accurate view on which optimizations w
[InstCombine] Duplicate tests for logical and/or (NFC)
This replicates existing and/or tests to also test variants using select. This should help us get a more accurate view on which optimizations we're missing if we disable the select -> and/or fold.
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Revision tags: llvmorg-11.1.0-rc1, llvmorg-11.0.1, llvmorg-11.0.1-rc2, llvmorg-11.0.1-rc1 |
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0b7b446a |
| 16-Oct-2020 |
Simon Pilgrim <llvm-dev@redking.me.uk> |
[InstCombine] Support vectors-with-undef in and(logicalshift(1,X),1) --> zext(X == 0) fold
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2d1fea29 |
| 16-Oct-2020 |
Simon Pilgrim <llvm-dev@redking.me.uk> |
[InstCombine] Add vectors-with-undef tests for and(logicalshift(1,X),1) --> zext(X == 0)
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Revision tags: llvmorg-11.0.0, llvmorg-11.0.0-rc6, llvmorg-11.0.0-rc5, llvmorg-11.0.0-rc4, llvmorg-11.0.0-rc3, llvmorg-11.0.0-rc2, llvmorg-11.0.0-rc1, llvmorg-12-init, llvmorg-10.0.1, llvmorg-10.0.1-rc4, llvmorg-10.0.1-rc3, llvmorg-10.0.1-rc2, llvmorg-10.0.1-rc1, llvmorg-10.0.0, llvmorg-10.0.0-rc6, llvmorg-10.0.0-rc5, llvmorg-10.0.0-rc4, llvmorg-10.0.0-rc3, llvmorg-10.0.0-rc2, llvmorg-10.0.0-rc1, llvmorg-11-init |
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7973aa05 |
| 03-Jan-2020 |
Roman Lebedev <lebedev.ri@gmail.com> |
[NFC][InstCombine] '(Op1 & С) - Op1' -> '-(Op1 & ~C)' fold (PR44427)
This decreases use count of Op1, potentially allows us to further hoist said 'neg' later on, and results in marginally better X86
[NFC][InstCombine] '(Op1 & С) - Op1' -> '-(Op1 & ~C)' fold (PR44427)
This decreases use count of Op1, potentially allows us to further hoist said 'neg' later on, and results in marginally better X86 codegen.
Name: (Op1 & С) - Op1 -> -(Op1 & ~C) %o = and i64 %Op1, C1 %r = sub i64 %o, %Op1 => %n = and i64 %Op1, ~C1 %r = sub i64 0, %n
https://rise4fun.com/Alive/rwgA
https://godbolt.org/z/R_RMfM
https://bugs.llvm.org/show_bug.cgi?id=44427
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9b750cc6 |
| 03-Jan-2020 |
Roman Lebedev <lebedev.ri@gmail.com> |
[NFC][InstCombine] Autogenerate and2.ll checklines
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Revision tags: llvmorg-9.0.1, llvmorg-9.0.1-rc3, llvmorg-9.0.1-rc2, llvmorg-9.0.1-rc1, llvmorg-9.0.0, llvmorg-9.0.0-rc6, llvmorg-9.0.0-rc5, llvmorg-9.0.0-rc4, llvmorg-9.0.0-rc3, llvmorg-9.0.0-rc2, llvmorg-9.0.0-rc1, llvmorg-10-init, llvmorg-8.0.1, llvmorg-8.0.1-rc4, llvmorg-8.0.1-rc3, llvmorg-8.0.1-rc2, llvmorg-8.0.1-rc1 |
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cee313d2 |
| 17-Apr-2019 |
Eric Christopher <echristo@gmail.com> |
Revert "Temporarily Revert "Add basic loop fusion pass.""
The reversion apparently deleted the test/Transforms directory.
Will be re-reverting again.
llvm-svn: 358552
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10edd2b7 |
| 09-Apr-2019 |
Nikita Popov <nikita.ppv@gmail.com> |
[ValueTracking] Use computeConstantRange() in signed add overflow determination
This is D59386 for the signed add case. The computeConstantRange() result is now intersected into the existing known b
[ValueTracking] Use computeConstantRange() in signed add overflow determination
This is D59386 for the signed add case. The computeConstantRange() result is now intersected into the existing known bits information, allowing to detect additional no-overflow/always-overflow conditions (though the latter isn't used yet).
This (finally...) covers the motivating case from D59071.
Differential Revision: https://reviews.llvm.org/D60420
llvm-svn: 358014
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20838195 |
| 19-Mar-2019 |
Nikita Popov <nikita.ppv@gmail.com> |
[ValueTracking] Use computeConstantRange() for unsigned add/sub overflow
Improve computeOverflowForUnsignedAdd/Sub in ValueTracking by intersecting the computeConstantRange() result into the Constan
[ValueTracking] Use computeConstantRange() for unsigned add/sub overflow
Improve computeOverflowForUnsignedAdd/Sub in ValueTracking by intersecting the computeConstantRange() result into the ConstantRange created from computeKnownBits(). This allows us to detect some additional never/always overflows conditions that can't be determined from known bits.
This revision also adds basic handling for constants to computeConstantRange(). Non-splat vectors will be handled in a followup.
The signed case will also be handled in a followup, as it needs some more groundwork.
Differential Revision: https://reviews.llvm.org/D59386
llvm-svn: 356489
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Revision tags: llvmorg-8.0.0, llvmorg-8.0.0-rc5, llvmorg-8.0.0-rc4, llvmorg-8.0.0-rc3, llvmorg-7.1.0, llvmorg-7.1.0-rc1, llvmorg-8.0.0-rc2, llvmorg-8.0.0-rc1, llvmorg-7.0.1, llvmorg-7.0.1-rc3, llvmorg-7.0.1-rc2, llvmorg-7.0.1-rc1, llvmorg-7.0.0, llvmorg-7.0.0-rc3, llvmorg-7.0.0-rc2, llvmorg-7.0.0-rc1 |
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995138ce |
| 31-Jul-2018 |
Sanjay Patel <spatel@rotateright.com> |
[InstCombine] move/add tests for xor+add fold; NFC
llvm-svn: 338364
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Revision tags: llvmorg-6.0.1, llvmorg-6.0.1-rc3, llvmorg-6.0.1-rc2, llvmorg-6.0.1-rc1, llvmorg-5.0.2, llvmorg-5.0.2-rc2, llvmorg-5.0.2-rc1, llvmorg-6.0.0, llvmorg-6.0.0-rc3, llvmorg-6.0.0-rc2, llvmorg-6.0.0-rc1, llvmorg-5.0.1, llvmorg-5.0.1-rc3, llvmorg-5.0.1-rc2, llvmorg-5.0.1-rc1 |
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2d4e6504 |
| 12-Sep-2017 |
Sanjay Patel <spatel@rotateright.com> |
[InstCombine] move related tests together; NFC
llvm-svn: 313036
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Revision tags: llvmorg-5.0.0, llvmorg-5.0.0-rc5, llvmorg-5.0.0-rc4, llvmorg-5.0.0-rc3, llvmorg-5.0.0-rc2, llvmorg-5.0.0-rc1 |
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3437ee27 |
| 15-Jul-2017 |
Sanjay Patel <spatel@rotateright.com> |
[InstCombine] improve (1 << x) & 1 --> zext(x == 0) folding
1. Add a one-use check to prevent increasing instruction count. 2. Generalize the pattern matching to include vector types.
llvm-svn: 308
[InstCombine] improve (1 << x) & 1 --> zext(x == 0) folding
1. Add a one-use check to prevent increasing instruction count. 2. Generalize the pattern matching to include vector types.
llvm-svn: 308105
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a59aac67 |
| 15-Jul-2017 |
Sanjay Patel <spatel@rotateright.com> |
[InstCombine] add tests for (1 << x) & 1 --> zext(x == 0) ; NFC
This fold hit the trifecta: 1. It was untested. 2. It oversteps (multiuse is not checked, so increases instruction count). 3. It is in
[InstCombine] add tests for (1 << x) & 1 --> zext(x == 0) ; NFC
This fold hit the trifecta: 1. It was untested. 2. It oversteps (multiuse is not checked, so increases instruction count). 3. It is incomplete (doesn't work for vectors).
llvm-svn: 308102
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55b9f88e |
| 15-Jul-2017 |
Sanjay Patel <spatel@rotateright.com> |
[InstCombine] allow (0 - x) & 1 --> x & 1 for vectors
llvm-svn: 308098
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Revision tags: llvmorg-4.0.1, llvmorg-4.0.1-rc3, llvmorg-4.0.1-rc2, llvmorg-4.0.1-rc1 |
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9d39a9d8 |
| 14-Apr-2017 |
Sanjay Patel <spatel@rotateright.com> |
[InstCombine] add/move tests for and/or-of-icmps equality folds; NFC
llvm-svn: 300357
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e70dffeb |
| 13-Apr-2017 |
Craig Topper <craig.topper@gmail.com> |
[InstCombine] Add vector version of a test to show missing optimization.
llvm-svn: 300161
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