1;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2; Copyright(c) 2011-2015 Intel Corporation All rights reserved. 3; 4; Redistribution and use in source and binary forms, with or without 5; modification, are permitted provided that the following conditions 6; are met: 7; * Redistributions of source code must retain the above copyright 8; notice, this list of conditions and the following disclaimer. 9; * Redistributions in binary form must reproduce the above copyright 10; notice, this list of conditions and the following disclaimer in 11; the documentation and/or other materials provided with the 12; distribution. 13; * Neither the name of Intel Corporation nor the names of its 14; contributors may be used to endorse or promote products derived 15; from this software without specific prior written permission. 16; 17; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 29 30%include "reg_sizes.asm" 31%include "multibinary.asm" 32 33default rel 34[bits 64] 35 36extern pq_gen_base 37extern pq_gen_sse 38extern pq_gen_avx 39extern pq_gen_avx2 40 41extern xor_gen_base 42extern xor_gen_sse 43extern xor_gen_avx 44 45extern pq_check_base 46extern pq_check_sse 47 48extern xor_check_base 49extern xor_check_sse 50 51%ifdef HAVE_AS_KNOWS_AVX512 52 extern xor_gen_avx512 53 extern pq_gen_avx512 54%endif 55 56mbin_interface xor_gen 57mbin_interface pq_gen 58 59 60mbin_dispatch_init6 xor_gen, xor_gen_base, xor_gen_sse, xor_gen_avx, xor_gen_avx, xor_gen_avx512 61mbin_dispatch_init6 pq_gen, pq_gen_base, pq_gen_sse, pq_gen_avx, pq_gen_avx2, pq_gen_avx512 62 63section .data 64 65xor_check_dispatched: 66 dq xor_check_mbinit 67pq_check_dispatched: 68 dq pq_check_mbinit 69 70section .text 71 72;;;; 73; pq_check multibinary function 74;;;; 75mk_global pq_check, function 76pq_check_mbinit: 77 endbranch 78 call pq_check_dispatch_init 79pq_check: 80 endbranch 81 jmp qword [pq_check_dispatched] 82 83pq_check_dispatch_init: 84 push rax 85 push rbx 86 push rcx 87 push rdx 88 push rsi 89 lea rsi, [pq_check_base WRT_OPT] ; Default 90 91 mov eax, 1 92 cpuid 93 test ecx, FLAG_CPUID1_ECX_SSE4_1 94 lea rbx, [pq_check_sse WRT_OPT] 95 cmovne rsi, rbx 96 97 mov [pq_check_dispatched], rsi 98 pop rsi 99 pop rdx 100 pop rcx 101 pop rbx 102 pop rax 103 ret 104 105 106;;;; 107; xor_check multibinary function 108;;;; 109mk_global xor_check, function 110xor_check_mbinit: 111 endbranch 112 call xor_check_dispatch_init 113xor_check: 114 endbranch 115 jmp qword [xor_check_dispatched] 116 117xor_check_dispatch_init: 118 push rax 119 push rbx 120 push rcx 121 push rdx 122 push rsi 123 lea rsi, [xor_check_base WRT_OPT] ; Default 124 125 mov eax, 1 126 cpuid 127 test ecx, FLAG_CPUID1_ECX_SSE4_1 128 lea rbx, [xor_check_sse WRT_OPT] 129 cmovne rsi, rbx 130 131 mov [xor_check_dispatched], rsi 132 pop rsi 133 pop rdx 134 pop rcx 135 pop rbx 136 pop rax 137 ret 138