| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64Schedule.td | 25 def WriteISReg : SchedWrite; // ALU of Shifted-Reg
28 def ReadISReg : SchedRead; // ALU of Shifted-Reg
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| H A D | AArch64SchedA55.td | 65 def : WriteRes<WriteISReg, [CortexA55UnitALU]> { let Latency = 3; } // ALU of Shifted-Reg
187 // Shifted operand
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| H A D | AArch64SchedA57.td | 140 // Shifted Register with Shift == 0
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| /netbsd-src/external/gpl3/gdb.old/dist/sim/ppc/ |
| H A D | dc-complex | 30 # Add Immediate Shifted
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| H A D | dc-stupid | 30 # Add Immediate Shifted
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| H A D | RUN | 205 CPU #1 executed 943,823 Add Immediate Shifted instructions.
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| /netbsd-src/external/gpl3/gdb/dist/sim/ppc/ |
| H A D | dc-stupid | 30 # Add Immediate Shifted
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| H A D | dc-complex | 30 # Add Immediate Shifted
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| H A D | powerpc.igen | 2518 0.15,6.RT,11.RA,16.SI:D:::Add Immediate Shifted
2960 0.29,6.RS,11.RA,16.UI:D:::AND Immediate Shifted
2979 0.25,6.RS,11.RA,16.UI:D:::OR Immediate Shifted
2997 0.27,6.RS,11.RA,16.UI:D:::XOR Immediate Shifted
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| H A D | RUN | 205 CPU #1 executed 943,823 Add Immediate Shifted instructions.
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| H A D | ChangeLog-2021 | 4954 (Add/And/Or/Xor Shifted Immediate): Ditto.
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| /netbsd-src/external/apache2/llvm/dist/clang/lib/Tooling/ASTDiff/ |
| H A D | ASTDiff.cpp | 150 int findPositionInParent(NodeId Id, bool Shifted = false) const;
339 int SyntaxTree::Impl::findPositionInParent(NodeId Id, bool Shifted) const { in findPositionInParent()
346 if (Shifted) in findPositionInParent()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMFrameLowering.cpp | 2334 unsigned Shifted = 0; in alignToARMConstant() local
2341 Shifted += 2; in alignToARMConstant()
2350 if (Shifted > 24) in alignToARMConstant()
2351 Value = Value >> (Shifted - 24); in alignToARMConstant()
2353 Value = Value << (24 - Shifted); in alignToARMConstant()
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| H A D | ARMScheduleM7.td | 322 // Shifted ALU operands are read a cycle early.
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| H A D | ARMInstrThumb2.td | 54 // Shifted operands. No register controlled shifts for Thumb2.
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 1007 Value *Shifted = IC.Builder.CreateLShr(Masked, in instCombineIntrinsic() local
1010 return IC.replaceInstUsesWith(II, Shifted); in instCombineIntrinsic()
1051 Value *Shifted = IC.Builder.CreateShl(Input, in instCombineIntrinsic() local
1054 Value *Masked = IC.Builder.CreateAnd(Shifted, II.getArgOperand(1)); in instCombineIntrinsic()
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| /netbsd-src/external/apache2/llvm/dist/clang/lib/Format/ |
| H A D | Format.cpp | 2742 auto Shifted = tooling::Replacement(FileName, NewOffset, 0, in fixCppIncludeInsertions() local
2744 Result = Result.merge(tooling::Replacements(Shifted)); in fixCppIncludeInsertions()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| H A D | ScalarEvolution.cpp | 5235 const SCEV *Shifted = SCEVShiftRewriter::rewrite(BEValue, L, *this); in createAddRecFromPHI() local
5236 const SCEV *Start = SCEVInitRewriter::rewrite(Shifted, L, *this, false); in createAddRecFromPHI()
5237 if (Shifted != getCouldNotCompute() && in createAddRecFromPHI()
5245 ValueExprMap[SCEVCallbackVH(PN, this)] = Shifted; in createAddRecFromPHI()
5246 return Shifted; in createAddRecFromPHI()
11525 const SCEV *Shifted = SE.getAddRecExpr(Operands, getLoop(), in getNumIterationsInRange() local
11527 if (const auto *ShiftedAddRec = dyn_cast<SCEVAddRecExpr>(Shifted)) in getNumIterationsInRange()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 2977 auto Shifted = MIRBuilder.buildAShr(Ty, Res, ShiftAmt); in lower() local
2978 MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted); in lower()
6796 auto Shifted = MIRBuilder.buildInstr(ShiftOp, {WideTy}, {Mul, ShiftAmt}); in lowerSMULH_UMULH() local
6797 MIRBuilder.buildTrunc(Result, Shifted); in lowerSMULH_UMULH()
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| /netbsd-src/external/gpl3/gcc.old/dist/libgcc/config/avr/ |
| H A D | lib1funcs.S | 1871 ;; Shifted 64 Bits: A7 has traveled to C7
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| /netbsd-src/external/gpl3/gcc/dist/libgcc/config/avr/ |
| H A D | lib1funcs.S | 1871 ;; Shifted 64 Bits: A7 has traveled to C7
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 4523 SDValue Shifted = DAG.getNode(ISD::SRL, DL, XLenVT, in lowerGET_ROUNDING() local
4525 SDValue Masked = DAG.getNode(ISD::AND, DL, XLenVT, Shifted, in lowerGET_ROUNDING()
4553 SDValue Shifted = DAG.getNode(ISD::SRL, DL, XLenVT, in lowerSET_ROUNDING() local
4555 RMValue = DAG.getNode(ISD::AND, DL, XLenVT, Shifted, in lowerSET_ROUNDING()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/ |
| H A D | SimplifyCFG.cpp | 6056 Value *Shifted = Builder.CreateLShr(TableMask, MaskIndex, "switch.shifted"); in SwitchToLookupTable() local
6058 Shifted, Type::getInt1Ty(Mod.getContext()), "switch.lobit"); in SwitchToLookupTable()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 585 SDValue MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
6802 SDValue DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos, in MatchRotatePosNeg() argument
6813 EVT VT = Shifted.getValueType(); in MatchRotatePosNeg()
6817 return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, Shifted, in MatchRotatePosNeg()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 12935 auto Shifted = DAG.getNode(ISD::SRL, DL, MVT::i64, SubNode, in generateEquivalentSub() local
12937 auto Final = Shifted; in generateEquivalentSub()
12941 Final = DAG.getNode(ISD::XOR, DL, MVT::i64, Shifted, in generateEquivalentSub()
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