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Searched refs:Enc (Results 1 – 23 of 23) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DSIMCCodeEmitter.cpp421 uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI); in getSDWASrcEncoding() local
422 if (Enc != ~0U && Enc != 255) { in getSDWASrcEncoding()
423 return Enc | SDWA9EncValues::SRC_SGPR_MASK; in getSDWASrcEncoding()
455 uint64_t Enc = MRI.getEncodingValue(Reg); in getAVOperandEncoding() local
468 Enc |= 512; in getAVOperandEncoding()
470 return Enc; in getAVOperandEncoding()
537 uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI); in getMachineOpValue() local
538 if (Enc != ~0U && in getMachineOpValue()
539 (Enc != 255 || Desc.getSize() == 4 || Desc.getSize() == 8)) in getMachineOpValue()
540 return Enc; in getMachineOpValue()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td29 class MipsReg<bits<16> Enc, string n> : Register<n> {
30 let HWEncoding = Enc;
34 class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>
36 let HWEncoding = Enc;
41 class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>;
44 class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs>
45 : MipsRegWithSubRegs<Enc, n, subregs> {
50 class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>;
53 class AFPR<bits<16> Enc, string n, list<Register> subregs>
54 : MipsRegWithSubRegs<Enc, n, subregs> {
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.td17 class Wi<bits<16> Enc, string n> : Register<n> {
18 let HWEncoding = Enc;
24 class Ri<bits<16> Enc, string n, list<Register> subregs>
26 let HWEncoding = Enc;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td13 class SparcReg<bits<16> Enc, string n> : Register<n> {
14 let HWEncoding = Enc;
18 class SparcCtrlReg<bits<16> Enc, string n>: Register<n> {
19 let HWEncoding = Enc;
32 class Ri<bits<16> Enc, string n> : SparcReg<Enc, n>;
35 class Rdi<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
41 class Rf<bits<16> Enc, string n> : SparcReg<Enc, n>;
44 class Rd<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
51 class Rq<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Bitstream/
H A DBitCodes.h99 unsigned Enc : 3; // The encoding to use. variable
111 : Val(Data), IsLiteral(false), Enc(E) {} in Val()
120 Encoding getEncoding() const { assert(isEncoding()); return (Encoding)Enc; } in getEncoding()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMMCInstLower.cpp159 int32_t Enc = ARM_AM::getSOImmVal(MCOp.getImm()); in LowerARMMachineInstrToMCInst() local
160 if (Enc != -1) in LowerARMMachineInstrToMCInst()
161 MCOp.setImm(Enc); in LowerARMMachineInstrToMCInst()
H A DARMRegisterInfo.td16 class ARMReg<bits<16> Enc, string n, list<Register> subregs = [],
18 let HWEncoding = Enc;
25 class ARMFReg<bits<16> Enc, string n> : Register<n> {
26 let HWEncoding = Enc;
/netbsd-src/external/apache2/llvm/dist/clang/lib/CodeGen/
H A DTargetInfo.cpp9855 std::string Enc; member in __anon6bad40bc1a11::FieldEncoding
9857 FieldEncoding(bool b, SmallStringEnc &e) : HasName(b), Enc(e.c_str()) {} in FieldEncoding()
9858 StringRef str() { return Enc; } in str()
9861 return Enc < rhs.Enc; in operator <()
10043 static bool getTypeString(SmallStringEnc &Enc, const Decl *D,
10051 SmallStringEnc Enc; in emitTargetMD() local
10052 if (getTypeString(Enc, D, CGM, TSC)) { in emitTargetMD()
10055 llvm::MDString::get(Ctx, Enc.str())}; in emitTargetMD()
10123 static bool appendType(SmallStringEnc &Enc, QualType QType,
10135 SmallStringEnc Enc; in extractFieldType() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td14 class CSKYReg<bits<6> Enc, string n, list<string> alt = []> : Register<n> {
15 let HWEncoding{5 - 0} = Enc;
19 class CSKYFReg32<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
20 let HWEncoding{4 - 0} = Enc;
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Transforms/IPO/
H A DAttributor.h252 IRPosition() : Enc(nullptr, ENC_VALUE) { verify(); } in IRPosition()
330 return Enc == RHS.Enc && RHS.CBContext == CBContext;
573 operator void *() const { return Enc.getOpaqueValue(); }
579 Enc.setFromOpaqueValue(Ptr); in CBContext()
593 Enc = {&AnchorVal, ENC_FLOATING_FUNCTION}; in CBContext()
595 Enc = {&AnchorVal, ENC_VALUE}; in CBContext()
599 Enc = {&AnchorVal, ENC_VALUE}; in CBContext()
603 Enc = {&AnchorVal, ENC_RETURNED_VALUE}; in CBContext()
606 Enc = {&AnchorVal, ENC_VALUE}; in CBContext()
641 Enc = {&U, ENC_CALL_SITE_ARGUMENT_USE}; in IRPosition()
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/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DX86FoldTablesEmitter.cpp496 uint64_t Enc = getValueFromBitsInit(RegRec->getValueAsBitsInit("OpEncBits")); in addEntryWithFlags() local
503 } else if (Enc != X86Local::XOP && Enc != X86Local::VEX && in addEntryWithFlags()
504 Enc != X86Local::EVEX) { in addEntryWithFlags()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td14 class RISCVReg<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
15 let HWEncoding{4-0} = Enc;
19 class RISCVReg16<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
20 let HWEncoding{4-0} = Enc;
45 class RISCVRegWithSubRegs<bits<5> Enc, string n, list<Register> subregs,
48 let HWEncoding{4-0} = Enc;
/netbsd-src/crypto/external/bsd/openssl/dist/doc/man3/
H A DSSL_CIPHER_get_name.pod141 =item Enc=<symmetric encryption method>
153 ECDHE-RSA-AES256-GCM-SHA256 TLSv1.2 Kx=ECDH Au=RSA Enc=AESGCM(256) Mac=AEAD
154 RSA-PSK-AES256-CBC-SHA384 TLSv1.0 Kx=RSAPSK Au=RSA Enc=AES(256) Mac=SHA384
/netbsd-src/crypto/external/bsd/openssl.old/dist/doc/man3/
H A DSSL_CIPHER_get_name.pod141 =item Enc=<symmetric encryption method>
153 ECDHE-RSA-AES256-GCM-SHA256 TLSv1.2 Kx=ECDH Au=RSA Enc=AESGCM(256) Mac=AEAD
154 RSA-PSK-AES256-CBC-SHA384 TLSv1.0 Kx=RSAPSK Au=RSA Enc=AES(256) Mac=SHA384
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp5077 uint64_t Enc = (32 - *MaybeImmed) & 0x1f; in selectShiftA_32() local
5078 return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}}; in selectShiftA_32()
5086 uint64_t Enc = 31 - *MaybeImmed; in selectShiftB_32() local
5087 return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}}; in selectShiftB_32()
5095 uint64_t Enc = (64 - *MaybeImmed) & 0x3f; in selectShiftA_64() local
5096 return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}}; in selectShiftA_64()
5104 uint64_t Enc = 63 - *MaybeImmed; in selectShiftB_64() local
5105 return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}}; in selectShiftB_64()
5906 uint64_t Enc = AArch64_AM::encodeLogicalImmediate(CstVal, 32); in renderLogicalImm32() local
5907 MIB.addImm(Enc); in renderLogicalImm32()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp2622 uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue()); in addModImmNotOperands() local
2623 Inst.addOperand(MCOperand::createImm(Enc)); in addModImmNotOperands()
2629 uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue()); in addModImmNegOperands() local
2630 Inst.addOperand(MCOperand::createImm(Enc)); in addModImmNegOperands()
4451 unsigned Enc, unsigned Reg) { in insertNoDuplicates() argument
4452 Regs.emplace_back(Enc, Reg); in insertNoDuplicates()
4454 if (J->first == Enc) { in insertNoDuplicates()
4458 if (J->first < Enc) in insertNoDuplicates()
5471 int Enc = ARM_AM::getSOImmVal(Imm1); in parseModImm() local
5472 if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) { in parseModImm()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86RegisterInfo.td15 class X86Reg<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> {
17 let HWEncoding = Enc;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIInsertWaitcnts.cpp1192 unsigned Enc = AMDGPU::encodeWaitcnt(IV, Wait); in generateWaitcntInstBefore() local
1195 .addImm(Enc); in generateWaitcntInstBefore()
H A DBUFInstructions.td2261 class MUBUF_Real_Base_vi <bits<7> op, MUBUF_Pseudo ps, int Enc,
2265 SIMCInstr<ps.PseudoInstr, Enc>,
2498 class MTBUF_Real_Base_vi <bits<4> op, MTBUF_Pseudo ps, int Enc> :
2501 SIMCInstr<ps.PseudoInstr, Enc> {
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp2040 if (unsigned Enc = dwarf::getAttributeEncoding(Token.stringValue())) { in parseDIExpression() local
2042 Elements.push_back(Enc); in parseDIExpression()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/IPO/
H A DAttributor.cpp484 assert(!Enc.getOpaqueValue() && in verify()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp3785 const auto Enc = VOP1 | VOP2 | VOP3 | VOPC | VOP3P | SIInstrFlags::SDWA; in validateLdsDirect() local
3786 if ((Desc.TSFlags & Enc) == 0) in validateLdsDirect()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1553 uint64_t OldImm = Imm, NewImm, Enc; in optimizeLogicalImm() local
1635 Enc = AArch64_AM::encodeLogicalImmediate(NewImm, Size); in optimizeLogicalImm()
1636 SDValue EncConst = TLO.DAG.getTargetConstant(Enc, DL, VT); in optimizeLogicalImm()