| /openbsd-src/sys/dev/pci/drm/i915/display/ |
| H A D | intel_overlay.c | 841 params->src_width); in intel_overlay_do_put_image()
843 tmp_width = params->src_width; in intel_overlay_do_put_image()
845 swidth = params->src_width; in intel_overlay_do_put_image()
856 swidth |= (params->src_width / uv_hscale) << 16; in intel_overlay_do_put_image()
860 params->src_width / uv_hscale); in intel_overlay_do_put_image()
862 params->src_width / uv_hscale); in intel_overlay_do_put_image()
1011 rec->src_width > IMAGE_MAX_WIDTH_LEGACY) in check_overlay_src()
1015 rec->src_width > IMAGE_MAX_WIDTH) in check_overlay_src()
1021 rec->src_width < N_HORIZ_Y_TAPS*4) in check_overlay_src()
1057 if (rec->src_width % uv_hscale) in check_overlay_src()
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| /openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_dwb.c | 78 REG_UPDATE_2(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, params->cnv_params.src_width, in dwb2_config_dwb_cnv()
104 if ((params->cnv_params.src_width != params->dest_width) || in dwb2_enable()
164 if ((params->cnv_params.src_width != params->dest_width) || in dwb2_update()
290 dwb_program_horz_scalar(dwbc20, params->cnv_params.src_width, in dwb2_set_scaler()
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| H A D | dcn20_dwb_scl.c | 723 uint32_t src_width, in dwb_program_horz_scalar()
746 src_width, dest_width); in dwb_program_horz_scalar()
720 dwb_program_horz_scalar(struct dcn20_dwbc * dwbc20,uint32_t src_width,uint32_t dest_width,struct scaling_taps num_taps) dwb_program_horz_scalar() argument
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| H A D | dcn20_dwb.h | 424 uint32_t src_width,
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| /openbsd-src/sys/dev/pci/drm/amd/display/dc/ |
| H A D | dm_services_types.h | 128 uint32_t src_width; member
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| H A D | dc_types.h | 413 unsigned int src_width; /* input active width */
412 unsigned int src_width; /* input active width */ global() member
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| /openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_dwb.c | 71 REG_UPDATE_2(FC_SOURCE_SIZE, FC_SOURCE_WIDTH, params->cnv_params.src_width, in dwb3_config_fc()
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| /openbsd-src/sys/dev/pci/drm/amd/amdgpu/ |
| H A D | dce_v8_0.c | 636 u32 src_width; /* viewport width */ member
801 fixed20_12 src_width; in dce_v8_0_average_bandwidth() local
809 src_width.full = dfixed_const(wm->src_width); in dce_v8_0_average_bandwidth()
810 bandwidth.full = dfixed_mul(src_width, bpp); in dce_v8_0_average_bandwidth()
862 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in dce_v8_0_latency_watermark()
927 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v8_0_check_latency_hiding()
992 wm_high.src_width = mode->crtc_hdisplay; in dce_v8_0_program_watermarks()
1031 wm_low.src_width = mode->crtc_hdisplay; in dce_v8_0_program_watermarks()
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| H A D | dce_v6_0.c | 501 u32 src_width; /* viewport width */ member
666 fixed20_12 src_width; in dce_v6_0_average_bandwidth() local
674 src_width.full = dfixed_const(wm->src_width); in dce_v6_0_average_bandwidth()
675 bandwidth.full = dfixed_mul(src_width, bpp); in dce_v6_0_average_bandwidth()
727 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in dce_v6_0_latency_watermark()
792 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v6_0_check_latency_hiding()
866 wm_high.src_width = mode->crtc_hdisplay; in dce_v6_0_program_watermarks()
893 wm_low.src_width = mode->crtc_hdisplay; in dce_v6_0_program_watermarks()
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| H A D | dce_v10_0.c | 697 u32 src_width; /* viewport width */ member
862 fixed20_12 src_width; in dce_v10_0_average_bandwidth() local
870 src_width.full = dfixed_const(wm->src_width); in dce_v10_0_average_bandwidth()
871 bandwidth.full = dfixed_mul(src_width, bpp); in dce_v10_0_average_bandwidth()
923 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in dce_v10_0_latency_watermark()
988 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v10_0_check_latency_hiding()
1053 wm_high.src_width = mode->crtc_hdisplay; in dce_v10_0_program_watermarks()
1092 wm_low.src_width = mode->crtc_hdisplay; in dce_v10_0_program_watermarks()
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| H A D | dce_v11_0.c | 729 u32 src_width; /* viewport width */ member
894 fixed20_12 src_width; in dce_v11_0_average_bandwidth() local
902 src_width.full = dfixed_const(wm->src_width); in dce_v11_0_average_bandwidth()
903 bandwidth.full = dfixed_mul(src_width, bpp); in dce_v11_0_average_bandwidth()
955 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in dce_v11_0_latency_watermark()
1020 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v11_0_check_latency_hiding()
1085 wm_high.src_width = mode->crtc_hdisplay; in dce_v11_0_program_watermarks()
1124 wm_low.src_width = mode->crtc_hdisplay; in dce_v11_0_program_watermarks()
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| /openbsd-src/sys/dev/pci/drm/amd/display/dc/dml/calcs/ |
| H A D | dce_calcs.c | 403 data->src_width[maximum_number_of_surfaces - 2] = data->src_width[5]; in calculate_bandwidth()
404 data->src_width[maximum_number_of_surfaces - 1] = data->src_width[5]; in calculate_bandwidth()
407 data->pitch_in_pixels[maximum_number_of_surfaces - 2] = data->src_width[5]; in calculate_bandwidth()
408 data->pitch_in_pixels[maximum_number_of_surfaces - 1] = data->src_width[5]; in calculate_bandwidth()
441 data->src_width_after_surface_type = bw_div(data->src_width[i], bw_int_to_fixed(2)); in calculate_bandwidth()
448 data->src_width_after_surface_type = data->src_width[i]; in calculate_bandwidth()
2827 data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width); in populate_initial_data()
2828 data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4]; in populate_initial_data()
2883 …data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.vi… in populate_initial_data()
2930 data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width); in populate_initial_data()
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| H A D | calcs_logger.h | 423 DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_width[%d]:%d", i, bw_fixed_to_int(data->src_width[i])); in print_bw_calcs_data()
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| /openbsd-src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/ |
| H A D | dce110_clk_mgr.c | 150 cfg->src_width = stream->src.width; in dce110_fill_display_configs()
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| /openbsd-src/sys/dev/pci/drm/radeon/ |
| H A D | evergreen.c | 1938 u32 src_width; /* viewport width */ member
2047 fixed20_12 src_width; in evergreen_average_bandwidth() local
2055 src_width.full = dfixed_const(wm->src_width); in evergreen_average_bandwidth()
2056 bandwidth.full = dfixed_mul(src_width, bpp); in evergreen_average_bandwidth()
2096 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in evergreen_latency_watermark()
2130 u32 lb_partitions = wm->lb_size / wm->src_width; in evergreen_check_latency_hiding()
2193 wm_high.src_width = mode->crtc_hdisplay; in evergreen_program_watermarks()
2220 wm_low.src_width = mode->crtc_hdisplay; in evergreen_program_watermarks()
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| H A D | si.c | 2057 u32 src_width; /* viewport width */ member
2183 fixed20_12 src_width; in dce6_average_bandwidth() local
2191 src_width.full = dfixed_const(wm->src_width); in dce6_average_bandwidth()
2192 bandwidth.full = dfixed_mul(src_width, bpp); in dce6_average_bandwidth()
2235 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in dce6_latency_watermark()
2269 u32 lb_partitions = wm->lb_size / wm->src_width; in dce6_check_latency_hiding()
2335 wm_high.src_width = mode->crtc_hdisplay; in dce6_program_watermarks()
2362 wm_low.src_width = mode->crtc_hdisplay; in dce6_program_watermarks()
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| H A D | cik.c | 8905 u32 src_width; /* viewport width */ member
9070 fixed20_12 src_width; in dce8_average_bandwidth() local
9078 src_width.full = dfixed_const(wm->src_width); in dce8_average_bandwidth()
9079 bandwidth.full = dfixed_mul(src_width, bpp); in dce8_average_bandwidth()
9131 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in dce8_latency_watermark()
9196 u32 lb_partitions = wm->lb_size / wm->src_width; in dce8_check_latency_hiding()
9262 wm_high.src_width = mode->crtc_hdisplay; in dce8_program_watermarks()
9302 wm_low.src_width = mode->crtc_hdisplay; in dce8_program_watermarks()
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| /openbsd-src/sys/dev/pci/drm/amd/display/dc/inc/ |
| H A D | dce_calcs.h | 391 struct bw_fixed src_width[maximum_number_of_surfaces]; member
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| /openbsd-src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/ |
| H A D | dcn30_fpu.c | 289 wb_info->dwb_params.cnv_params.src_width; in dcn30_fpu_populate_dml_writeback_from_context()
306 (double)wb_info->dwb_params.cnv_params.src_width / in dcn30_fpu_populate_dml_writeback_from_context()
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| /openbsd-src/sys/dev/pci/drm/amd/display/dc/dce/ |
| H A D | dce_clk_mgr.c | 526 cfg->src_width = stream->src.width; in dce110_fill_display_configs()
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| /openbsd-src/sys/dev/pci/drm/include/uapi/drm/ |
| H A D | i915_drm.h | 1862 __u16 src_width; member
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| /openbsd-src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 2505 wb_info->dwb_params.cnv_params.src_width; in dcn201_populate_dml_writeback_from_context_fpu()
2515 (double)wb_info->dwb_params.cnv_params.src_width / in dcn201_populate_dml_writeback_from_context_fpu()
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