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Searched refs:num_levels (Results 1 – 25 of 42) sorted by relevance

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/openbsd-src/sys/dev/pci/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_pp_smu.c122 clks->num_levels = 6; in get_default_clock_levels()
127 clks->num_levels = 6; in get_default_clock_levels()
132 clks->num_levels = 2; in get_default_clock_levels()
137 clks->num_levels = 0; in get_default_clock_levels()
224 dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS; in pp_to_dc_clock_levels()
226 dc_clks->num_levels = pp_clks->count; in pp_to_dc_clock_levels()
231 for (i = 0; i < dc_clks->num_levels; i++) { in pp_to_dc_clock_levels()
244 if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) { in pp_to_dc_clock_levels_with_latency()
247 pp_clks->num_levels, in pp_to_dc_clock_levels_with_latency()
250 clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS; in pp_to_dc_clock_levels_with_latency()
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/openbsd-src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c80 static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *entry_0, unsigned int *num_levels) in dcn3_init_single_clock() argument
88 *num_levels = 2; in dcn3_init_single_clock()
91 /* will set num_levels to 0 on failure */ in dcn3_init_single_clock()
92 *num_levels = ret & 0xFF; in dcn3_init_single_clock()
94 /* if the initial message failed, num_levels will be 0 */ in dcn3_init_single_clock()
95 for (i = 0; i < *num_levels; i++) { in dcn3_init_single_clock()
111 unsigned int num_levels; in dcn3_init_clocks() local
134 &num_levels); in dcn3_init_clocks()
140 &num_levels); in dcn3_init_clocks()
145 &num_levels); in dcn3_init_clocks()
409 unsigned int num_levels; dcn3_get_memclk_states_from_smu() local
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/openbsd-src/sys/dev/pci/drm/amd/display/dc/dce112/
H A Ddce112_resource.c1090 clks.clocks_in_khz[clks.num_levels-1], 1000); in bw_calcs_data_update_from_pplib()
1092 clks.clocks_in_khz[clks.num_levels/8], 1000); in bw_calcs_data_update_from_pplib()
1094 clks.clocks_in_khz[clks.num_levels*2/8], 1000); in bw_calcs_data_update_from_pplib()
1096 clks.clocks_in_khz[clks.num_levels*3/8], 1000); in bw_calcs_data_update_from_pplib()
1098 clks.clocks_in_khz[clks.num_levels*4/8], 1000); in bw_calcs_data_update_from_pplib()
1100 clks.clocks_in_khz[clks.num_levels*5/8], 1000); in bw_calcs_data_update_from_pplib()
1102 clks.clocks_in_khz[clks.num_levels*6/8], 1000); in bw_calcs_data_update_from_pplib()
1115 clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier, in bw_calcs_data_update_from_pplib()
1118 clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier, in bw_calcs_data_update_from_pplib()
1126 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
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/openbsd-src/sys/dev/pci/drm/amd/display/dc/dce120/
H A Ddce120_resource.c929 &eng_clks) || eng_clks.num_levels == 0) { in bw_calcs_data_update_from_pplib()
931 eng_clks.num_levels = 8; in bw_calcs_data_update_from_pplib()
934 for (i = 0; i < eng_clks.num_levels; i++) { in bw_calcs_data_update_from_pplib()
942 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
944 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
946 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
948 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
950 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
952 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
954 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
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/openbsd-src/sys/dev/pci/drm/radeon/
H A Dsumo_dpm.c347 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; in sumo_program_bsp()
354 for (i = 0; i < ps->num_levels - 1; i++) in sumo_program_bsp()
408 for (i = 0; i < ps->num_levels; i++) { in sumo_program_at()
409 asi = (i == ps->num_levels - 1) ? pi->pasi : pi->asi; in sumo_program_at()
423 a_t = CG_R(m_a * r[ps->num_levels - 1] / 100) | in sumo_program_at()
424 CG_L(m_a * l[ps->num_levels - 1] / 100); in sumo_program_at()
670 pi->boost_pl = new_ps->levels[new_ps->num_levels - 1]; in sumo_patch_boost_state()
743 dpm_ctrl4 |= (1 << (new_ps->num_levels - 1)); in sumo_program_wl()
759 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels; in sumo_program_power_levels_0_to_n()
761 for (i = 0; i < new_ps->num_levels; i++) { in sumo_program_power_levels_0_to_n()
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H A Dtrinity_dpm.c802 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels; in trinity_program_power_levels_0_to_n()
804 for (i = 0; i < new_ps->num_levels; i++) { in trinity_program_power_levels_0_to_n()
809 for (i = new_ps->num_levels; i < n_current_state_levels; i++) in trinity_program_power_levels_0_to_n()
925 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in trinity_set_uvd_clock_before_set_eng_clock()
926 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_before_set_eng_clock()
939 if (new_ps->levels[new_ps->num_levels - 1].sclk < in trinity_set_uvd_clock_after_set_eng_clock()
940 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_after_set_eng_clock()
1165 if (ps->num_levels <= 1) in trinity_dpm_force_performance_level()
1172 ret = trinity_dpm_n_levels_disabled(rdev, ps->num_levels - 1); in trinity_dpm_force_performance_level()
1176 for (i = 0; i < ps->num_levels; i++) { in trinity_dpm_force_performance_level()
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H A Dr100_track.h44 unsigned num_levels; member
H A Dkv_dpm.c1545 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1552 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1571 new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1580 new_ps->levels[new_ps->num_levels -1].sclk)) in kv_set_valid_clock_range()
1985 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
1991 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2003 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2014 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2376 ps->num_levels = 1; in kv_patch_boot_state()
2421 ps->num_levels = index + 1; in kv_parse_pplib_clock_info()
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H A Dtrinity_dpm.h48 u32 num_levels; member
/openbsd-src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c126 unsigned int *num_levels) in dcn32_init_single_clock() argument
135 *num_levels = 2; in dcn32_init_single_clock()
138 /* will set num_levels to 0 on failure */ in dcn32_init_single_clock()
139 *num_levels = ret & 0xFF; in dcn32_init_single_clock()
141 /* if the initial message failed, num_levels will be 0 */ in dcn32_init_single_clock()
142 for (i = 0; i < *num_levels; i++) { in dcn32_init_single_clock()
158 unsigned int num_levels; in dcn32_init_clocks() local
206 num_levels = num_entries_per_clk->num_dispclk_levels; in dcn32_init_clocks()
218 for (i = 0; i < num_levels; i++) in dcn32_init_clocks()
224 for (i = 0; i < num_levels; in dcn32_init_clocks()
842 unsigned int num_levels; dcn32_get_memclk_states_from_smu() local
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/openbsd-src/sys/dev/pci/drm/amd/display/dc/
H A Ddm_services_types.h98 uint32_t num_levels; member
108 uint32_t num_levels; member
118 uint32_t num_levels; member
/openbsd-src/sys/dev/pci/drm/i915/display/
H A Di9xx_wm.c828 dev_priv->display.wm.num_levels = G4X_WM_LEVEL_HPLL + 1; in g4x_setup_wm_latency()
935 for (; level < dev_priv->display.wm.num_levels; level++) { in g4x_raw_plane_wm_set()
954 for (; level < dev_priv->display.wm.num_levels; level++) { in g4x_raw_fbc_wm_set()
984 for (level = 0; level < dev_priv->display.wm.num_levels; level++) { in g4x_raw_plane_wm_compute()
1054 if (level >= dev_priv->display.wm.num_levels) in g4x_raw_crtc_wm_is_valid()
1390 dev_priv->display.wm.num_levels = VLV_WM_LEVEL_PM2 + 1; in vlv_setup_wm_latency()
1396 dev_priv->display.wm.num_levels = VLV_WM_LEVEL_DDR_DVFS + 1; in vlv_setup_wm_latency()
1532 for (; level < dev_priv->display.wm.num_levels; level++) { in vlv_invalidate_wms()
1561 for (; level < dev_priv->display.wm.num_levels; level++) { in vlv_raw_plane_wm_set()
1585 for (level = 0; level < dev_priv->display.wm.num_levels; level++) { in vlv_raw_plane_wm_compute()
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H A Dintel_wm.c151 for (level = 0; level < dev_priv->display.wm.num_levels; level++) { in intel_print_wm_latency()
191 for (level = 0; level < dev_priv->display.wm.num_levels; level++) { in wm_latency_show()
311 if (ret != dev_priv->display.wm.num_levels) in wm_latency_write()
316 for (level = 0; level < dev_priv->display.wm.num_levels; level++) in wm_latency_write()
H A Dskl_watermark.c364 for (level = i915->display.wm.num_levels - 1; in skl_crtc_can_enable_sagv()
752 for (level = 0; level < i915->display.wm.num_levels; level++) { in skl_cursor_allocation()
1528 for (level = i915->display.wm.num_levels - 1; level >= 0; level--) { in skl_crtc_allocate_plane_ddb()
1604 for (level++; level < i915->display.wm.num_levels; level++) { in skl_crtc_allocate_plane_ddb()
1993 for (level = 0; level < i915->display.wm.num_levels; level++) { in skl_compute_wm_levels()
2245 for (level = i915->display.wm.num_levels - 1; level >= 0; level--) { in skl_max_wm_level_for_vblank()
2283 crtc_state->wm_level_disabled = level < i915->display.wm.num_levels - 1; in skl_wm_check_vblank()
2285 for (level++; level < i915->display.wm.num_levels; level++) { in skl_wm_check_vblank()
2392 for (level = 0; level < i915->display.wm.num_levels; level++) in skl_write_plane_wm()
2427 for (level = 0; level < i915->display.wm.num_levels; level++) in skl_write_cursor_wm()
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/openbsd-src/sys/dev/pci/drm/amd/include/
H A Ddm_pp_interface.h175 uint32_t num_levels; member
185 uint32_t num_levels; member
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dce110/
H A Ddce110_resource.c1294 clks.clocks_in_khz[clks.num_levels-1], 1000); in bw_calcs_data_update_from_pplib()
1296 clks.clocks_in_khz[clks.num_levels/8], 1000); in bw_calcs_data_update_from_pplib()
1298 clks.clocks_in_khz[clks.num_levels*2/8], 1000); in bw_calcs_data_update_from_pplib()
1300 clks.clocks_in_khz[clks.num_levels*3/8], 1000); in bw_calcs_data_update_from_pplib()
1302 clks.clocks_in_khz[clks.num_levels*4/8], 1000); in bw_calcs_data_update_from_pplib()
1304 clks.clocks_in_khz[clks.num_levels*5/8], 1000); in bw_calcs_data_update_from_pplib()
1306 clks.clocks_in_khz[clks.num_levels*6/8], 1000); in bw_calcs_data_update_from_pplib()
1317 clks.clocks_in_khz[clks.num_levels-1], 1000); in bw_calcs_data_update_from_pplib()
1319 clks.clocks_in_khz[clks.num_levels>>1], 1000); in bw_calcs_data_update_from_pplib()
1332 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ, in bw_calcs_data_update_from_pplib()
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/
H A Ddce110_clk_mgr.c76 if (dc->sclk_lvls.num_levels == 0) in determine_sclk_from_bounding_box()
79 for (i = 0; i < dc->sclk_lvls.num_levels; i++) { in determine_sclk_from_bounding_box()
89 return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1]; in determine_sclk_from_bounding_box()
/openbsd-src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
H A Dsmu10_hwmgr.c1207 clocks->num_levels = 0; in smu10_get_clock_by_type_with_latency()
1210 clocks->data[clocks->num_levels].clocks_in_khz = in smu10_get_clock_by_type_with_latency()
1212 clocks->data[clocks->num_levels].latency_in_us = latency_required ? in smu10_get_clock_by_type_with_latency()
1216 clocks->num_levels++; in smu10_get_clock_by_type_with_latency()
1261 clocks->num_levels = 0; in smu10_get_clock_by_type_with_voltage()
1264 clocks->data[clocks->num_levels].clocks_in_khz = pclk_vol_table->entries[i].clk * 10; in smu10_get_clock_by_type_with_voltage()
1265 clocks->data[clocks->num_levels].voltage_in_mv = pclk_vol_table->entries[i].vol; in smu10_get_clock_by_type_with_voltage()
1266 clocks->num_levels++; in smu10_get_clock_by_type_with_voltage()
/openbsd-src/sys/dev/pci/drm/amd/pm/swsmu/smu13/
H A Daldebaran_ppt.c562 clocks->num_levels = min_t(uint32_t, in aldebaran_get_clk_table()
566 for (i = 0; i < clocks->num_levels; i++) { in aldebaran_get_clk_table()
784 display_levels = (clocks.num_levels == 1) ? 1 : 2; in aldebaran_print_clk_levels()
828 for (i = 0; i < clocks.num_levels; i++) in aldebaran_print_clk_levels()
831 (clocks.num_levels == 1) ? "*" : in aldebaran_print_clk_levels()
851 for (i = 0; i < clocks.num_levels; i++) in aldebaran_print_clk_levels()
854 (clocks.num_levels == 1) ? "*" : in aldebaran_print_clk_levels()
877 (clocks.num_levels == 1) ? "*" : in aldebaran_print_clk_levels()
900 (clocks.num_levels == 1) ? "*" : in aldebaran_print_clk_levels()
923 (clocks.num_levels in aldebaran_print_clk_levels()
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H A Dsmu_v13_0_6_ppt.c645 clocks->num_levels = count; in smu_v13_0_6_get_clk_table()
861 for (i = 0; i < clocks.num_levels; i++) in smu_v13_0_6_print_clk_levels()
865 (clocks.num_levels == 1) ? in smu_v13_0_6_print_clk_levels()
892 for (i = 0; i < clocks.num_levels; i++) in smu_v13_0_6_print_clk_levels()
896 (clocks.num_levels == 1) ? in smu_v13_0_6_print_clk_levels()
927 (clocks.num_levels == 1) ? in smu_v13_0_6_print_clk_levels()
958 (clocks.num_levels == 1) ? in smu_v13_0_6_print_clk_levels()
989 (clocks.num_levels == 1) ? in smu_v13_0_6_print_clk_levels()
/openbsd-src/gnu/llvm/lldb/source/Interpreter/
H A DOptions.cpp109 int num_levels = GetRequiredOptions().size(); in VerifyOptions() local
110 if (num_levels) { in VerifyOptions()
111 for (int i = 0; i < num_levels && !options_are_valid; ++i) { in VerifyOptions()
570 int num_levels = GetRequiredOptions().size(); in VerifyPartialOptions() local
571 if (num_levels) { in VerifyPartialOptions()
572 for (int i = 0; i < num_levels && !options_are_valid; ++i) { in VerifyPartialOptions()
/openbsd-src/lib/libcrypto/x509/
H A Dx509_policy.c775 int num_levels, user_has_any_policy; in has_explicit_policy() local
782 num_levels = sk_X509_POLICY_LEVEL_num(levels); in has_explicit_policy()
783 level = sk_X509_POLICY_LEVEL_value(levels, num_levels - 1); in has_explicit_policy()
824 for (i = num_levels - 1; i >= 0; i--) { in has_explicit_policy()
/openbsd-src/sys/dev/pci/drm/amd/pm/legacy-dpm/
H A Damdgpu_kv_dpm.c1782 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1789 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1808 new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1817 new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
2246 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2252 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2264 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2275 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2640 ps->num_levels = 1; in kv_patch_boot_state()
2685 ps->num_levels = index + 1; in kv_parse_pplib_clock_info()
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/openbsd-src/sys/dev/pci/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c1453 ASSERT(fclks->num_levels); in dcn_bw_update_from_pplib_fclks()
1456 vmid0p72_idx = fclks->num_levels > 2 ? fclks->num_levels - 3 : 0; in dcn_bw_update_from_pplib_fclks()
1457 vnom0p8_idx = fclks->num_levels > 1 ? fclks->num_levels - 2 : 0; in dcn_bw_update_from_pplib_fclks()
1458 vmax0p9_idx = fclks->num_levels > 0 ? fclks->num_levels - 1 : 0; in dcn_bw_update_from_pplib_fclks()
1480 if (dcfclks->num_levels >= 3) { in dcn_bw_update_from_pplib_dcfclks()
1482 dc->dcn_soc->dcfclkv_mid0p72 = dcfclks->data[dcfclks->num_levels - 3].clocks_in_khz / 1000.0; in dcn_bw_update_from_pplib_dcfclks()
1483 dc->dcn_soc->dcfclkv_nom0p8 = dcfclks->data[dcfclks->num_levels in dcn_bw_update_from_pplib_dcfclks()
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/openbsd-src/sys/dev/pci/drm/amd/pm/swsmu/smu11/
H A Darcturus_ppt.c578 clocks->num_levels = min_t(uint32_t, in arcturus_get_clk_table()
582 for (i = 0; i < clocks->num_levels; i++) { in arcturus_get_clk_table()
799 for (i = 0; i < clocks.num_levels; i++) in arcturus_print_clk_levels()
802 (clocks.num_levels == 1) ? "*" : in arcturus_print_clk_levels()
822 for (i = 0; i < clocks.num_levels; i++) in arcturus_print_clk_levels()
825 (clocks.num_levels == 1) ? "*" : in arcturus_print_clk_levels()
845 for (i = 0; i < clocks.num_levels; i++) in arcturus_print_clk_levels()
848 (clocks.num_levels == 1) ? "*" : in arcturus_print_clk_levels()
871 (clocks.num_levels == 1) ? "*" : in arcturus_print_clk_levels()
894 (clocks.num_levels == 1) ? "*" : in arcturus_print_clk_levels()
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