1*7ccd5a2cSjsg /* 2*7ccd5a2cSjsg * Copyright 2012 Advanced Micro Devices, Inc. 3*7ccd5a2cSjsg * 4*7ccd5a2cSjsg * Permission is hereby granted, free of charge, to any person obtaining a 5*7ccd5a2cSjsg * copy of this software and associated documentation files (the "Software"), 6*7ccd5a2cSjsg * to deal in the Software without restriction, including without limitation 7*7ccd5a2cSjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*7ccd5a2cSjsg * and/or sell copies of the Software, and to permit persons to whom the 9*7ccd5a2cSjsg * Software is furnished to do so, subject to the following conditions: 10*7ccd5a2cSjsg * 11*7ccd5a2cSjsg * The above copyright notice and this permission notice shall be included in 12*7ccd5a2cSjsg * all copies or substantial portions of the Software. 13*7ccd5a2cSjsg * 14*7ccd5a2cSjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*7ccd5a2cSjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*7ccd5a2cSjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*7ccd5a2cSjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*7ccd5a2cSjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*7ccd5a2cSjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*7ccd5a2cSjsg * OTHER DEALINGS IN THE SOFTWARE. 21*7ccd5a2cSjsg * 22*7ccd5a2cSjsg */ 23*7ccd5a2cSjsg #ifndef __TRINITY_DPM_H__ 24*7ccd5a2cSjsg #define __TRINITY_DPM_H__ 25*7ccd5a2cSjsg 26*7ccd5a2cSjsg #include "sumo_dpm.h" 27*7ccd5a2cSjsg 28*7ccd5a2cSjsg #define TRINITY_SIZEOF_DPM_STATE_TABLE (SMU_SCLK_DPM_STATE_1_CNTL_0 - SMU_SCLK_DPM_STATE_0_CNTL_0) 29*7ccd5a2cSjsg 30*7ccd5a2cSjsg struct trinity_pl { 31*7ccd5a2cSjsg u32 sclk; 32*7ccd5a2cSjsg u8 vddc_index; 33*7ccd5a2cSjsg u8 ds_divider_index; 34*7ccd5a2cSjsg u8 ss_divider_index; 35*7ccd5a2cSjsg u8 allow_gnb_slow; 36*7ccd5a2cSjsg u8 force_nbp_state; 37*7ccd5a2cSjsg u8 display_wm; 38*7ccd5a2cSjsg u8 vce_wm; 39*7ccd5a2cSjsg }; 40*7ccd5a2cSjsg 41*7ccd5a2cSjsg #define TRINITY_POWERSTATE_FLAGS_NBPS_FORCEHIGH (1 << 0) 42*7ccd5a2cSjsg #define TRINITY_POWERSTATE_FLAGS_NBPS_LOCKTOHIGH (1 << 1) 43*7ccd5a2cSjsg #define TRINITY_POWERSTATE_FLAGS_NBPS_LOCKTOLOW (1 << 2) 44*7ccd5a2cSjsg 45*7ccd5a2cSjsg #define TRINITY_POWERSTATE_FLAGS_BAPM_DISABLE (1 << 0) 46*7ccd5a2cSjsg 47*7ccd5a2cSjsg struct trinity_ps { 48*7ccd5a2cSjsg u32 num_levels; 49*7ccd5a2cSjsg struct trinity_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS]; 50*7ccd5a2cSjsg 51*7ccd5a2cSjsg u32 nbps_flags; 52*7ccd5a2cSjsg u32 bapm_flags; 53*7ccd5a2cSjsg 54*7ccd5a2cSjsg u8 Dpm0PgNbPsLo; 55*7ccd5a2cSjsg u8 Dpm0PgNbPsHi; 56*7ccd5a2cSjsg u8 DpmXNbPsLo; 57*7ccd5a2cSjsg u8 DpmXNbPsHi; 58*7ccd5a2cSjsg 59*7ccd5a2cSjsg u32 vclk_low_divider; 60*7ccd5a2cSjsg u32 vclk_high_divider; 61*7ccd5a2cSjsg u32 dclk_low_divider; 62*7ccd5a2cSjsg u32 dclk_high_divider; 63*7ccd5a2cSjsg }; 64*7ccd5a2cSjsg 65*7ccd5a2cSjsg #define TRINITY_NUM_NBPSTATES 4 66*7ccd5a2cSjsg 67*7ccd5a2cSjsg struct trinity_uvd_clock_table_entry 68*7ccd5a2cSjsg { 69*7ccd5a2cSjsg u32 vclk; 70*7ccd5a2cSjsg u32 dclk; 71*7ccd5a2cSjsg u8 vclk_did; 72*7ccd5a2cSjsg u8 dclk_did; 73*7ccd5a2cSjsg u8 rsv[2]; 74*7ccd5a2cSjsg }; 75*7ccd5a2cSjsg 76*7ccd5a2cSjsg struct trinity_sys_info { 77*7ccd5a2cSjsg u32 bootup_uma_clk; 78*7ccd5a2cSjsg u32 bootup_sclk; 79*7ccd5a2cSjsg u32 min_sclk; 80*7ccd5a2cSjsg u32 dentist_vco_freq; 81*7ccd5a2cSjsg u32 nb_dpm_enable; 82*7ccd5a2cSjsg u32 nbp_mclk[TRINITY_NUM_NBPSTATES]; 83*7ccd5a2cSjsg u32 nbp_nclk[TRINITY_NUM_NBPSTATES]; 84*7ccd5a2cSjsg u16 nbp_voltage_index[TRINITY_NUM_NBPSTATES]; 85*7ccd5a2cSjsg u16 bootup_nb_voltage_index; 86*7ccd5a2cSjsg u8 htc_tmp_lmt; 87*7ccd5a2cSjsg u8 htc_hyst_lmt; 88*7ccd5a2cSjsg struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table; 89*7ccd5a2cSjsg struct sumo_vid_mapping_table vid_mapping_table; 90*7ccd5a2cSjsg u32 uma_channel_number; 91*7ccd5a2cSjsg struct trinity_uvd_clock_table_entry uvd_clock_table_entries[4]; 92*7ccd5a2cSjsg }; 93*7ccd5a2cSjsg 94*7ccd5a2cSjsg struct trinity_power_info { 95*7ccd5a2cSjsg u32 at[SUMO_MAX_HARDWARE_POWERLEVELS]; 96*7ccd5a2cSjsg u32 dpm_interval; 97*7ccd5a2cSjsg u32 thermal_auto_throttling; 98*7ccd5a2cSjsg struct trinity_sys_info sys_info; 99*7ccd5a2cSjsg struct trinity_pl boot_pl; 100*7ccd5a2cSjsg u32 min_sclk_did; 101*7ccd5a2cSjsg bool enable_nbps_policy; 102*7ccd5a2cSjsg bool voltage_drop_in_dce; 103*7ccd5a2cSjsg bool override_dynamic_mgpg; 104*7ccd5a2cSjsg bool enable_gfx_clock_gating; 105*7ccd5a2cSjsg bool enable_gfx_power_gating; 106*7ccd5a2cSjsg bool enable_mg_clock_gating; 107*7ccd5a2cSjsg bool enable_gfx_dynamic_mgpg; 108*7ccd5a2cSjsg bool enable_auto_thermal_throttling; 109*7ccd5a2cSjsg bool enable_dpm; 110*7ccd5a2cSjsg bool enable_sclk_ds; 111*7ccd5a2cSjsg bool enable_bapm; 112*7ccd5a2cSjsg bool uvd_dpm; 113*7ccd5a2cSjsg struct radeon_ps current_rps; 114*7ccd5a2cSjsg struct trinity_ps current_ps; 115*7ccd5a2cSjsg struct radeon_ps requested_rps; 116*7ccd5a2cSjsg struct trinity_ps requested_ps; 117*7ccd5a2cSjsg }; 118*7ccd5a2cSjsg 119*7ccd5a2cSjsg #define TRINITY_AT_DFLT 30 120*7ccd5a2cSjsg 121*7ccd5a2cSjsg /* trinity_smc.c */ 122*7ccd5a2cSjsg int trinity_dpm_bapm_enable(struct radeon_device *rdev, bool enable); 123*7ccd5a2cSjsg int trinity_dpm_config(struct radeon_device *rdev, bool enable); 124*7ccd5a2cSjsg int trinity_uvd_dpm_config(struct radeon_device *rdev); 125*7ccd5a2cSjsg int trinity_dpm_force_state(struct radeon_device *rdev, u32 n); 126*7ccd5a2cSjsg int trinity_dpm_n_levels_disabled(struct radeon_device *rdev, u32 n); 127*7ccd5a2cSjsg int trinity_dpm_no_forced_level(struct radeon_device *rdev); 128*7ccd5a2cSjsg int trinity_dce_enable_voltage_adjustment(struct radeon_device *rdev, 129*7ccd5a2cSjsg bool enable); 130*7ccd5a2cSjsg int trinity_gfx_dynamic_mgpg_config(struct radeon_device *rdev); 131*7ccd5a2cSjsg void trinity_acquire_mutex(struct radeon_device *rdev); 132*7ccd5a2cSjsg void trinity_release_mutex(struct radeon_device *rdev); 133*7ccd5a2cSjsg 134*7ccd5a2cSjsg #endif 135