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Searched refs:constrainOperandRegClass (Results 1 – 17 of 17) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMFastISel.cpp304 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_r()
326 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rr()
327 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rr()
353 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_ri()
509 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0); in ARMMaterializeInt()
582 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0); in ARMMaterializeGV()
659 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0); in fastMaterializeAlloca()
1051 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1); in ARMEmitStore()
1127 SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0); in ARMEmitStore()
1264 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0); in SelectBranch()
[all …]
H A DARMCallLowering.cpp485 MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass( in lowerCall()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1901 Register FastISel::constrainOperandRegClass(const MCInstrDesc &II, Register Op, in constrainOperandRegClass() function in FastISel
1932 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_r()
1954 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
1955 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
1978 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrr()
1979 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrr()
1980 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrr()
2005 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_ri()
2028 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rii()
2073 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rri()
[all …]
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h102 Register constrainOperandRegClass(const MachineFunction &MF,
121 Register constrainOperandRegClass(const MachineFunction &MF,
H A DInstructionSelectorImpl.h1091 constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC, MO); in executeMatchTable()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1142 constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx)); in addLoadStoreOperands()
1144 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1)); in addLoadStoreOperands()
1333 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1334 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rr()
1378 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1419 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
1420 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rs()
1463 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rx()
1464 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rx()
2073 SrcReg = constrainOperandRegClass(II, SrcReg, 0); in emitStoreRelease()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostSelectOptimize.cpp218 constrainOperandRegClass(MF, *TRI, MRI, *TII, *RBI, II, II.getDesc(), in optimizeNZCVDefs()
H A DAArch64CallLowering.cpp1096 constrainOperandRegClass(MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(), in lowerTailCall()
1230 constrainOperandRegClass(MF, *TRI, MRI, *Subtarget.getInstrInfo(), in lowerCall()
H A DAArch64InstructionSelector.cpp2695 constrainOperandRegClass(MF, TRI, MRI, TII, RBI, *NewI, in select()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp53 Register llvm::constrainOperandRegClass( in constrainOperandRegClass() function in llvm
105 Register llvm::constrainOperandRegClass( in constrainOperandRegClass() function in llvm
148 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *OpRC, in constrainOperandRegClass()
185 constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), MO, OpI); in constrainSelectedInstRegOperands()
/openbsd-src/gnu/llvm/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp207 constrainOperandRegClass(MF, *TRI, MRI, *STI.getInstrInfo(), in lowerCall()
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DFastISel.h464 Register constrainOperandRegClass(const MCInstrDesc &II, Register Op,
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86CallLowering.cpp376 MIB->getOperand(0).setReg(constrainOperandRegClass( in lowerCall()
H A DX86FastISel.cpp217 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg, in addFullAddress()
642 ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1); in X86FastEmitStore()
3964 Register IndexReg = constrainOperandRegClass(Result->getDesc(), in tryToFoldLoadIntoMI()
3985 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrrr()
3986 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrrr()
3987 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrrr()
3988 Op3 = constrainOperandRegClass(II, Op3, II.getNumDefs() + 3); in fastEmitInst_rrrr()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp1291 MIB->getOperand(0).setReg(constrainOperandRegClass( in lowerTailCall()
1402 MIB->getOperand(1).setReg(constrainOperandRegClass( in lowerCall()
H A DAMDGPUInstructionSelector.cpp516 SrcReg = constrainOperandRegClass(*MF, TRI, *MRI, TII, RBI, I, in selectG_EXTRACT()
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp2128 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
2129 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()