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Searched refs:ValReg (Results 1 – 14 of 14) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp79 unsigned ValReg; in EmitTargetCodeForMemset() local
86 ValReg = X86::EAX; in EmitTargetCodeForMemset()
91 ValReg = X86::RAX; in EmitTargetCodeForMemset()
97 ValReg = X86::AX; in EmitTargetCodeForMemset()
102 ValReg = X86::AL; in EmitTargetCodeForMemset()
112 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl, AVT), in EmitTargetCodeForMemset()
H A DX86FastISel.cpp83 bool X86FastEmitStore(EVT VT, unsigned ValReg, X86AddressMode &AM,
479 bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, X86AddressMode &AM, in X86FastEmitStore() argument
499 .addReg(ValReg).addImm(1); in X86FastEmitStore()
500 ValReg = AndResult; in X86FastEmitStore()
642 ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1); in X86FastEmitStore()
645 addFullAddress(MIB, AM).addReg(ValReg); in X86FastEmitStore()
689 Register ValReg = getRegForValue(Val); in X86FastEmitStore() local
690 if (ValReg == 0) in X86FastEmitStore()
693 return X86FastEmitStore(VT, ValReg, AM, MMO, Aligned); in X86FastEmitStore()
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/
H A DMIPatternMatch.h143 std::optional<ValueAndVReg> &ValReg; member
144 GCstAndRegMatch(std::optional<ValueAndVReg> &ValReg) : ValReg(ValReg) {} in GCstAndRegMatch()
146 ValReg = getIConstantVRegValWithLookThrough(Reg, MRI); in match()
147 return ValReg ? true : false; in match()
151 inline GCstAndRegMatch m_GCst(std::optional<ValueAndVReg> &ValReg) { in m_GCst() argument
152 return GCstAndRegMatch(ValReg); in m_GCst()
H A DCallLowering.h312 Register extendRegister(Register ValReg, CCValAssign &VA,
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp1135 Register CallLowering::ValueHandler::extendRegister(Register ValReg, in extendRegister() argument
1142 return ValReg; in extendRegister()
1146 return ValReg; in extendRegister()
1150 const LLT ValRegTy = MRI.getType(ValReg); in extendRegister()
1155 ValReg = MIRBuilder.buildPtrToInt(IntPtrTy, ValReg).getReg(0); in extendRegister()
1164 return ValReg; in extendRegister()
1166 auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg); in extendRegister()
1171 MIRBuilder.buildSExt(NewReg, ValReg); in extendRegister()
1176 MIRBuilder.buildZExt(NewReg, ValReg); in extendRegister()
H A DLegalizerHelper.cpp4045 Register ValReg = LdStMI.getReg(0); in reduceLoadStoreWidth() local
4047 LLT ValTy = MRI.getType(ValReg); in reduceLoadStoreWidth()
4062 if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs, in reduceLoadStoreWidth()
4119 insertParts(ValReg, ValTy, NarrowTy, NarrowRegs, in reduceLoadStoreWidth()
7273 Register ValReg = MI.getOperand(ValRegIndex).getReg(); in lowerReadWriteRegister() local
7274 const LLT Ty = MRI.getType(ValReg); in lowerReadWriteRegister()
7283 MIRBuilder.buildCopy(ValReg, PhysReg); in lowerReadWriteRegister()
7285 MIRBuilder.buildCopy(PhysReg, ValReg); in lowerReadWriteRegister()
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp380 MachineBasicBlock *MBB, Register ValReg, in insertSext() argument
382 BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg) in insertSext()
383 .addReg(ValReg) in insertSext()
385 BuildMI(MBB, DL, TII->get(RISCV::SRA), ValReg) in insertSext()
386 .addReg(ValReg) in insertSext()
/openbsd-src/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArchExpandAtomicPseudoInsts.cpp351 MachineBasicBlock *MBB, Register ValReg, in insertSext() argument
353 BuildMI(MBB, DL, TII->get(LoongArch::SLL_W), ValReg) in insertSext()
354 .addReg(ValReg) in insertSext()
356 BuildMI(MBB, DL, TII->get(LoongArch::SRA_W), ValReg) in insertSext()
357 .addReg(ValReg) in insertSext()
/openbsd-src/gnu/llvm/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp303 createNewIdReg(Register ValReg, unsigned Opcode, MachineRegisterInfo &MRI, in createNewIdReg() argument
306 SPIRVType *SpvType = GR.getSPIRVTypeForVReg(ValReg); in createNewIdReg()
316 if (MRI.getType(ValReg).isPointer()) { in createNewIdReg()
320 } else if (MRI.getType(ValReg).isVector()) { in createNewIdReg()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMAsmPrinter.cpp1947 Register ValReg = MI->getOperand(1).getReg(); in emitInstruction() local
1951 .addReg(ValReg) in emitInstruction()
1958 .addReg(ValReg) in emitInstruction()
1961 .addReg(ValReg) in emitInstruction()
1968 .addReg(ValReg) in emitInstruction()
2013 Register ValReg = MI->getOperand(1).getReg(); in emitInstruction() local
2017 .addReg(ValReg) in emitInstruction()
2027 .addReg(ValReg) in emitInstruction()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1187 Register ValReg = MI.getOperand(0).getReg(); in legalizeLoadStore() local
1188 const LLT ValTy = MRI.getType(ValReg); in legalizeLoadStore()
1201 ValReg, {NewI->getOperand(0), NewI->getOperand(1)}); in legalizeLoadStore()
1233 auto Bitcast = MIRBuilder.buildBitcast(NewTy, ValReg); in legalizeLoadStore()
1237 MIRBuilder.buildBitcast(ValReg, NewLoad); in legalizeLoadStore()
H A DAArch64InstructionSelector.cpp2848 Register ValReg = LdSt.getReg(0); in select() local
2849 if (MRI.getType(ValReg).getSizeInBits() == 64 && MemSizeInBits != 64) { in select()
2872 const Register ValReg = LdSt.getReg(0); in select() local
2873 const LLT ValTy = MRI.getType(ValReg); in select()
2874 const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI); in select()
2887 .addReg(ValReg, 0, SubReg) in select()
5839 Register ValReg = I.getOperand(2).getReg(); in selectIntrinsic() local
5853 auto PAC = MIB.buildInstr(Opcode, {DstReg}, {ValReg}); in selectIntrinsic()
5866 Register ValReg = I.getOperand(2).getReg(); in selectIntrinsic() local
5873 MIB.buildInstr(Opcode, {DstReg}, {ValReg}); in selectIntrinsic()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp1561 Register ValReg = MI.getOperand(3).getReg(); in selectDSOrderedIntrinsic() local
1564 .addReg(ValReg) in selectDSOrderedIntrinsic()
3002 Register ValReg = MI.getOperand(2).getReg(); in selectG_INSERT_VECTOR_ELT() local
3006 LLT ValTy = MRI->getType(ValReg); in selectG_INSERT_VECTOR_ELT()
3011 const RegisterBank *ValRB = RBI.getRegBank(ValReg, *MRI, TRI); in selectG_INSERT_VECTOR_ELT()
3028 !RBI.constrainGenericRegister(ValReg, *ValRC, *MRI) || in selectG_INSERT_VECTOR_ELT()
3053 .addReg(ValReg) in selectG_INSERT_VECTOR_ELT()
3063 .addReg(ValReg) in selectG_INSERT_VECTOR_ELT()
H A DAMDGPULegalizerInfo.cpp2620 Register ValReg = MI.getOperand(0).getReg(); in legalizeLoad() local
2621 LLT ValTy = MRI.getType(ValReg); in legalizeLoad()
2656 B.buildTrunc(ValReg, WideLoad).getReg(0); in legalizeLoad()
2664 B.buildExtract(ValReg, WideLoad, 0); in legalizeLoad()
2669 B.buildDeleteTrailingVectorElements(ValReg, WideLoad); in legalizeLoad()